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Data Objects

The document discusses data objects in VHDL, including constants, signals, variables, and files. It explains the similarities and differences between these objects, their declarations, and their usage within VHDL programming. Additionally, it highlights the role of files in enabling communication between VHDL designs and the host environment.

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2 views

Data Objects

The document discusses data objects in VHDL, including constants, signals, variables, and files. It explains the similarities and differences between these objects, their declarations, and their usage within VHDL programming. Additionally, it highlights the role of files in enabling communication between VHDL designs and the host environment.

Uploaded by

ravipandey1729
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Advanced Digital System Design

Data Objects

Dr. Dipali Borakhade


Assistant professor
St. Vincent Pallotti college of
engineering and technology ,
Nagpur
Data
objects

Constants Signals Variables


File
(Global) (Global) (Local)
Signal

q The use of constants and variables in VHDL is similar to what you are already familiar
with from other programming languages.
q Signals usually represent voltages on wires. But you can also use a signal in place of a
variable. Sometimes it may not matter if you use a signal or a variable.
q Other times there may be subtle reasons for using one over the other.
q The signal represents interconnection wires between ports
q it may be declared in the declaration part of Signal objects are typically used to
model wires and flip-flops

signal signal_name : signal_type;


Signal assignment: <=
Signal

signal CLOCK ;
signal DATA_BUS: BIT_VECTOR(0 to 7);
signal GATE_DELAY: TIME := 10 ns;
Variable

q The variable locally stores temporary data and it is used only


inside a sequential statement that means process , function ,
procedures
q The variable is visible only inside processes and subprograms
in which it is declared.

variable variable_name : variable_type;


Variable assignment: :=
Constant

qThe constant names specific values to make the model better documented and
easy to update.
qThe constant can be declared in all the declarative VHDL statement,
qsequential
qconcurrent
qIt may be declared in the declaration section of packages, entities, architectures,
processes, subprograms and blocks
q An object of constant class can hold a single value of a given type. This
value is assigned to the object before simulation starts and the value
cannot be changed during the course of the simulation.
constant RISE_TIME: TIME := 10ns;
constant BUS_WIDTH: INTEGER := 8;
q The value of the constant has not been specified, called as a deferred
constant and it can appear only inside a package declaration. The
complete constant declaration with the associated value must appear in
the corresponding package body.
constant NO_OF_INPUTS: INTEGER;
This example highlights the difference
between signals and variables
ARCHITECTURE test1 OF mux IS ARCHITECTURE test2 OF mux IS
SIGNAL x : BIT := '1'; SIGNAL y : BIT := '0';
SIGNAL y : BIT := '0'; BEGIN
BEGIN PROCESS (in_sig, y)
PROCESS (in_sig, x, y) VARIABLE x : BIT := '1';
BEGIN BEGIN
x <= in_sig XOR y; x := in_sig XOR y;
y <= in_sig XOR x; y <= in_sig XOR x;
END PROCESS; END PROCESS;
END test1; END test2;
File

q Files provide a way for a VHDL design to communicate with the host
environment.
q File declarations make a file available for use to a design.
q Files can be opened for reading and writing.
q It is used only in test bench; in fact File type cannot be implemented in
hardware.
q In order to use the FILE type you shall include the TextIO package that
contains all procedures and functions that allow you to read from and
write to formatted text files.
Thank
You

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