Computer architecture topologies refer to the arrangement and interconnection of various

components within a computer system. These topologies play a crucial role in determining
performance, scalability, and fault tolerance. These topologies have diverse applications
depending on the system requirements, balancing trade-offs between performance, scalability,
and fault tolerance. Here are some common topologies:

. Linear Array

 Description: A one-dimensional arrangement of processing elements (PEs) where each

element is connected to its immediate neighbors.
 Advantages: Simple structure; easy to implement and understand.
 Disadvantages: Limited scalability and can become a bottleneck as the number of PEs
increases.
 Applications: Suitable for certain parallel computing tasks, like sorting and searching.

 This is a most elementary interconnection design. In this processors are linked in a linear
one-dimensional array. The first and last processors are linked with one adjacent
processor and the middle processing components are linked with two adjacent processors.
It is a one-dimensional interconnection network.

2. Ring

 Description: Each processing element is connected to two others, forming a closed loop.
 Advantages: Simple and efficient for data transmission; each node has equal access.
 Disadvantages: A single point of failure can disrupt the entire network.
 Applications: Often used in networked systems and certain parallel processing
architectures.

 This is a simple linear array where the end nodes are linked. It is similar to a mesh with
wrap-around connections. The data transfer in a ring is generally in one direction.
3. Chordal Ring

 Description: An extension of the ring topology, where additional connections (chords)

are added between non-adjacent nodes.
 Advantages: Reduces the average path length between nodes, enhancing communication
efficiency.
 Disadvantages: More complex than a simple ring; increased overhead for managing
additional connections.
 Applications: Useful in distributed computing and peer-to-peer networks.

4. Star

 Description: All processing elements are connected to a central node or hub.

 Advantages: Easy to manage and troubleshoot; failure of one node doesn’t affect others.
 Disadvantages: If the central hub fails, the whole system is affected.
 Applications: Common in local area networks (LANs) and client-server architectures.

 The star connection is another simple and low-cost (C=N-1) topology as shown in the
figure which has the same poor bisection width (B=1) and arc connectivity (A=1)
parameters as the linear array but the diameter is radically improved (D=2).
5. Tree

 Description: A hierarchical structure with a root node and child nodes, resembling an
inverted tree.
 Advantages: Efficient for hierarchical data representation; can be scalable.
 Disadvantages: If the root node fails, it can disrupt the entire network.
 Applications: Used in various applications like file systems, database indexing, and
networking.

 In the tree interconnection network, processors are organized in a complete binary tree
scheme.

 Fat tree: It is a changed version of the tree network. In this network, the bandwidth of the
edge improves towards the root. It is a more sensible simulation of the normal tree where
branches get deep towards the root.

6. 2D Mesh

 Description: A grid-like topology where each node is connected to its four (or sometimes
eight) neighboring nodes.
 Advantages: High connectivity and fault tolerance; data can take multiple paths.
  Disadvantages: Can be complex to manage; performance can degrade with increased
load.
 Applications: Common in parallel computing and multi-core processors.

It is a two-dimensional network. In this, all processing components are organized in a

two-dimensional grid. The processor in rows i and column j are indicated by PEi.
The processors on the corner can connect to two nearest neighbors i.e. PE00 can connect
with PE01 and PE10. The processor on the boundary can connect to 3 adjacent processing
elements i.e. PE01 can interact with PE00, PE02, and PE11 and internally placed processors
can connect with 4 adjacent processors i.e. PE11 can connect with PE01, PE10,
PE12, and PE21.

7. Barrel Shifter

 Description: A specialized circuit that can shift data left or right through a set of
connected registers, wrapping around when the end is reached.
 Advantages: Efficient for bit manipulation and arithmetic operations.
 Disadvantages: Limited to specific operations; not a general-purpose topology.
 Applications: Used in ALUs and digital signal processing.

A barrel shifter is a digital circuit used to shift a data word (usually a binary number) left or
right by a specified number of bit positions in a single operation. This is accomplished without
the need for multiple clock cycles, making it efficient for certain computational tasks. Here's a
deeper look into its structure and applications:

Characteristics of Barrel Shifter

1. Functionality:
o Left Shift: Moves all bits in the data word to the left, filling the vacated bits with
zeros. For example, shifting 1011 left by one results in 0110.
 o Right Shift: Moves all bits to the right. For arithmetic right shifts, the sign bit
may be preserved (for signed numbers), while logical right shifts fill vacated bits
with zeros.
o Rotation: A barrel shifter can also rotate bits, meaning bits that are shifted out on
one end reappear on the opposite end.
2. Architecture:
o A typical barrel shifter consists of a series of multiplexers and logic gates. Each
stage of multiplexers can select between different shifted versions of the input
data.
o The number of stages corresponds to the number of bits being shifted, allowing
for shifts of any size up to the width of the input data.
3. Control:
o It includes control lines that determine how many positions to shift. The control
lines are typically binary, so for an nnn-bit data word, you need log⁡2(n)\
log_2(n)log2(n) bits to specify the shift amount.

Advantages

 Speed: Performs shifting operations in a single clock cycle, unlike traditional shift
registers that may require multiple cycles.
 Versatility: Capable of both shifting and rotating operations, making it suitable for
various arithmetic and logical functions.

Disadvantages

 Complexity: The circuit can become complex and large for wide data words, especially
if implemented in hardware.
 Area: More area on silicon compared to simpler shift registers.

Applications

 Arithmetic Logic Units (ALUs): Used for performing multiplication and division
operations, as well as bit manipulation tasks.
 Digital Signal Processing (DSP): Essential for fast data processing tasks, such as
filtering and convolution operations.
 Microcontrollers and Processors: Utilized in various computational tasks where
efficient data manipulation is necessary.

8. Hypercube

 Description: A multi-dimensional cube where each node is connected to other nodes

based on binary representations of their addresses.
 Advantages: Highly scalable and provides multiple paths for communication; efficient
for parallel processing.
  Disadvantages: Complexity in routing and higher overhead in managing connections.
 Applications: Widely used in high-performance computing and parallel processing
systems.

 3D CUBE: It is a 3-dimensional interconnection network. In this, the PE’s are organized

in a cube structure.

 A Hypercube interconnection network is an extension of a cube network. Hypercube

interconnection network for n ≥ 3, can be represented recursively as follows −
 For n = 3, it cube network in which nodes are assigned number 0, 1… 7 in binary. In
other words, one of the nodes is assigned a label 000, another one as 001…. and the final
node is 111.
 Thus any node can connect with any other node if their labels differ in exactly one place,
e.g., the node with label 101 can connect directly with 001, 000, and 111.

NOTE:

In a static network, the connection between input and output nodes is fixed and cannot be
modified. Static interconnection network cannot be reconfigured. Examples of this network
are linear array, ring, chordal ring, tree, star, fat tree, mesh, tours, systolic arrays, and
hypercube. The design space for static interconnection topologies is shown in the figure.
 Completely Connected Network

 This topology is ideal from the point of view of network diameter (D=1) since any two
nodes are directly connected. The cost (C=N (N-1)/2) and node degree (d=N-1)
parameters are prohibitive in building massively parallel computers based on this
topology.