Data Convestet (Pat-B)

-5Mot of the phyescal hantitiec cuch

veltage, cumrent teperature , prseskure eke
are o analog form.
An analo iga Pe difffcult to
tsanmit and store without noiee .
’ Herce for proessjn , tsantrnicGon and
stoga qe purposes, convenlet to
exprese o digital fors. qvee betteo
and seduces noce.
accataeyADC Pnalot to Digital Corvetes
DAC bigital to Arn alog Cornester
Basie DAC Technique
CmcB) To
d

(D)
Sehenatie of DAC
an n-it blnaryt wosd
accepte
(D- di dedodo) and Cormbied with the
reference vetlr geik) to gire analog outpuuk
can be ethez
dqnal The output af bAC
vettaqe Cursent
 -’ For vottage-output DAC (oo D/A covestos; )
Voz kFs (di2+ de+ -+dn)
whese Vo output vottaqe
VEs full-seale output
kscalinq factos vottnge
did-do n-bit btnont uord
d- msB (moet ignifcart Bt)
dn LeB CLeat signfcant BtE)
Tpes:
arse thsee baic DAC

( Binang weiqhted Reai ctor DAc

i ) R-2R addes DAC
(çt) Iovested R2R laddes DAC

Wefahted Reictors DAC:

(9 RA
To
Vo

R
dn

UceS
’ Thte Pe the simplest DAC Tt
anplifes with benany welqhted seetor netuosk
n-electromic witchee didasdodo

b?mart Rnput wosd.

controlled by lorary
’ Thece svitches aTe of stnqle-pole Double.
"TFroo (sPDT) tYpe. Tf binory Pnput to a
parbeular ewitch Ps ' t conecte the
seitance to refesence vottaqe cVa) and
ef Boput bet Pe to', the switcb
conecte
the setance to

’ The output cursent (To) fos an deal OpP-Amp

-+In

VRd
2R
t VR t VR d3 t r t Ve dy
2R
To Ve ( di'+ da
R dettd2)
output votage (o) acsoce Re
Voz-Io Rf -VR Re ( ditd,ttdo2
R
Fos Rf 2R and kel ,then
Vo - V R ( d 2 + d e + t d n

If negative referene vottage used, then

Vo VR ( d + de2 -tdn)

-’ The aralog output

ctaiscace Ppoximati Vk
for 3-bt
cwelghtzd,
seistorr DAC.
ool Input Code
 Drabacks!
CD Wide san 9e of reic tose ase used
As no of bits Poceaces, the
sechetance value al ko Pnceaces .
() Drffcult to fabicate large valuee of
Trteqrated Ctrcuit)
resictvss Prn Te C

(2) R-2B Laddes sAC:

’ wide sange of sesstose are
equired
boony wetqbted eeictos pe DAC.
hic be avoided bt ueng R-2R (addes
can
type DAC whese only tmo values of the
reistore ae Uced.

’ This techriqe Re wet &uited fos

faoricaBon .
The typica vale of Rramges
foonn 25kr to I o k .
2R

R R R
Vo MB LeB
didads
¿2R2R 22R 2R +

-VR ( Refesenee Veltnqe)

where the witch
Conider 3-bit DAC
Ex:
postio didads covrexpornd to bimot
word Loo
 Ctreuit can be simplifrer usng Thevenin'e
Cytvalent

2R $2R

node cc iven bt
Vottage at nede
Vea
(GR) (-Ve)
GR+2R)

Output vottage gien bg:

RI
Vo 2 Ve VFS
2

’ Hence the output votta qe(vo) ? Ve for

loo
binoy Tnput oomd
R
Vo
2f $2R
ladder DAC fos euoitch
R-2R
posiion oo1(didda)
4
 2R
32
7
2K

§2R
Eapivaent Cereure
cosseporntnq to binat
’ The soiteh postom t considered:
word
The clreuit einplified ueing cauiralent form :
Vottaqes at nodes A, B,c obtained by
^eeistor brnchee.

Outpt votage, Vo Ve)

Vo VR Vec

similas the
output voléage for
K-2R Qaddes
laddes ÞAC for other 3-bt blrt
are caleulated.

(2) Iovested R-2R addes DAC:

26

2R 28
Jda(sB) R

Iy

and Rr2R
Tn we?hted Reistos type DAC
laddes ttpe DAc, curent flowtng Pn he
enput data changee.
2 he excese
power die oipatiorn
and non-lnenity DAC
caucee

heating
Thie povbler carn be avoided
Po nvested R-2R laddes type DAC coropletely
Consdes 3-bit
Trvested RreR laddes type
DAC whese the postbo of meB and LeB

-’ Hee eaeb
each
Rnteschanqed
Rt of binany wosd Connects the
Cowespondng cuitch ethes to qrDnd (or)
to PnvesBn nput teoninal of Op- Arop
whtcb alo at vistual
’ Stnce both the teminale of switches d?
at qround poterttal the cusent
flootng thoough retancee con stant
and Bndependent of sw itcb pbation (oo
tndepzndenk of btny wond.
’ wh en switch di Pa ot loie o' ay to left
cUsret
through seie tos flowe to qround
and when Soitch di e at loie u'ics
iqht cussent thmough 28 ejtors simke
to vistual qound.
’ The curent divides
af the ndee. Thus cunet
qyaltg at each

conetamt Pn each branch of ladder.

 Ve
2R

2R 46 2

I3 2 Vg|4 Ve
2R 4

In: VR
(m-) 2R (2n-1)
Vo e -IoRf
In)
2 -Rf( I+I + I 3 t t
2 -Rf ( b 2R
Vet ba 2(2R)
Ve + b3 VR t
4 (25)
+ bn VR
2R
-Ve. Rf£( bi2 +b2+
mootbn)
R
then
Dutput voftage,
Vo a VR ( b + b a t - t b n 2 )

Cx: 3 bik DAC(Iovested R-2R) with the

binay nput LOO Re =R. dudod 2R
A R

2r orsmal VRsV
$2R $2R O2sm2R
2mA ma R.
diel dseo diao

Tol Vo

Voe VRCix2tOxox2) Noa2sV

2)
VR() = Gx 2 2SV
’ The Pnverting Rr2R Laddes DAC
of suntng Cusrernte and
the pcple
alko operates o cusent- mode.

Advantage voltages remaly

Since the laddes nde
constamt wtth changina Roput codes
Capacltam cec are
(o0) btnay worde} stat
not able to clow douwn effects n the
pesfoan ce of the

Note: The cuset throgb the feedback seictor

Uorent
R' the suvnming
the Pnput blnat wosd dependng
upon
A|D Covertes
Tha funchon of sDe (Aralo
(aralog to Digital corvertes)
Pe t oppoite to that of DAC.
accepte amalog lnput 'eltage tva and produce
oubut bivag wondDdidsds do)
Dzd+dstt

Analog d Digitad
Pnput
(Va)

fo: Scham atie of ADC

usually has tm additomal comto
An ADc
sOc (start of ConvesGon) to tel ADC
lnes
start the Cornves o and EOC
ohen to
anmounce whe
(end af Convesiom) output to
coNeShOm Re completed
’ bependirg upo the bype, of applcatior,
ADc'e are
devigned for
ollretly dive Les (o6) LED
entesfactna
 Clasificatio
’ The vaous types of ABes are foltousr :
Flach| Conp arator type ADC
(2) Countes tye ADC
(3) Succeutve Approrirnatlo type ADC
Duat- slope Abc
C) Placb| Pastlel Cornparator ADCI

enput

sLene
to
a line

pioritt
encodes

Flash Parallel Comparator ADC

 is the ainpe t pocesble A]D conveter.
Tt Re thefastest and mout expentve
tecmiae The clrcuit comprdiee of eelatve
divides network
S Op-Anp conparature and
cltne to line encodder (B-bt psoty encode).
node of eejstve divider netwosk
’ At each
covopaision vofta ge ?e araliable. (analog
loput vottag Va compared to the node
vottnqe).all tthe gectore of egual value
ince
the vottage lerele
lerele avliable at the nodes
dvided betwees the vefena nee
arse
eanatly qround.
vottage Va and
Compator
Coutput)
The coiuit corparea Va

anatog oput vottag la)

of the nodeva
with each VazVd, x=l
voltagee Vak Vd;x0
Va -vottage input
Advantag Vd’ nade rottaqe
’ TE hae hiah epeed
convession taks place imultaneouely
xathe
DRLadvantage!
than ceapatiatug
’ The no. of comparatoe reguired doule
for each added blt.
E. 2-bit 3 Comp, 3-bit7Covnp,4titi
 No: of co-m parators meauired= (a
where of bits
the alue of n, the more
the more comper
Larqes encoder

Tauth Table fos Flach Type ADe

Tnputgtnge
o to Vr D

1
to

to VB
(2) Succeuive Appwlmator ADC
’ Thts techmiqe Veny effelert code
seareh strateqy to commplete n-bit corverior
n-clock periode.
An 8-blt convertes reayires g-clk pulsee
to obtain desised digital output
(End atConvro
(Stast af lonvere

Yas SAR.
dida

dy
’decuse)

DAC
SA ADC
of
Block Dlagram
block diagram of Successive Approxator
ADe conte of DAC, cormparator and Gucceseive
approxinaBo Te qiater (SAR).
Te control imale SOe Cstart of co nversjon)
Pnitater A|D corver sdon proceec and EOc
(end of conve Son) atrated aftes the
Coropetson of ppeeee. The SAR e uced to
fnd the Teaulred value of each bit by
ti al and method
 Opesationy
’ w With
ith the avovad of soc connand, the SAR
sets the msB CdiaD with all othe bits to
Ber 6o that the tial code 2s |oo00o00

’ The output Vd of DAC Pe now Conpared

wth the analog Rnput Va Tf VaVd
ther 1000OOO0 lacc than the cosrect
digitad repreentatiors
’ ie meB is lo ft at ' and nent lowe
eignifearnt bik Re made 1? ond fusther
tested.
-’ Lf VasVd, then Pe greatex than
he corseck digital vepresentator So reset
mSB to o' and to nent lowes siqnif
cank bit:

This poce duse a epeoted for atl the

Eubriáuant bits
one at a tinne until al
bt poitons -have been tosted
outputof DAc e e e e Va the
cormpasatod changes ctate and take as
end of con vereon (E oc) command
Con
 eot
Cosseot dital Succesgve appoDRmato Coropartor
Tepresembtior Ra atVs.stfot output
|oloIO0

Succesedve approrirn atto cocorvereien teaance

One coYTion)
toput
Load
output Actyal

DAC

o
+
Hme
Þ|A Output vottage Seen to becorne
succestvely cloces to attua analog
tnput votag:
 output vottage becomes
be cones cuceesevely
closer to actual analog Roput veltage.
TE Tequtree eiht ctock pulces to etablleh
the accurate output eqardleas of value
of analo Pnput
’ An
An additioal clock ' putee Re ueed to load

the. output (reqardlese of value of analog

Poput) veqstes and retsitalige the. clsoult
vescatle and and supesor
Comnpared to all othes Conesters.

AD1Sa2t 28pRo DIP cmos package

12-bit AlD Comveskes ucmg
Succeseve appromatio
cloek pulee Pe
eaired for sAR
to compare eaeh bit An
A additonal clk
putee reqised to the egiter
poor to cOVerom

foo analog to digital

CoNeGion must depend both clk
period (T) and of brts(n)
Tea T(n+1)|
where Te comveron tme
T clk pesod
of bits
(8) Dual- Stope ADCI
ndisect method for AlD corveston
whese
an alog votage amd reference
votage are convested rrto timer perjoda
Roteqratos and then meaured
by an

bt courtes.
The speed of convess oo Re clous but the
accurat Rs

Vo

Sw

tost Contrl
GOce counte n
Functional Dlagrorn of Dual-slope Abc
Von Intagratos
Neclee, Autogur
’ tm)
Time

Tntgrate| Trtygate
Output wave
Inteqrated Output aefooo of
dud-slope ADe
 he naleg pare of the creutk cor ejete of
btgh Propeuk Propecanee hiffer (A1)) preci ei on
Pteqrtor (As) and vettuge coporator, ohile
digital part con &j cte of binay countex,
output tateh (eonésol logje) and oferene
vettage VR
Operation!
- The convester ftrct oteratea the analot
Rnput ciqnal Va for fxed dusation of 2n
elock persode. Then E Pnteqrates fotersnal
weferenee vettage vR of oppotite pofoity
polaiy
Until the Poteqsatos output ?e geo
’ he nunbes (N) of clock cyeles eayised
to the enterator to
Poportionall to value af Va avenged over
the Inteqrati on peiod
’ Befose the SOC cormnand aires , thesuwitch
sw e conncted to qround and
closed Any offet vottrge prerent n Aiy Azt
comparatos loop fter rtqatior, appeare
the capacito cAz
Caz ll the thechold
of the cornp aratvs Pe achteved
’whern Sw opens, CAz holde the vettage
veauired to keep, the offeet nulled. A the
adval of sOC coomand at ta ti, the Cortrol
logie opens sw and Connectc SwI to Va
and emablee the coutes statirg frmzeD
The clscult Uces a n-stage ipe counter
and ttherefore the
the countes recets to

aftes counting pulees.

’ The anateg vottage a e Rnteqrated for a
fxed number of 2 counte of clk pulcee
aftes which courtes oecet to geoD T the
clk period Pe'T', the poteqration takes place
fos time Tie2T and output Pe negative

The counts recets Pteelf to 3er0 at end

comnected
of Poteval T amd cwitch sw).e
to eference voftge cv6) The output voftago

as vo Pe negatre, output of cornparat

e pocitve and contol (ogie aloooe the clk
pulee to be courted. But, when Vo becomee
at tzts, the control logic Peeuec
an end af corveion ( EOc) conomand and
no
fuethes clk pulees entes the countes
’ The seading of the Counter at t t s e
poportienal to analog nput vottage Va
Te ta-tj = 2 courts
clk rte
tz-tz digital count(N)
clk ste
For an

() to VI
Outqut votkaqe Vo oi be eaal
at Prnctant t and qve
)Va ta-ti)
Veténge v Pe olto qven by:
-t)

Gva ta-b):
Valtart) Vkt-t)
uloctitute, (ty-k)2 and tar)
Val) (VR)N
2)
Vaz(ue)[
Advantages
prvportional to Ne Prdependint o R,caT:
() Va Pe rejecton to ac eiqnale
() Povides ercellet noce
DIsadrantage:
corveion time.
Long