UNIT – IV: Architecture of 8051

1.1 Introduction
Microprocessors vs. Microcontrollers
 Microprocessor
 The word microprocessor, in a broader sense a Central Processing Unit (CPU) only.
 The functional blocks like memory and other peripherals are to be connected externally
to a microprocessor chip to form a complete microprocessor board. The system, which is
built this way, is called a “Single-Board Microcomputer”.
example 8085, 8086 and 80486 microprocessors.
 Microcontroller
 For the applications like design automation, designer needs a device which has all the
functional blocks inside a single IC.
 Therefore, the concept of “Single chip” microcomputers came into reality.
 Single-chip microcomputers are ‘Microcontrollers’.
 The examples are Intel MCS-51, PIC family by Microchip, Atmel 89CXX, 89CXX51.
 These microcontrollers used for general-purpose applications in the sense that they are
user programmable and have functional blocks suitable to meet a more general design
requirement.
The general structure of microprocessor and microcontroller is shown in figure 4.1.

Fig. 4.1 General structure of microprocessor and microcontroller

Merits of microcontroller over microprocessor
 The fixed amount of on-chip ROM, RAM, and I/O ports makes them ideal for
applications in which cost and space are critical.
 Less wiring complexity.
 More reliable
 Low power dissipation
 Basic building block of an embedded system is a microcontroller.
Criteria for Choosing a Microcontroller
1. Meeting the computing needs of the task at hand efficiently and cost effectively
 Speed
 Packaging
 Power consumption
 The amount of RAM and ROM on chip
 The number of I/O pins and the timer onchip
 How easy to upgrade to higher performance or lower power-consumption versions
 Cost per unit
2. Availability of software development tools, such as compilers, assemblers, and debuggers
3. Wide availability and reliable sources of the microcontroller
1.2 OVERVIEW OF 8051 MICROCONTROLLER
Figure 4.2 shows a general functional block diagram of a microcontroller.

Fig. 4.2 Functional block diagram of a microcontroller.

1.2.1 Features
The Intel MCS-51 family of microcontrollers consists of various devices and versions.
The salient features of 8051 microcontrollers are given below.
 MCS-51 is a family of 8-bit microcontrollers by Intel, designed around HMOS
technology and CHMOS versions also available.
 8-bit CPU.
 On-chip clock oscillator.
 Operating frequency is 12 MHZ.
 Available in ROM/EPROM/EEPROM versions.
 4K bytes of on-chip program memory.
 128 bytes of on-chip data random access memory.
 4 I/O ports
 Two 16-bit timers or counters
 Full duplex serial port
 Five vector interrupt structure with two priority levels
1.3 ARCHITECTURE OF 8051
The block diagram of 8051 microcontroller is shown in figure 4.3.
 Arithmetic and Logic Unit (ALU)
 It performs arithmetic and logic operation on 8-bit operands.
 arithmetic operations such as addition, subtraction, multiplication, division, etc.
 logical operations such AND, OR, NOT, EX-OR, etc.
 In most of the instructions to perform arithmetic operations, one of the operand must
be A register.
 ALU affects various flags namely carry, auxiliary carry, overflow, and parity flags of
status register.
 Instruction decoder and control
 The timing and control unit is having instruction decoder and control unit.
 When an instruction is fetched from program memory it is loaded into the instruction
register.
 The decoder decodes the instruction and identifies the type of operation.
 The instruction register is not programmable.
  The timing generation and control unit synchronizes all the microcontroller
operations with the clock and generates control signals necessary for communication
between the processor and peripherals.

Fig. 4.3 Block diagram of 8051 microcontroller

 Oscillator
 All the 8051 family members use an external crystal for oscillator function.
 the crystal frequency is 11.0592 MHz.
 The slight lower frequency allows one of the timers to generate clock frequency for
the baud rate of 9600 baud for the operation of serial port.
1.4 REGISTER ORGANIZATION OF 8051
There are three types of registers in 8051
 General purpose or working registers
 Stack pointer and program counter
 Special function registers.
 General purpose or working registers
Accumulator, B-register and four register banks may be used as general purpose registers.
Table 4.1 General purpose or working registers.
Register symbol Description
Accumulator or A-register 8-bit
B-register 8-bit
R0 through R7 Bank 0: 00-07 H
(There are four register banks in the on-chip Bank 1: 08-0F H
RAM, each having 8-bit wide registers R0 Bank 2: 10-17 H
through R7) Bank 3: 18 -1FH
 Accumulator:
 8-bit accumulator is used by all the arithmetic and logical instructions.
 Referred as ‘A’ register.
 bit addressable register
 Also used in indexed addressing mode to access information from program
memory.
 B register (F0H):
 It is an 8-bit register having bit addressable capability
 Used during multiply and division operations.
 In multiplication operation, one of the 8-bit operand is stored in ‘B’ register.
 After the operation, it stores the higher byte of the result in B register.
 In division operation, it holds 8-bit divisor.
 After the operation remainder is stored in B register.
 Registers R0 through R7:
 8-bit registers are used as scratch pad registers.
 Four register banks each containing R0 through R7 registers.
 At any time only one bank can be selected by appropriate setting of bits in the
program status word (PSW).
  These register banks are located in the on-chip RAM.
Figure 4.4 shows the four register banks located in the on-chip RAM.

Fig 4.4 Four register banks and their locations in the On-Chip RAM
 Stack pointer and Program counter
 Stack pointer:
 8-bit register.
 It is incremented during push or call operations.
 Decremented during POP or return operation.
 Initialized anywhere in the available on-chip data.
 After the RESET operation, the stack pointer is initialized to 07 H.
 Program counter (PC):
 16 bit register, and it can address 64 K code bytes.
 The 16 bit program counter specifies the address of the next instruction to be
executed.
 After reset, PC will be set to 0000H and the CPU will start executing the first
execution stored at program memory location 0000H.
Table 4.2 shows the stack pointer and program counter and their addresses.
Table 4.2 Stack pointer and Program counter
Register symbol Register name Address
SP (8) Stack pointer 81 H
PC (16) Program Counter NO ADDR
 Special Function Registers (SFR)
These registers have some special functions like
 Controlling the timer/counter.
 Enabling interrupts.
  Controlling the serial port operations.
 The 128 bytes of on-chip additional RAM locations from 80H to 0FFH are reserved for
the special function registers (SFRs).
 There are 21 special function registers in the 8051.
Table 4.3 Special Function Registers.
SFR symbol Register name Address
ACC* Accumulator 0E0H
B* B-register 0F0H
P0* Port 0 80H
P1* Port 1 90H
P2* Port 2 0A0H
P3* Port 3 0B0H
IP* Interrupt priority control 0B8H
IE* Interrupt Enable Control 0A8H
TMOD Timer/Counter Mode Control 89H
T2CON (Only in 8052) Timer/Counter 2 control 0C8H
TCON* Timer/Counter control 88H
TH0 Timer/Counter 0 (high byte) 8CH
TL0 Timer/Counter 0 (low byte) 8AH
TH1 Timer/Counter 1 (high byte) 8DH
TL1 Timer/Counter 1 (low byte) 8BH
TH2 (only in 8052) Timer/Counter 2 (high byte) 0CDH
TL2 ( only in 8052) Timer/Counter 2 (low byte) 0CCH
RCAP2H (only in 8052) Timer/Counter 2 Capture register (high byte) 0CBH
RCAP2L (only in 8052) Timer/Counter 2 Capture register (low byte) 0CAH
SCON* Serial control 98H
SBUF Serial data buffer 99H
PCON Power control 97H
PSW* Program status word 0D0H
DPTR Data pointer
DPH Data pointer (high byte) 83H
DPL Data pointer (low byte) 82H
 Program Status Word:
  Program status word or simply PSW, is an 8-bit register
 It consists of carry, auxiliary carry, overflow, and parity flags,
 Also RS1 and RS0 for register bank selection.
 The PSW is a bit addressable register.
MSB LSB
C AC F0 RS1 RS0 OV ---- P
Fig. 4.5 Program status word
 Bit 7 (Carry/ Borrow flag) PSW.7:
 When two 8-bit operands are added, the result may exceed 8-bit and the
9th bit is copied in the carry bit.
 During subtraction, if the borrow occurs, the carry bits is set and otherwise
it is cleared.
 Similarly, SETB C and CLR C instructions can also change carry bit.
 Bit 6 (Auxiliary carry) PSW.6:
 Used for BCD operations
 Set when a carry generated from lower nibble to upper nibble
 Bit 5 (F0):
 F0 is available to user as a general purpose flag.
 This flag can be set/cleared by software.
 Bit 4 & 3: Register Bank select bits RS1 and RS0:
 These bits for selecting one of the four register banks.
 Each of these register banks consists of registers R0 through R7.
 When power up reset, bank 0 is selected.
Table 1.4 shows the address ranges of four register banks along with RS1 and
RS0 bits.
Table 4.4 Register Bank Select Bits
Register bank Address range in
RS1 RS0
selected the on-chip RAM
0 0 Bank 0 00-07 H
0 1 Bank 1 08-0F H
1 0 Bank 2 10-17 H
1 1 Bank 3 18-1F H
  Bit 2 (Over flow flag):
 When two signed numbers are added, if the result exceeds the destination,
overflow flag is set, else it is reset.
 Timer Registers:
 Two 16-bit Registers T0 and T1 (TH0, TL0), (TH1, TL1) to hold the count
value.
 TCON- to control the timer operations.
 TMOD-timer mode selection.
 Serial data Buffer (SBUF):
 This register holds the data that has to be transmitted through the serial port
and holds the data that is received.
1.5 I/O PORTS
 8051 has four 8-bit I/O ports, named as P0, P1, P2 and P3.
 Denoted as P0.0-P0.7, P1.0-P1.7, P2.0-P2.7, P3.0-P3.7
 Each port can be used as a single 8-bit port or single bit of each port can be
programmable
 Each port consists of a latch, an output driver and an input buffer.
Port 0
 A true bidirectional port as shown in figure 4.6.
 Can be configured as input or output port
 External pull up resistors are required if configured as an input port.
 Alternate function of this port as a time multiplexed address and data bus AD0-AD7.

Fig. 4.6 A true bidirectional port

Port 1, 2, 3
 A quasi bidirectional port as shown in figure 4.7.
  Can be configured as input or output port.
 Alternate functions of port 2 as higher order address bus while accessing external
memory (A8-A15).
 Alternate functions of port 3 as follows
P3.0 RXD serial input
P3.1 TXD serial output
P3.2 external interrupt
P3.3 external interrupt

P3.4 T0 timer/counter 0 external interrupt

P3.5 T1 timer/counter 1 external interrupt
P3.6 external data memory write strobe

P3.7 external data memory read strobe

Fig. 4.7 A Quasi bidirectional port

1.6 MEMORY ORGANIZATION
 The MCS-51 family of microcontrollers has Harvard architecture.
 Separate program (ROM) and data (RAM) memory spaces, and different sizes
supported.
 Internal program memory space is 4KB and extended up to 64KB by external
memory interfacing.
 Internal data memory space is 128Bytes and extended up to 64KB by external
memory interfacing.
Program Memory organization
 The 64K program memory space of 8051 is divided into internal and external
memory.
 If the pin is high, then 8051 executes from the internal program memory till the
address exceeds 0FFFH.
  locations 1000H through 0FFFFH are executed from the external memory portion.
 If pin is held low, then 8051 executes instructions from external memory only.

Fig.4.8 Program Memory organization

Data Memory organization
 The internal data memory of 8051 is 256 bytes and is divided into two parts.
1. lower 128 bytes (00H through 7FH) called as internal data RAM and is divided
in to three parts
a) 32 bytes for four register banks,
Bank 0 (00-07H)
Bank 1(08-0FH)
Bank 2(10-17H)
Bank 3(18-1FH)
b) 16 bytes (20-2FH) as bit addressable memory
c) Scratch pad RAM (30-7FH)
2. upper 128 bytes (80 through FFH) special function registers (SFRs).
Fig. 4.9 Data Memory organization
1.7 ADDRESSING MODES
The way of specifying the operand is called as an addressing mode, generally the operand may in
the instruction, as an immediate data, register or memory.
The different addressing modes supported by 8051 are classified as follows
1. Immediate and register addressing modes
a) Immediate addressing mode
b) Register addressing mode
2. Accessing memory using various addressing modes
a) Direct addressing mode
b) Register indirect addressing
c) Indexed addressing
3. Implicit addressing mode
Immediate addressing mode
 The source operand is a constant
 The immediate data must be preceded by the pound sign, “#”
 Used to load information into any registers, including 16-bit DPTR register
E.g: MOV A, #45 : A<- 45H
Register addressing mode
 Use registers to hold the data to be manipulated
 The source and destination registers must match in size
 The movement of data between Rn registers is not allowed
E.g: MOV A, B : A=B
MOV A, DPTR Invalid
MOV R4, R7 Invalid
Direct addressing mode
 The memory address of the operand is given as a part of the instruction as a source or
destination operand.
 The on chip 128 bytes of the RAM can be accessed with direct addressing mode and also
special function registers
 Direct addressing mode is only used to copy or retrieve the data from stack.
E.g: MOV A, 40 : A=[40]
Register indirect addressing mode
 A register is used as a pointer to data.
 Only registers R0 and R1 are used as a pointer, when internal RAM is accessed.
  To access external memory PC and DPTR are used as pointers.
E.g: MOV A, @R0 : A=[[R0]]
Indexed addressing
 Used to access the data elements of lookup table located in ROM space
E.g: MOVC A, @A+DPTR
 Used to access external data memory
E.g: MOVX A, @A+DPTR
 Used to access upper 128 bytes of on chip RAM
Implicit addressing mode
 No operand is specified in the instruction
 Instruction definition itself tells the operand
E.g: CMA-complement accumulator
1.8 INSTRUCTION SET OF 8051
Instruction:
 Command to the controller to specify the task to be performed
 Instruction is having two parts, opcode and operand
 Opcode specify the task to be performed
 Operand specify the location of data
 111 instructions supported by MCS-51.
 The instructions can further be classified as single-byte, two-byte and three-byte
instructions.
 45 single byte instructions
 45 two byte instructions
 17 three byte instructions.
The instruction set of MCS-51 is classified based on the type of operations as follows
 Data transfer instructions
 Arithmetic instructions
 Logical instructions
 Boolean variable manipulation instructions
 Program branch instructions
Data transfer instructions
 These instructions are used to copy the data from specified source to destination.
 The content of source will not be changed.
  No flags are affected
MOV A, Rn/direct/# data/@Ri
 The content of R0-R7 or direct address or immediate data or indirect address specified
with R0 or R1 is copied into accumulator.
E.g: MOV A, R2 A=R2 MOV A, 30 A=[30]
MOV A, #0FH A=0FH MOV A, @R1 A=[[R1]]
MOV Rn, A/direct/# data
 The content of accumulator or direct address or immediate data is copied into Rn.
E.g: MOV R2, A R2=A
MOV R3, 30 R3=[30]
MOV R7, #0FH R7=0FH
MOV direct, A/ Rn/direct/# data/@Ri
 The content of accumulator or Rn or direct address or immediate data or indirect address
is copied into direct memory address.
MOV @Ri, A/direct/# data
 The content of accumulator or Rn or direct address or immediate data copied into indirect
memory address.
MOV DPTR, #data16
 16 bit immediate data is copied to DPTR
 Lower order eight bits copied to DPL
 Higher order eight bits copied to DPH
E. g: MOV DPTR, #398FH; DPL=8FH, DPH=39H
MOVC A,@A+DPTR/@A+PC
 The code byte relative to DPTR or PC is copied to accumulator
MOVX A, @Ri/MOVX @Ri, A
 Copy the content of external RAM to accumulator/copy the content accumulator to
external RAM
 Only 8-bit address.
MOVX A, @DPTR/MOVX @DPTR, A
 Copy the content of external RAM to accumulator/copy the content accumulator to
external RAM
 16-bit address.
PUSH direct
 The stack pointer is incremented by one
  The content of memory is copied to stack memory.
E. g: PUSH 10H SP=SP+1; content of 10H is copied to stack memory
POP direct
 The data from stack is retrieved to direct memory address.
 For each byte transfer the stack pointer is decremented by one.
E. g: POP 10H content of stack memory is copied 10H ; SP=SP-1
XCH A, Rn/direct/@Ri
 The content of accumulator is exchanged with the contents of Rn or direct memory or
indirect memory location.
XCHD A, @Ri
 Exchange the lower nibble of accumulator with lower nibble of indirect address.
Arithmetic instructions
 These instructions are used to perform arithmetic operations like addition, subtraction,
multiplication, division, increment and decrement operations on specified operands.
ADD A, Rn/direct/@Ri/#data
 The accumulator contents are added with either the contents of register or direct address
or indirect address or immediate data.
 The result is stored in accumulator.
 All the flags are affected according to the result.
E. g: ADD A, B; A=A+B
ADDC A, Rn/direct/@Ri/#data
 The accumulator contents are added with either the contents of register or direct address
or indirect address or immediate data along with the carry flag.
 The result is stored in accumulator.
 All the flags are affected according to the result.
E. g: ADDC A, B; A=A+B+CF
SUBB A, Rn/direct/@Ri/#data
 The contents of register or direct address or indirect address or immediate data are
subtracted from content of accumulator along with the carry flag.
 The result is stored in accumulator.
 All the flags are affected according to the result.
E. g: SUBB A, B; A=A-B-CF
INC A/ Rn/direct/@Ri
INC DPTR
  The contents of accumulator or register or direct address or indirect address are
incremented by 1.
E. g: INC A; A=A+1
DEC A/ Rn/direct/@Ri
DEC DPTR
 The contents of accumulator or register or direct address or indirect address are
decremented by 1.
E. g: DEC A; A=A-1
MUL AB
 Mutiply the content of A register with B register
 Lower byte of product in register A and upper byte of the result in B register
DIV AB
 Divide the content of A by content of B
 Result: A <- Quotient, B <- remainder.
DAA Decimal adjust ACC.
 Used for BCD operations
Logical instructions
These instructions are used to perform logical operations like AND, OR XOR, NOT, COMARE,
shift and rotate operations on specified operands.
ANL A, Rn/direct/@Ri/#data
ANL direct, A/#data
 Bit by bit logical AND operation is performed between specified source and destination.
 Result is stored in destination.
ORL A, Rn/direct/@Ri/#data
ORL direct, A/#data
 Bit by bit logical OR operation is performed between specified source and destination.
 Result is stored in destination.
XRL A, Rn/direct/@Ri/#data
XRL direct, A/#data
 Bit by bit logical exclusive OR operation is performed between specified source and
destination.
 Result is stored in destination.
CLR A
 Clear the contents of accumulator
CPL A
 Complement the contents of accumulator
Boolean variable manipulation instructions
 Operands for Boolean variable manipulations are defined in the instruction.
 In case of two operand instructions, there is a destination bit and source bit.
CLR C Clear carry flag. CF=0
CLR bit Clear direct bit.
SETB C Set carry flag. CF=1
SETB bit Set direct bit
CPL C Compliment carry flag.
CPL bit Compliment direct bit.
ANL C, bit/bit direct bit or complement of direct bit is ANDed with carry flag.
ORL C, bit/bit direct bit or complement of direct bit is ORed with carry flag.
MOV C, bit direct bit is copied to carry flag.
MOV bit, C carry flag is copied to direct bit.
JC rel change the program sequence to relative address if carry flag is set.
JNC rel change the program sequence to relative address if carry flag is reset.
JB bit, rel change the program sequence to relative address if direct bit is set.
JNB bit, rel change the program sequence to relative address if direct bit is reset.
JBC bit,rel change the program sequence to relative address if direct bit is set and
clear the bit.
Program branch instructions
 Change the sequential execution of the program sequence
Classified as
1. Conditional branch: Change the program sequence if the specified condition is true
2. Unconditional branch: Change the program sequence independent of any condition
E. g: JUMP, CALL, and RET
 Jump instructions are classified as three types
1. SJMP(short jump): Transfer control within 256 bytes range
2. AJMP (absolute jump): Transfer control within 2K bytes range
3. LJMP (long jump): Transfer control to anywhere in 64KB of program memory
CALL instruction
 Used to call the sub routine program
 Two types of CALL instructions
 1. ACALL (Absolute call): Calling the subroutine in 2KB of program memory
2. LCALL (Long call): Calling the subroutine in 64KB of program memory
Conditional jump instructions
JZ rel: jump to the specified address if accumulator content is zero
CJNE A, direct, rel: compare the content of direct address with accumulator and change the
program sequence to relative address if not equal.
DJNZ Rn, rel: Decrement the content of Rn and change the program sequence to relative
address if not equal to zero.
1.9 INTERRUPTS
 A single microcontroller can serve several devices with the help of two methods
1. Polling
2. interrupts
Polling:
 The MC continuously monitors the status of given devices
 If the status is met then the MC service that device
 After completing first device go for the next device
 This is not the efficient method of using MC
Interrupt mechanism
 When a device needs the service, then it notify with some indication called as interrupt
 Then the MC interrupts its own operations and service the device
Steps in executing an interrupt
1. It completes the current instruction execution and saves the address of the next
instruction to the stack.
2. It also saves the current status of all the interrupts.
3. It jumps to a fixed location in memory, called the interrupt vector table, that holds the
address of the ISR
4. The microcontroller get the address of the ISR and jumps to it
5. It starts to execute the interrupt service subroutine until it reaches the last instruction of
the subroutine which is RETI
6. Upon executing the RETI instruction, the microcontroller returns to the main program.
Sources of interrupts
1. Reset – power-up reset
2. timer 0 over flow TF0
3. timer 1 over flow TF1
 4. External interrupt-INT0
5. External interrupt-INT1
6. Serial communication interrupt (TI or RI)

Interrupt vector table

 After reset, all interrupts are disabled.

 Interrupts must be enabled by software.
 Interrupt Enable (IE) register is used to enable or disable the interrupts
Interrupt Enable (IE) Register
 Special function register with an address of A8H
 Bit addressable register
 To enable the particular interrupt bit D7 of IE register must be set.
Figure 4.10 shows the format of interrupt enable register

Fig. 4.10 Format of IE register

EX0 IE.0 Enables or disables external interrupt 0
ET0 IE.1 Enables or disables timer 0 overflow interrupt
EX1 IE.2 Enables or disables external interrupt 1
ET1 IE.3 Enables or disables timer 1 overflow interrupt
ES IE.4 Enables or disables the serial port interrupt
ET2 IE.5 Enables or disables timer 2 overflow or
capture interrupt (8952)
IE.6 Not implemented, reserved for future use
EA IE.7 Disables all interrupts
E. g:
Show the instructions to (a) enable the serial interrupt, timer 0 interrupt, and external hardware
interrupt 1 (EX1), and (b) disable (mask) the timer 0 interrupt

Programming Timer interrupts

 If the timer interrupt in the IE register is enabled
 whenever the timer rolls over, TF is set
 the microcontroller is interrupted
 jumps to the interrupt vector table to service the ISR. The vector addresses are given in
figure 4.11.

Fig. 4.11 Interrupt vector addresses of timer interrupts

1.Write a program to generate 2 square waves-one of 5KHZ

frequency at pin P1.3 and another frequency 25KHZ at pin
p2.3.assume XTAL=22MHZ
ORG 0000h
LJMP MAIN
ORG 000B .......ISR for timer 0
CPL P1.3
RETI
ORG 001BH ....................ISR timer 1
CPL P2.3
RETI
ORG 0030H
MAIN: MOV TMOD,#22H
MOV IE,#8AH ......Enable timer 0 and timer 1 interrupts
MOV TH0,#48H
MOV TLO,#B6H
SETB TR0
SETB TR1
 WAIT: SJMP WAIT
END

Programming External hardware interrupts

 Two interrupts INT0 and INT1
 Two activation levels edge triggered and level triggered
 Default activation is level triggered
 To make edge triggered program the IT0 and IT1 bits of TCON register.
Figure 4.12 gives the structure of external hardware interrupts.
 Fig.4.12 External interrupts and vector addresses

Programming Serial Communication interrupt

 TI (transfer interrupt) is set when the last bit of the framed data, the stop bit, is
transferred, indicating that the SBUF register is ready to transfer the next byte.
The structure of serial communication interrupt is explored in figure 4.13
 RI (received interrupt) is raised when the entire frame of data, including the stop bit, is
received.

Fig. 4.13 Serial communication interrupt

Interrupt Priority
Figure 4.14 shows the interrupt priority register format.
 When more than one interrupt is enabled at a time, then the MC handles the interrupts
based on priority
 After power up the default priority is like this

 Priority is also programmable and it should be done with Interrupt Priority (IP) register
 Bit addressable register
 If bit=1, then highest priority
 Fig. 4.14 Format of IP register

PX0 IP.0 External interrupt 0 priority bit

PT0 IP.1 Timer 0 interrupt priority bit
PX1 IP.2 External interrupt 1 priority bit
PT1 IP.3 Timer 1 interrupt priority bit
PS IP.4 Serial port interrupt priority bit
PT2 IP.5 Timer 2 interrupt priority bit (8052 only)
IP.6 Reserved
IP.76 Reserved
1.10 TIMER/COUNTER
 A timer counts machine cycles and provide the reference time delay
 Counter counts the external events
 8051 is having two 16-bit timers namely Timer 0 and Timer1.
 Two 16-bit registers associated with these operations as To and T1
 They can be also accessed as a 8-bit registers as TH0-TL0 and TH1-TL1.
 The timers are counters are programmed through two SFRs, TMOD and TCON
TMOD Register
 Used for timer mode selection
 Byte addressable register
The structure of TMOD register is shown in figure 4.15.

Fig. 4.15 TMOD register format

 M1 and M0 is used for mode selection
 There are four modes of operation
M1 M0 MODE OPERATION
0 0 Mode0 13-bit timer
0 1 Mode1 16-bit timer
1 0 Mode2 8-bit auto reload
1 1 Mode3 Split timer mode
 Gate bit will specify whether timer counter is internal or external control.
  If gate=1, then the timer is controlled with external interrupt pin as well as TR0 or TR1 of
the corresponding timer.
 If gate=0, then the timer is controlled with no external control, under the control of TR0
or TR1 of the corresponding timer.
TCON Register
 To start a particular timer the run control bit TR bit should be set
 When over flows that is indicated with TF bit.

Fig. 4.16 TCON register format

The figure 4.17 illustrates the timer/counter selection and control.

Fig. 4.17 Timer/counter selection and control

Timer modes of operation
Mode 0:
 13 bit timer/counter
 The upper 8 bits of the T0/T1, i.e, TH0/TH1 are used
 The lower 5 bits of T0/T1, i.e, TL0/TL1 are used
Mode 1:
 It is a 16-bit timer
 it allows value of 0000 to FFFFH to be loaded into the timer’s register TL and TH
 After TH and TL are loaded with a 16-bit initial value, the timer must be started
 After the timer is started, it starts to count up until it reaches its limit of FFFFH
 When it rolls over from FFFFH to 0000, it sets high a flag bit called TF (timer flag) and
is shown in figure 4.18.
 Fig. 4.18 Mode 1 operation of 8051 timers
Mode 2:
 It is an 8-bit timer; therefore, it allows only values of 00 to FFH to be loaded into the
timer’s register TH
 After TH is loaded with the 8-bit value, the 8051 gives a copy of it to TL
 After the timer is started, it starts to count up by incrementing the TL register
 It counts up until it reaches its limit of FFH
 When it rolls over from FFH to 00, it sets high
1.11 SERIAL COMMUNICATION
In general computers can transfer the data in two ways is shown in figure 4.19.
1. Parallel data transfer:
 Group of wires will transfer the data with in a short distance range.
 Fastest data transfer
 Cost is high
2. Serial data transfer:
 Single wire is used to transfer the data to long distances.
 Bit by bit data transmission.
 Data transfer is in slower manner
 Cost is less

Fig. 4.19 Serial and parallel transfer of data

The microcontroller will transmit the parallel data with the help of buses. To transfer serial data
serial port is available (TXD, RXD).
Serial data communication uses two techniques to transfer serial data
1. Synchronous: Block of data is transmitted at a time
2. Asynchronous: Byte of data is transmitted at a time
Data transmission schemes
1. Simplex: One way data transmission from transmitter to receiver
2. Half Duplex: Bi directional data transfer, only one direction at a time
3. Full Duplex: Bidirectional, both the directions simultaneously.
Figure 4.20 shows the serial data transmission schemes.

Fig. 4.20 Data transmission schemes

 Asynchronous serial data communication is widely used for character-oriented

transmissions. And it is depicted in figure 4.21.
 Each character is placed in between start and stop bits, this is called framing
 The start bit is always one bit, but the stop bit can be one or two bits
 Asynchronous serial data communication is widely used for character-oriented
transmissions
 The start bit is always a 0 (low) and the stop bit(s) is 1 (high)
 Fig. 4.21 Asynchronous serial data transfer format
 The rate of data transfer in serial data communication is stated in bps (bits per second)
 Another widely used terminology for bps is baud rate-the number of signal changes per
second.
 Two registers are used for serial communication SBUF and SCON
SBUF Register
 8-bit byte addressable register
 Hold the serial data during transmission as well as reception
 Single register serves the transmit and receive purpose
SCON Register
 SCON is an 8-bit register.
 Bit addressable register.
 Used to program the start bit, stop bit, and data bits of data framing.

Fig. 4.22 SCON register format

SM0, SM1: used for mode selection
SM0 SM1 Mode Baud rate
0 0 Shift register fosc /12

0 1 8-bit UART Variable and set by timer 1

overflow rate
1 0 9-Bit UART fosc /64 or fosc /32

1 1 9-Bit UART Variable and set by timer 1

overflow rate
SM2: Enables multi processing capability
REN: To receive serial data on RXD line this pin should be high
TB8: This bit used to transmit the 8th bit
RB8: This bit used to receive the 8th bit
TI: When 8051 finishes the transfer of 8-bit character
 It set TI flag to indicate that it is ready to transfer another byte
 TI bit is raised at the beginning of the stop bit
RI: When 8051 receives data serially via RxD,
 It raises the RI flag bit to indicate that a byte has been received
 RI is raised halfway through the stop bit
Procedure to program serial port
1. TMOD register is loaded with the value 20H, indicating the use of timer 1 in mode
2 (8-bit auto-reload) to set baud rate.
2. The TH1 is loaded with one of the values to set baud rate for serial data transfer
3. The SCON register is loaded with the value 50H, indicating serial mode 1, where an 8-bit
data is framed with start and stop bits
4. TR1 is set to 1 to start timer 1
5. TI is cleared by CLR TI instruction
6. The character byte to be transferred serially is written into SBUF register
7. The TI flag bit is monitored with the use of instruction JNB TI,xx to see if the character
has been transferred completely
8. To transfer the next byte, go to step 5
The baud rate can be increased by programming one more SFR, PCON register.
PCON register
 8-bit register
 Byte addressable register
 After power-up SMOD bit is reset
 To increase the baud rate set the SMOD bit

Fig. 4.23 PCON register format

programs on Timers:
Write an ALP to generate a delay of 30ms in glowing a LED using Timer 0 and mode 1.
ORG 0000H
MOV TMOD,#01H
UP: MOV TL0,#0D0H
MOV TH0,#8AH
CPL P1.5
ACALL DELAY
SJMP UP
DELAY: SETB TR0
AGAIN: JNB TF0, AGAIN
CLR TR0
CLR TF0
RET
END

Write an ALP to Interface 8- LEDs to PORT 2 of 8051 with the delay of 45mS using the interrupt
Timer0 mode1. The data has to display the value “0AAH”.

ORG 0000H
MOV TMOD,#01H
MOV P2,#00H
UP: MOV TL0,#38H
MOV TH0,#50H
 CPL A
MOV P2,A
ACALL DELAY
SJMP UP
DELAY: SETB TR0
AGAIN: JNB TF0, AGAIN
CLR TR0
CLR TF0
RET
END

Write an ALP to toggle the LED, which is connected with the P2.7 and without using
timers. the delay need to be generated as 5 Sec.

ORG 0000H
UP: CPL P2.7
ACALL DELAY
SJMP UP
DELAY: SETB TR0
AGAIN: JNB TF0, AGAIN
CLR TR0
CLR TF0
RET
END

ORG 0000H
MOV P2, #00H
RETURN: ACALL DELAY
CPL P2.7
SJMP RETURN
DELAY: MOV R5, #50H //load register R5 with 50//
DELAY1: MOV R6, #200 //load register R6 with 200//
DELAY2: MOV R7, #229 //load register R7 with 200//
DJNZ R7, $ //decrement R7 till it is zero//
DJNZ R6, DELAY2 //decrement R6 till it is zero//
DJNZ R5, DELAY1 //decrement R5 till it is zero//
RET //go back to the main program //
END

Write an ALP to Transmit the information “***INDIA***” with baud rate of 9600 and 8
data bits, 1 stop bit
MOV TMOD,#20H ; Timer 1, mode 2
MOV TH1,#-3 ; 9600 baud rate
MOV SCON,#50H ; 8-bit, 1-stop bit
SETB TR1 ; start timer 1
AGAIN: MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"I" ;transfer "I"
ACALL TRANS
MOV A,#"N" ;transfer "N"
ACALL TRANS
MOV A,#"D" ;transfer "D"
ACALL TRANS
MOV A,#"I" ;transfer "I"
ACALL TRANS
MOV A,#"A" ;transfer "A"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
SJMP AGAIN ;keep doing it
TRANS: MOV SBUF,A ; load SBUF
HERE: JNB TI,HERE ; wait for last bit to transfer
CLR TI ;get ready for next bute
RET
Write an ALP to transmit the information “***TELANGANA***” with 4800 baud rate, data bit 8, and 1
stop bit
MOV TMOD,#20H ; Timer 1, mode 2
MOV TH1,#-2 ; 4800 baud rate
MOV SCON,#50H ; 8-bit, 1-stop bit
SETB TR1 ; start timer 1
AGAIN: MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"T" ;transfer "T"
ACALL TRANS
MOV A,#"E" ;transfer "E"
ACALL TRANS
MOV A,#"L" ;transfer "L"
ACALL TRANS
MOV A,#"A" ;transfer "A"
ACALL TRANS
MOV A,#"N" ;transfer "N"
ACALL TRANS
MOV A,#"G" ;transfer "G"
ACALL TRANS
MOV A,#"A" ;transfer "A"
ACALL TRANS
MOV A,#"N" ;transfer "N"
ACALL TRANS
MOV A,#"A" ;transfer "A"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
MOV A,#"*" ;transfer "*"
ACALL TRANS
 SJMP AGAIN ;keep doing it
TRANS: MOV SBUF,A ; load SBUF
HERE: JNB TI,HERE ; wait for last bit to transfer
CLR TI ;get ready for next byte
RET