MALLA REDDY ENGINEERING COLLEGE (AUTONOMOUS)

II B.Tech II Semester (MR 22) II Mid Question Bank 2023-24 (Objective)

Subject: Pulse and Linear Integrated Circuits (C0412) Branch: ECE
Name of the Faculty: Dr.A.Pradeep Kumar, Mrs. P. Sowjanya & Dr. Sima Sahu

Sl.No Questions Ans

Module-III
1 A certain OP-amp has bias currents of 18μA and 22μA. The input offset current is ……. b
(a) 2μA (b) 4μA (c) 6μA (d) 8μA
2 With zero volts applied to both inputs, an OP-amp ideally should have an output ……….. c
(a) equal to the positive supply voltage (b) equal to the negative supply voltage
(c) equal to zero (d) equal to CMRR
3 For an ideal OP-AMP PSRR is ___________ b
(a) Zero (b) Infinity (c) 100 (d) 1
4 The Op-amp can amplify……. c
(a) a.c. signals only (b) d.c. signals only
(c) both a.c. and d.c. signals (d) neither d.c. nor a.c. signals
5 The input offset current equals the ………. a
(a) difference between two base currents (b) average of two base currents
(b) collector current divided by current gain (d) none of these
6 The input bias current equals the ……….
(a) difference between two base currents (b) average of two base currents b
(c) collector current divided by current gain (d) none of these
7 _____ is the unit for the slew rate of an OP-AMP.
d
(a) V/ms (b) ms/V (c) V (d) V/ μs
8 The common-mode rejection ratio (CMRR) is defined by _____.
a
(a) Ad / Ac (b) Ac / Ad (c) Ad × Ac (d) Ad + Ac
9 Ideally, the value of the CMRR is _____. Practically, the _____ the value of CMRR, the better
the circuit operation. b

(a) zero, smaller (b) infinite, larger (c) zero, larger (d) infinite, smaller
10 What is the slew rate of an op-amp if the output voltages change from 2 V to 3 V in 0.2 ms?
a
(a) 5 V/ms (b) 3 V/ms (c) 2 V/ms (d) 1 V/ms
11 What is the level of the voltage between the input terminals of an op-amp? a
(a) 0V (b) 5V (c) 18V (d) 22V
12 Bandwidth of an Ideal Op-Amp is c
(a) Zero (b) Infinite (c) finite (d) Negative
13 The ratio of change in input offset voltage with variation in supply voltage is d
(a) Rise time (b) CMRR (c) transient response (d) PSRR
14 The maximum rate of change of output voltage with time is called as c
(a) Rise time (b) CMRR (c) Slew rate (d) PSRR
15 For a given Op amp _____________ remains always constant. d
(a) Error voltage (b) Feedback voltage (c) Closed loop gain (d)Gain-bandwidth product
16 The ratio between differential gain and common-mode gain is called:
(a) amplitude (b) differential-mode rejection c
(c) common-mode rejection (d) Signal-mode rejection
17 The voltage required to be applied at the input for making output voltage to zero volts is ____.
(a) Input bias voltage (b) input offset voltage b
(c) Output bias voltage (d) Output offset voltage
18 In an OP-AMP __________ changes with temperature. d
(a) Input bias current (b) input offset current (c) input offset voltage (d) All of the above
19 The following is a DC characteristic of an OP-AMP a
(a) CMRR (b) PSRR (c) Rise time (d) Thermal drift
20 PSRR also called as ____________ c
(a) SVRR (b) PSS (c) both a & b (d) None of these
21 ____________ circuits are used to improve frequency response of an OP-AMP
(a) Resistive networks (b) Capacitive networks d
(c) Inductive networks (d) Compensating networks
22 The condition for stability of a practical OP-AMP is ______ a
(a) ACL< AOL (b) ACL > AOL (c) ACL = 0 (d) ACL = infinity
23 At high frequencies OP-AMP gain reduces due to ______ b
(a) Coupling capcitances (b) Paracitic capacitances (c) Both a & b (d) None of the above
24 At low frequencies OP-AMP gain reduces due to ______ a
(a) Coupling capacitance (b) Parasitic capacitance (c) Both a & b (d) None of the above
25 For an ideal OP-AMP CMRR is ___________ b
(a) Zero (b) Infinity (c) 100 (d) 1
Module-IV
26 For an Op-amp with negative feedback, the output is …….
(a) equal to the input (b) increased c
(c) fed back to the inverting input (d) fed back to the non inverting input
27 For an Op-amp with positive feedback, the output is …….
(a) equal to the input (b) increased b
(c) fed back to the inverting input (d) fed back to the non inverting input
28 A certain non-inverting amplifier has Ri of 1 kΩ and Rf of 100 kΩ. The closed-loop voltage
gain is __________ d
(a) 1000 (b) 1001 (c) 100 (d) 101
29 A certain inverting amplifier has Ri of 1 kΩ and Rf of 100 kΩ. The closed-loop voltage gain is
__________ c
(a) - 1000 (b) - 1001 (c) - 100 (d) - 101
30 The ________ is the voltage gain of an op-amp with external feedback. b
(a) Aol (b) Acl (c) Av (d) A
31 Refer to the given figure. What is the output voltage?
 d

(a) 2 V (b) - 2 V (c) +Vsat (d) –Vsat

32 The feedback component of an integrator is _____ b
(a) resistor (b) capacitor (c) inductor (d) diode

33 The feedback component of a differentiator is _____ a

(a) resistor (b) capacitor (c) inductor (d) diode
34 The advantages of Integrated Circuit is/are d
(a) Small Size (b) Low Cost (c) Low Power consumption (d) All the Above
35 The output signal of an op-amp is _____ out of phase with its input signal connected to the
inverting input terminal
c
(a) 0º (b) 90º (c) 180º (d) 270º
36 An integrator is used in the conversion of square waveform to ___________ b

(a) sine wave (b) triangular wave (c) pulse wave (d) ramp wave
37 A differentiator is used in the conversion of triangular waveform to ___________ b

(a) sine wave (b) square wave (c) pulse wave (d) ramp wave
38 Refer to the given figure. Determine the output voltage, V OUT

(a) 1.05 V (b) –0.35 V (c) 0.35 V (d) –1.05 V

39 What type(s) of circuit(s) use comparators?
b
(a) summer (b) zero-level detector (c) averaging amplifier (d) subtractor
40 A differentiator is used to measure
(a) The sum of the input voltages (b) The difference between two voltages
(c) The area under a curve (d) The rate of change of the input voltage d

41 A(n) ________ amplifier is a summing amplifier with a closed-loop gain equal to the
reciprocal of the number of inputs. a
(a) averaging (b) scaling (c) multiplier (d) none
42 What circuit produces an output that approximates the area under the curve of an input
function? a
(a) integrator (b) differentiator (c) summing amplifier (d) comparator
43 A comparator with a Schmitt trigger has b
(a) One trigger level (b) Two trigger levels (c) Three trigger levels (d) None of the above
44 The output of a Schmitt trigger is a a
(a) Rectangular wave (b) Saw tooth wave (c) Sinusoidal wave (d) triangle wave
45 Refer to the given figure. This circuit is known as

(a) Non inverting amplifier (b) Differentiator (c) An integrator (d) A summing amplifier
46 Refer to the given figure. This circuit is known as

(a) Non inverting amplifier (b) Differentiator (c) An integrator (d) A summing amplifier
47 In a _______ circuit when the input voltage exceeds a specified reference voltage, the output
changes state. d
(a) Integrator (b) Differentiator (c) summing amplifier (d) Comparator
48 A Schmitt trigger is
(a) Comparator with only one triggers point (b) comparator with hysteresis b
(c) Comparator with three triggers points (d) None of the above
49 Disadvantage of Ideal Differentiator
(a) Gain of the differentiator increases as frequency increases
(b) Gain of the differentiator increases as frequency decreases a
(c) Gain of the differentiator decreases as frequency decreases
(d) Gain of the differentiator decreases as frequency increses
50 If step voltage applied as input to an integrator then the output a
(a) ramp (b) Square (c) triangular (d) Sine
51 Above the cut off frequency of 1 order LPF, the output voltage decrement at the rate of
st
a
(a) 20 dB / decade (b) 40 dB / decade (c) 60 dB / decade (d) 80 dB / decade
52 A wide band stop filter is a combination of d
(a) LPF (b) HPF (c) Summing amplifier (d) Both (a) and (c)
53 The band of frequency beyond the cutoff frequency which are attenuated is called____ d
(a) Pass band (b) Stop band (c) Narrow band (d) None
54 The filter which is having both pass band and stop band quite flat is a
(a) Butter worth filter (b) Chebyshev filter (c) Capture filter (d) None
55 An Electrical Filter is a b
(a) Phase-selective circuit (b) Frequency-selective circuit
(c)Filter-selective circuit (d) None of the mentioned
56 For a wide band pass filter Quality factor is _______ a
(a) < 10 (b) > 10 (c) < 1 (d) > 1
57 A HPF will
(a) pass high frequencies (b) pass low frequencies (c) pass dc (d) Block dc a

58 The filter that produces necessary phase shift between output and input signals is c
(a) Notch filter (b) Band pass filter (c) All pass filter (d) None
59 As the order of the filter increases, the roll off rate of gain in the stop band b
(a) Decreases (b) Increases (c) Constant (d) None
60 A LPF will
(a) pass high frequencies (b) pass low frequencies (c) pass dc (d) Block dc b

61 For a band pass filter pass band present ___________

(a) before fL (b) between fL and fH (c) after fH (d) All the above b

62 For a band pass filter stop band present ___________ d

(a) before fL (b) between fL and fH (c) after fH (d) both a and c
63 For a band reject filter pass band present ___________ d
(a) before fL (b) between fL and fH (c) after fH (d) both a and c
64 For a band reject filter stop band present ___________ b
(a) before fL (b) between fL and fH (c) after fH (d) both a and c
65 For a low pass filter pass band present ___________ a
(a) before fH (b) between fL and fH (c) after fH (d) All the above
66 For a low pass filter stop band present ___________ c
(a) before fH (b) between fL and fH (c) after fH (d) All the above
67 For a high pass filter pass band present ___________ c
(a) before fL (b) between fL and fH (c) after fL (d) All the above
68 For a high pass filter stop band present ___________ a
(a) before fL (b) between fL and fH (c) before fH (d) All the above
69 _______________ filter allows all the frequency signals through it d
(a) low pass (b) high pass (c) band pass (d) all pass
70 What is the factor to be multiplied to the dc gain of the filter to obtain filter magnitude at
cutoff frequency? c
(a) 1 (b) √2 (c) 1/√2 (d) 1/2
71 What is the factor to be multiplied to the dc gain of the filter to obtain filter magnitude at
cutoff frequency? c
(a) 1 (b) 1.414 (c) 0.707 (d) 0.5
72 Lower cut off frequency of low pass filter is __________
(a) 0 (b) 1 (c) 1/2ΠRC (d) 2ΠRC a
73 Higher cut off frequency of low pass filter is __________
(a) 0 (b) 1 (c) 1/2ΠRC (d) 2ΠRC c
74 Lower cut off frequency of high pass filter is __________
(a)0 (b) 1 (c) 1/2ΠRC (d) 2ΠRC c
75 Higher cut off frequency of high pass filter is __________
(a)0 (b) 1 (c) 1/2ΠRC (d) infinity d
Module-V
76 VCO stands for _________ c
(a) Voltage crystal oscillator (b) Variable crystal Oscillator
(c) Voltage controlled Oscillator (d) Variable controlled Oscillator
77 The flipflop in 555 timer is a
(a) SR (b) JK (c) D (d) T
78 The pin 7 of IC 555 is used for the purpose of _______________ of the transistor in the basic
functional diagram b
(a) Charge (b) Discharge (c) Both a & b (d) None
79 In Astable Multivibrator using 555 timer if Ra=Rb then duty cycle is d
(a) 10% (b) 50% (c) 35% (d) 65%
80 In PLL, the capture range is always _________the lock range. a
(a) Greater than (b) Equal to (c) Less than (d) None of the above
81 Which characteristic of PLL is defined as the range of frequencies over which PLL can acquire d
lock with the input signal?
(a) Free-running state (b) Pull-in time (c) Lock-in range (d) Capture range
82 Which characteristic of PLL is defined as the range of frequencies over which PLL can c
maintain lock with the input signal?
(b) Free-running state (b) Pull-in time (c) Lock-in range (d) Capture range
83 The output of the 555 timer is high, if the amplitude of the trigger pulse is
(a) >1/3Vcc (b) <1/3Vcc (c) <2/3Vcc (d) >2/3Vcc b
84 In AM detector using PLL, the phase detector is basically a multiplier which produces
________components of frequencies at its output. b
(a) Sum (b) Difference (c) Both a and b (d) None of the above
85 In the locked state of PLL, the phase error between the input & output is _________
(a) Maximum (b) Minimum (c) Moderate (d) None of the above b
86 The o/p of the 555 timer is low, if the amplitude of the threshold input pin is ________
(a) <1/3Vcc (b) >1/3Vcc (c) <2/3Vcc (d) >2/3Vcc d
87 In communication circuits, PLL is currently applicable for __________
(a) Demodulation applications
(b) Tracking a carrier or synchronizing signal c
(c) Both a and b
(d) None of the above
88 Basically, PLL is used to lock _______
(a) Its output frequency (b) Phase to the frequency
b
(b) Phase of the input signal (d) All of the above
89 In VCO IC 566, the value of charging & discharging is dependent on the voltage applied at
_________? c
(a) Triangular wave output (b) Square wave output (c) Modulating input (d) None
90 Duty cycle is defined as
(a) Ton/(Ton+Toff) (b)Ton/(Ton-Toff) (c) Toff/(Ton+Toff) (d) Toff/(Ton-Toff) a
91 Which multivibrator also called as One-Shot
(a) Bistable (b) Astable (c) Monostable (d) None of the above c
92 Which multivibrator also called as free running
(a)Bistable (b) Astable (c) Monostable (d) None of the above b
93 Which multivibrator also called as Uni vibrator
(a)Bistable (b) Astable (c) Monostable (d) None of the above c
94 In schmitt trigger circuit, UTP stands for
(a) Upper triggering point (b) Upper tripping point (c) both a and b (d) None of the above c
95 Pulse width expression of Monostable Multivibrator
(a) 0.69 RC (b) 1.38 RC (c) 0.693 (R 1C1- R2C2) (d) 1.38 (R1C1- R2C2) b
96 The Logic gate that works similar to phase detector is:
(a) AND gate (b) OR gate (c) XOR gate (d) NOR gate c
97 The timing range of 555 Timer is
(a) nano to micro sec. (b) micro sec. to milli sec. (c) micro sec to hrs. (d) Few days c
98 The pin 1 of IC 555 is
(a) Ground (b) trigger (c) Threshold (d) reset a
99 The pin 4 of IC 555 is
(a) Ground (b) trigger (c) Threshold (d) reset d
100 The pin 6 of IC 555 is
Ground (b) trigger (c) Threshold (d) reset c
101 Which of the following is a type of error associated with digital-to-analog converters (DACs)?
(a) Non monotonic error (b) incorrect output codes
c
(c) offset error (d) Non monotonic and offset error

102 A 4-bit digital-to-analog (DAC) converter has a full scale voltage of 5 volts. What is the
analog output for the input code 0101.
d
(a) 0.3125 V (b) 3.125 V (c) 0.78125 V (d) 1.5625 V

103 Change in the output as a result of change in the input is called as __________.

(a) Accuracy (b) Linearity (c) Monotonicity (d) Resolution d

104 The difference between expected output and actual output of data converter is called as _____.

(a) Quantization (b) Accuracy (c) Resolution (d) Monotonicity b

105 The primary disadvantage of the flash analog-to digital converter (ADC) is that:

(a) A long conversion time is required

(b) A large number of output lines is required to simultaneously decode the input voltage c

(c) A large number of comparators is required to represent a reasonable sized binary number
 (d) It requires the input voltage to be applied to the inputs simultaneously

106 What is the major advantage of the R/2R ladder digital-to-analog (DAC), as compared to a
binary-weighted digital-to-analog DAC converter?

(a) It only uses two different resistor values

(b) It has fewer parts for the same number of inputs

a
(c) Its operation is much easier to analyze.

(d) The virtual ground is eliminated and the circuit is therefore easier to analyze understand
and troubleshoot.

107 The resolution of a 0–5 V, 6-bit digital-to-analog converter (DAC) is:

(a) 63% (b) 64% (c) 7.81% (d) 15.6% c

108 What is the level of the output voltage of a ladder-network conversion?

(a) The analog output voltage proportional to the digital input voltage

(b) The digital output voltage proportional to the linear input voltage a

(c) A fixed digital value Vref

(d) A fixed analog value Vref

109 Which among the following types of ADCs require/s the shortest conversion time?

(a) Flash type (b) Successive Approximation (c) Dual Slope (d) All of the above a

110 In a flash analog-to-digital converter, the output of each comparator is connected to an input of
a:
b
(a) Decoder (b) Priority encoder (c) Multiplexer (d) Demultiplexer

111 Sample-and-hold circuits in analog-to digital converters (ADCs) are designed to:

(a) sample and hold the output of the binary counter during the conversion process

(b) stabilize the comparator's threshold voltage during the conversion process d

(c) stabilize the input analog signal during the conversion process

(d) sample and hold the D/A converter staircase waveform during the conversion process

112 What is the first phase of the dual-slope method of conversion?

 (a) Connecting the analog voltage to the integrator for a fixed time

(b) Setting the counter to zero a

(c) Connecting the integrator to a reference voltage

(d) All of the above

113 What is the maximum conversion time of a clock rate of 1 MHz operating a 10-stage counter
in an ADC?
d
(a) 1.024 s (b) 102.3 ms (c) 10.24 ms (d) 1.024 ms

114 On which of the following does the conversion depend in ladder-network conversion?

(a) Binary word length (b) Control logic (c) Digital counter (d) Clock a

115 What is the function of a ladder network?

(a) Changing an analog signal to a digital signal

(b) Changing a linear signal to a digital signal c

(c) Changing a digital signal to an analog signal

(d) None of the above

116 Which of the slope intervals of the integrator does the counter in the analog-to-digital
converter (ADC) operate?
(a) Positive (b) Negative
b
(c) Both positive and negative (d) Neither positive nor negative

117 At which of the following period(s) is the counter advanced (incremented) in dual-slope
conversion?
(a) During the charging of the capacitor of the integrator
a
(b) During the discharging of the capacitor of the integrator

(c) During both the charging and discharging of the capacitor of the integrator

(d) None of the above

118 What is (are) the input(s) to the comparator in the ladder-network conversion of an ADC?

(a) Staircase voltage (b) Analog input voltage c

(c) Both staircase and analog input voltage (d) None of the above
119 This circuit is an example of a _______

(a) Comparator (b) 555 timer (c) D to A converter (d) ladder network

120 When is the counter set to zero in the dual-slope method of conversion?

Prior to the charging of the capacitor of the integrator

(b) While the capacitor is being charged d

(c) At the end of the charging of the capacitor

(d) During the discharging of the capacitor

121 Which of the following devices is (are) a component of a Analog-to-Digital converter (ADC)?

(a) Integrator (b) Comparator (c) Digital Counter (d) All the above d

122 What is the voltage resolution of an 8-stage ladder network?

(a) Vref /128 (b) Vref /256 (c) Vref /512 (d) Vref /1024 b

123 The advantage of ADC of dual slope type is

(a)Excellent noise rejection (b) Long conversion time a

(c) Fastest in operation (d) Slow varying in nature

124 Only two values of resistor are required for the DAC

(a) Weighted resistor method (b) R-2R ladder b

(c) Binary weighted method (d) None of the above

125 In DAC’s, gain error can be eliminated by _________.

(a) Adjusting VFS value (b) Adjusting K value b

(c) both (a) & (b) (d) Changing SPDT switch position

Signature of the Faculty Signature of the HOD