Micro computer and Interfacing

CH-1

Introduction to Microprocessor

1. History of Microprocessors

The microprocessor is a compact, integrated circuit that serves as the central

processing unit (CPU) of a computer. It was first developed in the early 1970s,
revolutionizing computing by replacing bulky transistor-based CPUs.

 1971 – Intel introduced the first commercial microprocessor, the Intel 4004, a 4-
bit processor designed for calculators.

 1974 – Intel released the 8080, an 8-bit processor that became widely used in
early personal computers.

 Late 1970s to 1980s – The introduction of 16-bit and 32-bit processors like the
Intel 8086 and 80386 enhanced computing capabilities.

 1990s to Present – The evolution of multi-core and high-performance

processors, including Intel’s Pentium, Core i-Series, and Xeon, led to significant
advancements in computing power.

2. Evolution of the Intel Processor

Intel has been a leader in microprocessor development, continuously improving

processing speed, architecture, and efficiency.

 Intel 4004 (1971) – First 4-bit microprocessor with 2,300 transistors.

  Intel 8086 (1978) – 16-bit architecture, foundation for x86 architecture.

 Intel 80386 (1985) – 32-bit processor, supporting multitasking.

 Intel Pentium Series (1993) – Improved performance with superscalar

architecture.

 Intel Core Series (2006-Present) – Introduction of multi-core processors for

enhanced parallel processing.

 Intel Core i9 & Xeon (2017-Present) – High-performance processors with AI

acceleration and advanced computing capabilities.

3. How does a Microprocessor Work?

The microprocessor follows a sequence: Fetch, Decode, and then Execute.

 Initially, the instructions are stored in the memory in a sequential order.

 The microprocessor fetches those instructions from the memory,

 Then decodes it and executes those instructions till STOP instruction is reached.

 Later, it sends the result in binary to the output port.

 Between these processes, the register stores the temporarily data and ALU
performs the computing functions.

A microprocessor can be classified into three categories

RISC Processor

RISC stands for Reduced Instruction Set Computer. It is designed to reduce the
execution time by simplifying the instruction set of the computer. Using RISC
processors, each instruction requires only one clock cycle to execute results in uniform
execution time. This reduces the efficiency as there are more lines of code, hence more
RAM is needed to store the instructions. The compiler also has to work more to convert
high-level language instructions into machine code.

Some of the RISC processors are −

 Power PC: 601, 604, 615, 620

 DEC Alpha: 210642, 211066, 21068, 21164

 MIPS: TS (R10000) RISC Processor

 PA-RISC: HP 7100LC
Architecture of RISC

RISC microprocessor architecture uses highly-optimized set of instructions. It is used in

portable devices like Apple iPod due to its power efficiency.

Characteristics of RISC

The major characteristics of a RISC processor are as follows −

 It consists of simple instructions.

 It supports various data-type formats.

  It utilizes simple addressing modes and fixed length instructions for pipelining.

 It supports register to use in any context.

 One cycle execution time.

 “LOAD” and “STORE” instructions are used to access the memory location.

 It consists of larger number of registers.

 It consists of less number of transistors.

CISC Processor

CISC stands for Complex Instruction Set Computer. It is designed to minimize the
number of instructions per program, ignoring the number of cycles per instruction. The
emphasis is on building complex instructions directly into the hardware.

The compiler has to do very little work to translate a high-level language into assembly
level language/machine code because the length of the code is relatively short, so very
little RAM is required to store the instructions.

Some of the CISC Processors are −

 IBM 370/168

 VAX 11/780

 Intel 80486

Architecture of CISC

Its architecture is designed to decrease the memory cost because more storage is
needed in larger programs resulting in higher memory cost. To resolve this, the number
of instructions per program can be reduced by embedding the number of operations in
a single instruction.
Characteristics of CISC

 Variety of addressing modes.

 Larger number of instructions.

 Variable length of instruction formats.

 Several cycles may be required to execute one instruction.

 Instruction-decoding logic is complex.

 One instruction is required to support multiple addressing modes.

List of Terms Used in a Microprocessor

Here is a list of some of the frequently used terms in a microprocessor −

 Instruction Set − It is the set of instructions that the microprocessor can

understand.

 Bandwidth − It is the number of bits processed in a single instruction.

 Clock Speed − It determines the number of operations per second the processor
can perform. It is expressed in megahertz (MHz) or gigahertz (GHz). It is also
known as Clock Rate.

 Word Length − It depends upon the width of internal data bus, registers, ALU, etc.
An 8-bit microprocessor can process 8-bit data at a time. The word length ranges
from 4 bits to 64 bits depending upon the type of the microcomputer.

 Data Types − The microprocessor has multiple data type formats like binary,
BCD, ASCII, signed and unsigned numbers.
CH-2

8086 Microprocessor Architecture

2. Architecture of 8086 Microprocessor

1. Features of 8086 Microprocessor

The 8086 microprocessor has several key features that differentiate it from earlier
processors:

 16-bit Processor: The ALU (Arithmetic Logic Unit), internal registers, and data
bus are all 16-bit, allowing it to process 16-bit data at a time.

 20-bit Address Bus: Can address up to 1MB (220) of memory using a segmented
memory model.

 Instruction Queue (Pipelining): A 6-byte prefetch queue allows instruction

fetching to overlap with execution, improving speed.

 Operating Modes: Supports both minimum mode (single processor) and

maximum mode (multiprocessor system) operations.

 Registers: Includes general-purpose registers, segment registers, pointer

registers, and index registers.

 Memory Segmentation: Uses segmented addressing, where memory is divided

into 64KB segments (Code, Data, Stack, Extra).

 Interrupt Handling: Supports 256 interrupts, including both hardware and

software interrupts.

 Clock Speed: Available in 5 MHz, 8 MHz, and 10 MHz versions.

 Multiplication and Division Support: Can perform multiplication and division

 operations internally.

 I/O Addressing: Supports I/O-mapped I/O (64K ports) and memory-mapped I/O

Architecture of 8086 microprocessor

The 8086-microprocessor architecture consists of two main functional units:

1. Bus Interface Unit (BIU)

2. Execution Unit (EU)

A. Bus Interface Unit (BIU)

The Bus Interface Unit (BIU) handles memory addressing, instruction fetching, and
communication with peripherals.

 The BIU fetches instructions from memory and stores them in the instruction
queue.

Components of BIU:

1. Segment Registers (16-bit each):

o CS (Code Segment) – Holds the base address of the code.

o DS (Data Segment) – Points to the data stored in memory.

o SS (Stack Segment) – Manages function calls and stack operations.

o ES (Extra Segment) – Used for additional data storage.

2. Instruction Queue:

o Stores up to 6 bytes of prefetched instructions.

o Implements pipelining, reducing instruction-fetch time.

3. Address Generation Unit:

o Generates a 20-bit physical address using the segment: offset scheme.

4. Bus Control Logic:

o Controls memory and I/O read/write operations.

B. Execution Unit (EU)

The Execution Unit (EU) decodes and executes instructions fetched by the BIU.
  The EU fetches instructions from the queue, decodes them, and executes them.

Components of EU:

1. Arithmetic Logic Unit (ALU) – Performs arithmetic and logic operations.

2. General-Purpose Registers:

o AX (Accumulator) – Used for arithmetic and I/O operations.

o BX (Base Register) – Holds base addresses.

o CX (Counter Register) – Used in loop operations.

o DX (Data Register) – Used in multiplication and division.

3. Pointer and Index Registers:

o SP (Stack Pointer) – Points to the top of the stack.

o BP (Base Pointer) – Used in stack-based addressing.

o SI (Source Index) – Used in string operations.

o DI (Destination Index) – Used for string operations.

4. Control Unit – Manages instruction execution.

5. Flag Register – Stores status flags (Zero Flag, Carry Flag, etc.).
3. Bus Operation of 8086 Microprocessor

The 8086 microprocessor communicates with memory and I/O devices through three
main buses:

A. Address Bus (20-bit, Unidirectional)

 Can address up to 1MB of memory.

 Used to select memory locations or I/O ports.

B. Data Bus (16-bit, Bidirectional)

 Transfers data between CPU, memory, and I/O devices.

 Supports byte (8-bit) or word (16-bit) transfers.

C. Control Bus

 Carries control signals such as Read (RD), Write (WR), Interrupt Request (INT),
Clock signals, etc.

Bus Cycles

1. Memory Read/Write Cycle – Transfers data between memory and CPU.

2. I/O Read/Write Cycle – Transfers data between I/O devices and CPU.

3. Interrupt Acknowledge Cycle – Handles interrupt processing.

4. 8086 Register Organization

The 8086 has various registers classified into different groups:

 Type 8086 registers

A. General-Purpose Registers (16-bit each)

Used for arithmetic, logic, and data manipulation:

 AX – Accumulator

 BX – Base Register

 CX – Counter

 DX – Data Register

B. Segment Registers (16-bit each)

Used for memory segmentation:

 CS (Code Segment)

 DS (Data Segment)
  SS (Stack Segment)

 ES (Extra Segment)

C. Pointer and Index Registers (16-bit each)

Used for addressing memory locations:

 SP (Stack Pointer)

 BP (Base Pointer)

 SI (Source Index)

 DI (Destination Index)

D. Flag Register (16-bit)

Stores status flags that indicate processor state:

 Carry Flag (CF) – Set when a carry occurs.

 Zero Flag (ZF) – Set if result is zero.

 Sign Flag (SF) – Set if result is negative.

 Overflow Flag (OF) – Set if arithmetic overflow occurs.

 Direction Flag (DF) – Controls string operations.

5. 8086 Memory Segmentation

The 8086 microprocessor uses segmented memory addressing to efficiently manage

memory access.
A. Memory Segments (Each 64KB in size)

1. Code Segment (CS) – Stores program instructions.

2. Data Segment (DS) – Holds data variables.

3. Stack Segment (SS) – Manages stack operations.

4. Extra Segment (ES) – Used for additional data.

B. Physical Address Calculation

The 20-bit physical address is computed using:

Physical Address=Segment Base×10+Offset

For example, if CS = 2000H and IP = 1234H, then:

(2000H×10H) +1234H=21234H

Thus, the instruction is fetched from memory location 21234H.

CH - 3

8086 Microprocessor Programming and Instruction Set

8086 Addressing Modes

The 8086 microprocessor provides several addressing modes to access data efficiently.
Each addressing mode specifies how the operands for instructions are selected and
located. Here are the detailed notes and examples for the different addressing modes in
8086:

1. Immediate Addressing Mode

In this mode, the operand is a constant value (data) provided explicitly in the instruction
itself.

 The operand (data) is part of the instruction itself.

 The CPU does not need to fetch data from memory.

 Format: MOV destination, data

 Example:

MOV AX, 5; Load immediate value 5 into AX register

Here, 5 is the immediate value.

MOV AX, 1234H ; Move immediate value 1234H into register AX

MOV BL, 0AH ; Move immediate value 0AH into register BL

The number (1234H, 0AH) is directly given in the instruction.

2. Register Addressing Mode

In this mode, the operand is located in a register. The operand is directly accessed from
one of the processor's registers.

 The operand is located in a register.

 The instruction specifies which register to use

 Format: MOV destination, source

 Example:

MOV AX, BX; Copy the value in register BX into AX register

In this case, the data comes directly from the register BX.

ADD AL, CL ; Add CL register content to AL

The data is moved within the registers without using memory.

3. Direct Addressing Mode

In direct addressing, the operand is located in memory at the address specified by the
instruction. The effective address (EA) is given directly in the instruction.

 The memory address is directly mentioned in the instruction.

 The CPU fetches data from that memory address.

 Format: MOV destination, [memory_address]

 Example:

MOV AX, [1234h]; Move the data at memory address 1234h into AX
The operand is fetched from memory address 1234h.

MOV AL, [1234H] ; Load AL with the content at memory address 1234H

The content at memory address 1234H is loaded into register AL.

MOV [5678H], BL ; Store BL content into memory address 5678H

The content of BL is stored in memory at 5678H.

4. Register Indirect Addressing Mode

This mode uses the contents of a register as the address of the operand. The operand
resides in memory at the address stored in the register.

 The memory address is indirectly given through a register.

 The register contains the address of the operand.

 Format: MOV destination, [register]

 Example:

MOV AX, [DI]; Move the data from the memory address in DI into AX

The register DI contains the address where the operand is stored.

MOV AL, [BX] ; Move data from memory address in BX to AL

MOV [SI], DL ; Store DL in memory location pointed by SI

The value of BX or SI is used as a pointer to access memory.

5. Indexed Addressing Mode

In this mode, the effective address is the sum of a base register and an index register. It
is useful for accessing elements in arrays or tables.

 The effective address is obtained by adding an index register to a base address.

 Format: MOV destination, [base_register + index_register]

 Example:
MOV AX, [SI + 10]; Move the data at the address SI+10 into AX

Here, SI is the base register, and 10 is the offset.

MOV AL, [BP + SI] ; Move data from memory address BP + SI to AL

MOV [DI], CX ; Store CX at memory location pointed by DI

Used in array processing where an index register holds an offset.

6. Base-Register Addressing Mode

This mode combines the use of a base register (e.g., BX, BP) with a direct memory
address or an offset. The base register holds the starting address, and an offset is
added to it to calculate the final memory address.

 The effective address is obtained by adding an index register to a base address.

 Format: MOV destination, [base_register + displacement]

 Example:

MOV AX, [BX + 10]; Move the data at the address (BX+10) into AX

In this example, the value of BX is added with 10 to form the effective address.

MOV AL, [BP + SI] ; Move data from memory address BP + SI to AL

MOV [DI], CX ; Store CX at memory location pointed by DI

Used in array processing where an index register holds an offset.

7. Stack Addressing Mode

The stack addressing mode involves the use of the stack pointer (SP) or base pointer
(BP) register. The operand is accessed from or written to the stack, which is a last-in-
first-out (LIFO) structure.

 Format: MOV destination, [SP + offset] or MOV destination, [BP + offset]

 Example:
MOV AX, [SP + 4]; Move the data from the address (SP+4) into AX

Here, SP holds the current stack pointer, and 4 is the offset from the stack top.

8. Based Indexed Addressing Mode

This mode combines both base and index registers to calculate the effective address. It
is commonly used for accessing arrays or structures.

 Both base and index registers are used to determine the memory address.

 Format: MOV destination, [base_register + index_register + displacement]

 Example:

MOV AX, [BX + SI + 10]; Move the data from the address (BX + SI + 10) into AX

In this case, both BX and SI provide the base and index, and 10 is an additional offset.

Summary of Addressing Modes

Addressing Example Operand Location

Mode

Immediate MOV AX, 5 Operand is constant (5)

Register MOV AX, BX Operand is in register BX

Direct MOV AX, [1234h] Operand is in memory at 1234h

Indirect MOV AX, [SI] Operand is in memory at address in SI

Indexed MOV AX, [SI + 10] Operand is in memory at address (SI + 10)

Base-Register MOV AX, [BX + 10] Operand is in memory at address (BX + 10)

Stack MOV AX, [SP + 4] Operand is on the stack at address (SP + 4)

Register Indirect MOV AX, [DI] Operand is in memory at address in DI

Based Indexed MOV AX, [BX + SI + Operand is in memory at address (BX + SI +

10] 10)
 Register-Relative MOV AX, [BX + 100] Operand is in memory at address (BX +
100)

These addressing modes allow flexibility in how operands are accessed in 8086
assembly language programming, making it possible to access memory and registers in
various ways for different applications.

8086 Instruction Set

The 8086-instruction set is categorized into different groups based on the operations
they perform. These groups include data transfer, arithmetic, logical, control transfer,
string, and processor control instructions. Below is a detailed classification of the 8086
-instruction set

The 8086-instruction set is divided into different categories:

✅ Data Transfer Instructions – Move data between registers, memory, and I/O.
✅ Arithmetic Instructions – Perform mathematical operations.
✅ Logical Instructions – Work with bitwise operations.
✅ Control Transfer Instructions – Change program execution flow.
✅ String Instructions – Handle large data blocks.
✅ Processor Control Instructions – Modify processor behavior
1. Data Transfer Instructions

These instructions move data between registers, memory, and I/O ports.

Instruction Example Description

MOV MOV AX, BX Copy BX to AX

PUSH PUSH AX Push AX onto the stack

POP POP CX Pop top of the stack into CX

XCHG XCHG AX, BX Exchange AX and BX

IN IN AL, 60H Read data from port 60H into AL

 OUT OUT 60H, AL Write AL to port 60H

Example:

MOV AX, 1234H; Load AX with 1234H

MOV BX, AX; Copy AX to BX

PUSH AX; Save AX on stack

POP DX ; Retrieve it into DX

2. Arithmetic Instructions

These perform mathematical operations like addition, subtraction, multiplication, and

division.

Instruction Example Description

ADD ADD AX, BX AX = AX + BX

ADC ADC AL, 05H Add 5 with carry

SUB SUB DX, CX DX = DX - CX

SBB SBB AX, 10H Subtract with borrow

MUL MUL BX Multiply AX by BX (unsigned)

IMUL IMUL CX Multiply AX by CX (signed)

DIV DIV CX Divide AX by CX

IDIV IDIV BX Signed divide AX by BX

INC INC AX Increment AX

DEC DEC BX Decrement BX

Example:
MOV AX, 05H ; Load AX with 5

MOV BX, 02H ; Load BX with 2

ADD AX, BX ; AX = AX + BX (AX = 7)

SUB AX, 01H ; AX = AX - 1 (AX = 6)

MUL BX ; AX = AX * BX (AX = 12)

3. Logical Instructions

These instructions perform bitwise operations such as AND, OR, XOR, NOT, and shifting.

Instruction Example Description

AND AND AX, BX AX = AX & BX

OR OR AX, BX AX = AX | BX

XOR XOR AL, 0FFH Toggle all bits

NOT NOT DX Invert all bits

SHL SHL AX, 1 Shift left by 1 bit

SHR SHR AX, 1 Shift right by 1 bit

ROL ROL AL, 1 Rotate left by 1 bit

ROR ROR AL, 1 Rotate right by 1 bit

Example:

MOV AL, 0F0H ; AL = 11110000

AND AL, 0F3H ; AL = 11110000 AND 11110011 = 11110000

OR AL, 0FCH ; AL = 11110000 OR 11111100 = 11111100

XOR AL, 0FFH ; AL = 11111100 XOR 11111111 = 00000011

4. Control Transfer Instructions

These change the flow of execution by jumping or calling subroutines.

Instruction Example Description

JMP JMP NEXT Jump to label NEXT

JE / JZ JE END Jump if equal

JNE / JNZ JNE LOOP Jump if not equal

JG JG POSITIVE Jump if greater

JL JL NEGATIVE Jump if less

JC JC CARRYSET Jump if carry flag is set

CALL CALL FUNCTION Call subroutine

RET RET Return from subroutine

LOOP LOOP AGAIN Loop until CX = 0

Example:

MOV CX, 5

LOOP_LABEL:

DEC CX

JNZ LOOP_LABEL; Repeat until CX = 0

5. String Instructions

These handle blocks of data in memory for string operations.

Instruction Example Description

MOVS MOVS BYTE PTR ES: [DI], DS: [SI] Copy string from SI to DI

CMPS CMPS BYTE PTR DS: [SI], ES: [DI] Compare strings
SCAS SCAS BYTE PTR ES: [DI] Scan string for a value

LODS LODS BYTE PTR DS: [SI] Load string element into AL/AX

STOS STOS BYTE PTR ES: [DI] Store AL/AX into a string

Example:

MOV CX, 5 ; Set loop counter

REP MOVS BYTE PTR ES: [DI], DS: [SI] ; Copy CX bytes from DS:SI to ES:DI

6. Processor Control Instructions

These control CPU behavior by modifying flags and execution.

Instruction Example Description

STC STC Set carry flag

CLC CLC Clear carry flag

CMC CMC Complement carry flag

STD STD Set direction flag

CLD CLD Clear direction flag

HLT HLT Halt processor execution

NOP NOP No operation

Example:

STC ; Set carry flag

CLC ; Clear carry flag

HLT ; Halt execution

Review Questions
1. What are the two main components of the 8086 microprocessors?

2. What is the purpose of the Instruction Queue in the 8086?

3. What is memory segmentation in the 8086 microprocessors?

4. How is memory segmented in the 8086 microprocessors?

5. How does the 8086 generate a physical address from the segment address?

6. What is the function of the ALU in the Execution Unit (EU) of the 8086?

7. Explain the difference between Pointer and Index Registers and give examples.

8. Explain the role of the flag register in the 8086.

9. What is the function of the Bus Interface Unit (BIU) in the 8086?

10. What is the maximum size of the memory that can be addressed by the 8086?

11. What is the difference between the 8086 and 8088 microprocessor?

12. What are the different types of instruction formats in the 8086 microprocessor?

13. How does the 8086 handle interrupt requests?

14. What is the role of the Control Unit in the Execution Unit of the 8086?

15. What is the significance of the 16-bit flag register in the 8086?

16. What are the different addressing modes supported by the 8086 microprocessor?
Give 18. 19. 20. What is the role of String Instructions in 8086? List some common
string instructions.
21. Explain the arithmetic operations performed by the 8086. How does the processor
handle multiplication and division?