Question Bank 2024-25 GIFT (Autonomous) Bhubaneswar

Subject Name: Computer Organization Architecture Subject Code: (BTCA-T-PC-601)

Questions
Q Marks CO BTL By
Section-A
No
1 Define DMA? 2 4
What is the function of I/O interface? 2 4
2
3 What is peripheral device? 2 4
4 What is I/O device? 2 4
5 What is storage device? 2 4
6 Define communication device? 2 4
7 Define I/O subsystem? 2 4
8 Define I/O interface? 2 4
9 What is pipelining? 2 5
10 What is pipeline structure? 2 5
11 What is instruction pipeline? 2 5
12 What is Hazard? 2 5
13 What is data hazard? 2 5
14 What is structural hazard? 2 5
15 What is control hazard? 2 5
16 What is data dependency? 2 5
17 What do you mean operand forwarding? 2 5
18 Define NOP? 2 5
What is side-effect? 2 5
19
20 Define branch penalty instruction? 2 5
21 Define computing stage? 2 5
22 What do you mean by target instruction? 2 5
23 What is throughput? 2 5
24 What is speedup? 2 5
25 What do you mean by efficiency? 2 5
26 What is SISD? 2 5
27 What is SIMD? 2 5
28 What is MISD? 2 5
29 What is MIMD? 2 5
30 What do mean by Memory hierarchical? 2 6
What is cache memory? 2 6
31
32 Define Cache Hit? 2 6
33 Define Cache Miss? 2 6
34 What do you mean by cache access time? 2 6
35 What do you mean by miss penalty? 2 6
Draw the diagram of Memory hierarchical? 2 6
36
Draw the neat diagram of Hardwired control unit?
2 4
37
Draw the neat diagram of Micro-programmed 2 4
38
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 control unit?
39 What is cache mapping? 2 6
What is associated mapping? 2 6
40
What is direct mapping? 2 6
41
What is set-associated mapping? 2 6
42
43 What do you mean by Mode of data transfer in I/O? 2 4
44 What is programmed I/O? 2 4
45 What is interrupt initiated I/O? 2 4
46 What do you mean by memory cell operations? 2 6
47 Write down the characteristics of memory system? 2 6
48 What are the advantages of hardwired control unit? 2 4
What are the advantages of micro programmed
2 4
49 control unit?
50 What do you mean by control unit operations? 2 4
51 What is an interrupt? 2 4
52 What do you mean by Flynn’s classification? 2 5
Why MISD is theoretically possible but not in
2 5
53 practically?
What do you mean by Stages in pipelining? 2 5
54
What do you mean by clock cycle in the pipelining
2 5
55 concept?
56 What is pipelining performance? 2 5
What is 2-stages pipelining? 2 5
57
What is 4-stages pipelining? 2 4
58
What are the disadvantages of hardwired control
2 4
59 unit?
What are the disadvantages of micro programmed
2 4
60 control unit?
Define interface? 2 4
61
What is microprogrammed control? 2 4
62
What are the uses of interrupts? 2 4
63
What is microprogramming? 2 4
64
What are the steps taken when an interrupt occurs? 2 4
65
Define parallel processing? 2 5
66
67 Define interface? 2 4
68 Define hardware control unit? 2 4
69 Define I/O Transfer Mode? 2 4
70 List out the different types of I/O Transfer Mode? 2 4
71 Define I/O organization? 2 4
What is the difference between pipeline and non-
2 5
72 pipeline?
Write down the name of the different types of
2 5
73 pipelining?
What are the steps required for a pipelining
2 5
74 processor to process the instruction?
75 What are the types of dependencies? 2 5
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 What are the various stages in a Pipeline
2 5
76 execution?
77 What are the major characteristics of a Pipeline? 2 5
78 Define WT & WB. 2 6
79 What do you mean by volatile memory? 2 6
80 What do you mean by non-volatile memory? 2 6

Q Mark CO BTL
Section B
NO
Draw and explain Control unit of Basic computer
4 4
1 system.
Describe Flynn’s Classification in details with neat
4 5
2 diagram?
Write about hardware organization of micro
4 4
3 programmed control unit.
With a neat schematic, Explain about DMA controller
4 4
4 and its mode of data transfer
5 What is interrupt driven and DMA controller? 4 4
6 Write down the characteristics of peripheral device? 4 4
7 Write down the functions of interface I/O? 4 4
8 Explain input /output transfer mode. 4 4
9 What is direct memory access controller? 4 4
10 Memory Organization in Computer Architecture? 4 6
11 Types of Instructions in Computer Architecture? 4 5
12 Arithmetic Pipeline in Computer Architecture? 4 5
13 Control Hazards in Computer Architecture? 4 5
14 Data Hazards in Computer Architecture? 4 5
In the 4 stages pipelining, following instructions are
given. Calculate how many clock cycles are used to
complete the task and identify the hazard. 4 5
(i) ADD R1, R2, R3
15 (ii) SUB R3, R4, R5
In the 4 stages pipelining, following instruction is
given. Calculate how many clock cycles are used to
complete the task and identify the hazard. 4 5
N.B:- Here, 2 extra memories are used.
16 LOAD X(R1), R2
What is operand forwarding? Draw a pipeline
4 5
17 diagram for forwarding path?
18 Differentiate between SRAM and DRAM. 4 6
Write short notes:
(i)Computing stage
4 5
(ii)Branch penalty instruction
19 (iii)Target instruction
20 Differentiate between RAM and ROM. 4 6
Write short notes:
(i)Operand forwarding
4 5
(ii)No operation
21 (iii)Side-effect
22 What is RAM? Discuss the different types of RAMs. 4 6
23 Write short notes: 4 6
(i)Primary memory
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 (ii)Secondary memory
In the 4 stages pipelining, following instruction is
given. 2nd instruction is branch instruction and the
computation result addressed at Execution stage.
4 5
Calculate how many clock cycles are used to
complete the task.
24 ADD R1, R2, R3
25 Explain the types of peripheral devices. 4 4
Write short notes:
(i)Read operation 4 6
(ii)Write operation
26
What is cache memory? Write down the working
4 6
27 principle of Cache memory.
In the 4 stages pipelining, following instruction is
given. Calculate how many clock cycles are used to
complete the task and identify the hazard. 4 5
N.B:- Here, 1 extra memory is used.
28 LOAD X(R0), R1
Define the types of memory operations. 4 6
29
30 Explain the properties of memory hierarchical. 4 6
31 Explain the characteristics of memory system. 4 6
Write short notes:
(i)Register & Cache memory
4 6
(ii)Main memory
32 (iii)Disk drive & Backup storage.
33 Explain input device with examples. 4 4
34 Explain output device with examples. 4 4
Explain storage device with examples. 4 4
35
36 Explain communication device with examples. 4 4
37 Define branch penalty? 4 5
What is target instruction? Do an example of target
4 5
38 instruction of data hazard.
Differentiate between micro-instruction and micro
4 4
39 program?
What is NOP? Do an example of NOP operation of
4 5
40 data hazard.

Q
Section C Marks CO
NO
Describe Flynn’s Classification in details with neat
6 6
1 diagram?
Differentiate between Programmed I/O and Interrupt-
6 4
2 driven I/O.
What is Peripheral device? Explain the characteristics
6 4
3 of peripheral devices.
Distinguish between Microprogrammed Control unit
6 4
4 and Hardwired Control unit.
5 Explain DMA in details? 6 4
Control Hazards in Computer Architecture? 6 5
6
Data Hazards in Computer Architecture? 6 5
7
What is memory? Explain the Memory Cell operations
6 6
8 with diagram.
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 What is Pipeline? And also describe the performance
6 5
9 of pipeline?
10 Explain the types of Pipelining? 6 5
Explain the Cache mapping system? 6 6
11
Write short notes:
(i)Throughput
6 5
(ii)Speedup
12 (iii)Efficiency
Demonstrate the general configuration of Micro
6 4
13 programmed Control unit with a neat block diagram.
What is data hazard? Explain the methods for dealing
6 5
14 with data hazard?
Explain Pipelining Analogy with an example.
6 5
15
Explain the basic concepts of pipelining and compare
6 5
16 it with sequence processing with a neat diagram.
How the registers are contents in the pipeline?
6 5
17 Explain it with an example.
What are the problems faced in instruction pipeline? 6 5
18
With a neat schematic, Explain about DMA controller
6 4
21 and its mode of data transfer.
Demonstrate the general configuration of Hardwired
6 4
22 Control unit with a neat block diagram.
Define I/O interface? Write down the functions of I/O
6 4
25 interface.
26 What is ROM? Discuss the different types of ROMs. 6 6
What is computer memory system? Explain the
6 6
27 characteristics of memory system.
What is data hazard? Explain the methods for dealing
6 5
32 with data hazard?
In the 4 stages pipelining, following instructions are
given. Calculate how many clock cycles are used to
complete the task and identify the hazard.
(i) MUL A, B, R0
6 5
(ii) ADD R1, R0, R11
(iii) SUB R7, (R8), R11
(iv) DIV R11, R12, R5
33 (v) XOR R2, R10, R6
Do a 4-stages pipeline diagram, where the 3rd
instruction is branch instruction and the computation
result addressed at Execution stage. How many no. of 6 5
Branch penalty instructions not performing result and
36 which stage perform the target instruction.
37 Explain I/O device interface with diagram. 6 4
38 Briefly explain Programmed I/O with diagram. 6 4
With a neat diagram, explain how the hardwired
control unit determines the instruction after decoding 6 4
39 an instruction.

Q
Section D Marks CO BTL
No
Page 5
 1 What is data hazard? Explain briefly with diagram. 8 5
What is micro programmed control unit explain with
8 4
2 diagram?
In the 4-stages pipelining at the end of clock cycle 3 &
which type of buffer or latches workable? Briefly 8 5
3 explain it.
What is Hazard? Explain the types of hazards with
8 5
4 diagram.
What is hardware control unit explain briefly with
8 4
5 diagram?
Briefly explain mode of data transfer and its types with
8 4
6 diagram.
Briefly explain about the Peripheral devices and its
8 4
7 types with examples.
Briefly explain Memory Hierarchical and also explain
8 6
8 its properties.
What is Cache memory? Explain the Mapping function
of cache memory. 8 6
9
What is Structural hazard? Explain briefly with
8 5
10 diagram.

** BTL: Bloom’s Taxonomy Level

** CO: Course Outcomes

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