Module 3 Assignment
Uploaded by
Shweta KulkarniModule 3 Assignment
Uploaded by
Shweta KulkarniSRI VENKATESHWARA COLLEGE OF ENGINEERING
International Airport road, Vidyanagar, Bangalore-562157
Department of Electronics and CommunicationEngineering (NBA Accredited)
ASSIGNMENT -3
Course Name: VLSI Design Course Code: 18EC72
Sem/Sec: VII ‘A & B’ Faculty Name: Jayalakshmi.N
MODULE-2
1. Derive the expression for threshold voltage reduction in short channel effect.
2. With a neat sketch explain Narrow Channel Effects in MOS transistor.
3. Write a note on i) Sub threshold condition
ii) HOT electron effect
4. Describe Gate-to-Channel charge capacitances in cutoff, linear and saturation mode.
5. Briefly explain effect of full scaling on oxide capacitance, drain current and power
dissipation.
6. Derive the expression for equivalent large signal capacitance in junction capacitances.
MODULE-3
1. Sketch a 3-input NAND gate with transistor widths chosen to achieve effective rise
and fall resistance equal to that of a unit inverter(R). Annotate the gate with its gate
and diffusion capacitances.
2. Explain RC delay model with equivalent circuit of an inverter.
3. Define Elmore delay. Compute the Elmore delay for Vout in second order RC system.
4. Draw the schematic diagram of an 3-input NAND annotated with diffusion
capacitances and also conventional layout style of an inverter.
5. With a neat sketch calculate logic effort for 3-input NOR gate and 3-input NAND
gate.
6. With a neat logic diagram explain delay in multistage logic networks.
7. Design a 3-stage decoder and calculate logical effort, path effort, stage effort and
delay.
8. Design a circuit to compute F=AB+CD using NANDs and NORs with bubble
pushing.
9. Draw the logic symbol and schematic diagram for an expression AOI21 and calculate
its logical effort and parasitic delay.
10. Discuss asymmetric gates and skewed gates.
11. With a neat circuit diagram explain Pseudo-nMOS inverter DC transfer
characteristics.
12. With a neat circuit diagram and waveform explain Domino gates.
13. Briefly explain Cascode voltage switch logic with neat diagrams.
