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Microprocessor Module 4

The 8086 Microprocessor, designed by Intel in 1976, is a 16-bit processor with a powerful instruction set, capable of addressing up to 1MB of memory. It operates in two modes: Maximum mode for multi-processor systems and Minimum mode for single-processor systems, featuring a Bus Interface Unit (BIU) and Execution Unit (EU) for managing operations. The architecture includes general-purpose registers, segment registers, flag registers, and various addressing modes, allowing for efficient data handling and processing.

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1 views35 pages

Microprocessor Module 4

The 8086 Microprocessor, designed by Intel in 1976, is a 16-bit processor with a powerful instruction set, capable of addressing up to 1MB of memory. It operates in two modes: Maximum mode for multi-processor systems and Minimum mode for single-processor systems, featuring a Bus Interface Unit (BIU) and Execution Unit (EU) for managing operations. The architecture includes general-purpose registers, segment registers, flag registers, and various addressing modes, allowing for efficient data handling and processing.

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ytecy82
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 4

8086 Microprocessor
8086 Microprocessor
8086 Microprocessor
8086 Microprocessor is an enhanced version of
8085Microprocessor that was designed by Intel in 1976.
It is a 16-bit Microprocessor having 20 address lines and16 data
lines that provides up to 1MB storage.
It consists of powerful instruction set, which provides
operations like multiplication and division easily.
8086 Microprocessor
It supports two modes of operation, i.e. Maximum mode and
Minimum mode. Maximum mode is suitable for system
having multiple processors and Minimum mode is suitable for
system having a single processor.
Architecture of 8086
8086 Architecture
The architecture of 8086 microprocessor is composed of 2 major units, the BIU i.e., Bus
Interface Unit and EU i.e., Execution Unit.

Bus Interface Unit (BIU)

The Bus Interface Unit (BIU) manages the data, address and control buses.

The function of BIU is to:

● Fetch the instruction or data from memory.


● Write the data to memory.
● Write the data to the port.
● Read data from the port.
8086 Architecture
Execution Unit (EU)

The functions of execution unit are:

● To tell BIU where to fetch the instructions or data from.


● To decode the instructions.
● To execute the instructions.

The EU contains the control circuitry to perform various internal operations. A


decoder in EU decodes the instruction fetched memory to generate different
internal or external control signals required to perform the operation. EU has
16-bit ALU, which can perform arithmetic and logical operations on 8-bit as
well as 16-bit.
8086 Architecture
Instruction Queue

To increase the execution speed, BIU fetches as many as six instruction bytes
ahead to time from memory.

All six bytes are then held in first in first out 6 byte register called instruction
queue.
8086 Architecture
General Purpose Registers of 8086
These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to have AX,
BX, CX, and DX.

AX Register: AX register is also known as accumulator register that stores operands for arithmetic
operation like divided, rotate.
BX Register: This register is mainly used as a base register. It holds the starting base location of a
memory region within a data segment.
CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop counter.
DX Register: DX register is used to contain I/O port address for I/O instruction.
8085 Architecture
Segment Registers

In 8086 microprocessor, memory is divided into 4 segments as follow:

Memory segment of Intel 8086

Code Segment (CS): The CS register is used for addressing a memory location
in the Code Segment of the memory, where the executable program is stored.

Data Segment (DS): The DS contains most data used by program. Data are
accessed in the Data Segment by an offset address or the content of other
register that holds the offset address.

Stack Segment (SS): SS defined the area of memory used for the stack.

Extra Segment (ES): ES is additional data segment that is used by some of the
string to hold the destination data.
8086 segments
8086 Architecture
Flag Registers of 8086

Flag register in EU is of 16-bit.

Flags Register determines the current state of the processor. They are
modified automatically by CPU after mathematical operations.8086 has 9
flags and they are divided into two categories:

1.Conditional Flags

2.Control Flags
8086 Architecture
Conditional Flags

Conditional flags represent result of last arithmetic or logical instruction


executed. Conditional flags are as follows.

Carry Flag (CF): This flag indicates an overflow condition for unsigned
integer arithmetic.
Auxiliary Flag (AF): If an operation performed in ALU generates a carry/
barrow from lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7),
the AF flag is set.
8086 Architecture
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits
of the result contains even number of 1’s, the Parity Flag is set and for odd number
of 1’s, the Parity Flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is
reset.
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit.
If the result of operation is negative, sign flag is set.
Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF
indicates that the result has exceeded the capacity of machine.
8086 Architecture
Control Flags

Control flags are set or reset deliberately to control the operations of the
execution unit. Control flags are as follows:

Trap Flag (TP):

It is used for single step control.It allows user to execute one instruction of a
program at a time for debugging.When trap flag is set, program can be run in
single step mode.

Interrupt Flag (IF):

It is an interrupt enable/disable flag.


8086 Architecture
Direction Flag (DF):

It is used in string operation.

If it is set, string bytes are accessed from higher memory address to lower
memory address.

When it is reset, the string bytes are accessed from lower memory address to
higher memory address.
8086 Flag register
8086 Addressing modes
Addressing mode is the manner in which an operand is given in an
instruction
Classification of Addressing Mode

There are mainly 8 addressing modes of an 8086 microprocessor.


1. Immediate Addressing Mode
2. Direct Addressing Mode
3. Register Addressing Mode
4. Register Indirect Addressing Mode
5. Based Addressing Mode
6. Indexed Addressing Mode
7. Based Indexed Addressing Mode
1. Immediate Addressing Mode
In this type of Addressing Mode immediate data is the part of the
instruction itself.
Example: MOV Ax, 0020H 16- bit data transfer

2. Absolute/ Direct Addressing Mode


In Absolute/ Direct Addressing Mode the effective address of memory
location where operand is present is written directly in the instruction.
Example: Mov Ax, [5000H]
3. Register Addressing Mode

Register Addressing Mode the data is stored in a register and it is referred


using the particular register.

Example: MOV Ax, Bx ;copies the contents of the 16-bit BX register into ;
the 16-bit AX register

ADD BX, AX
4. Register Indirect Addressing
In this addressing mode effective address of memory is
calculated from baseregister (BX) or index register (SI, DI),
specified in the instruction. Then it is added to the segment
register to generate physical address.

5.Based mode – In this the effective address is the sum of base


register and displacement.
Example:
MOV AL, [BP+ 0100]
6.Indexed mode – In this type ofaddressing mode the
effective address is sum of index register and
displacement.
Example:
MOV AX, [SI+2000]
MOV AL, [DI+3000]
7.Based indexed mode – In this the effective address is sum of base
register and index register.
Base register: BX, BP
Index register: SI, DI
The physical memory address is calculated according to the base
register.
Example:
MOV AL, [BP+SI]
MOV AX, [BX+DI]

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