Computer Architecture and Organization

(CSE2003)

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 Module 5
Interfacing and Communication

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Input Output Devices
The computer is useless without some kind of interface to the
outside world.
There are many different devices which we can connect to the
computer system; keyboards, VDUs and disk drives are some of
the more familiar ones.
Irrespective of the details of how such devices are connected we
can say that all I/O is governed by three basic strategies.
• Programmed I/O
• Interrupt driven I/O
• Direct Memory Access (DMA)

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Programmed I/O

• In programmed I/O all data transfers between the computer system

and external devices are completely controlled by the computer
program.
• Programmed I/O is probably the most common I/O technique
because it is very cheap and easy to implement, and in general does
not introduce any unforeseen hazards.

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Contd..
• It is a method of transferring data between the CPU and a peripheral, such
as a network adapter or an ATA storage device. In general, programmed I/O
happens when software running on the CPU uses instructions that access
I/O address space to perform data transfers to or from an I/O device.
• The programmed I/O, interface is grouped into different modes that
correspond to different transfer rates. The electrical signalling among the
different modes is similar-only the cycle time between transactions is
reduced in order to achieve a higher transfer rate.
• The PIO modes require a great deal of CPU overhead to configure a data
transaction and transfer the data. Because of this inefficiency, the DMA
interface was created to increase performance.
• The simple digital logic required to implement a PIO transfer still makes this
transfer method useful today, especially if high transfer rates are not
required like in embedded systems, or with FPGA chips where PIO mode
can be used without significant performance loss.
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Interrupt driven I/O
• It is a way of controlling input/output activity in which a peripheral or
terminal that needs to make or receive a data transfer sends a signal that
causes a program interrupt to be set.
• At a time appropriate to the priority level of the I/O interrupt, relative to
the total interrupt system, the processor enters an interrupt service routine
(ISR). The function of the routine will depend upon the system of interrupt
levels and priorities that is implemented in the processor.
• In a single-level single-priority system there is only a single I/O interrupt-
the logical OR of all the connected I/O devices.
• The associated interrupt service routine polls the peripherals to find the
one with the interrupt status set.

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 Handshaking and Buffering

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Handshaking
• Handshaking is a I/O control method to synchronize I/O devices with the
microprocessor. As many I/O devices accepts or release information at a much
slower rate than the microprocessor, this method is used to control the
microprocessor to work with a I/O device at the I/O devices data transfer rate.
• Handshaking is an automated process of negotiation that dynamically sets
parameters of a communications channel established between two entities
before normal communication over the channel begins.
• It follows the physical establishment of the channel and precedes normal
information transfer. The handshaking process usually takes place in order to
establish rules for communication when a computer sets about communicating
with a foreign device. When a computer communicates with another device like a
modem, printer, or network server, it needs to handshake with it to establish a
connection.

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Handshaking
• Handshaking can negotiate parameters that are acceptable to equipment and
system at both ends of the communication channel, including information
transfer rate, coding alphabet, parity, interrupt procedure, and other protocol or
hardware features. Handshaking is a technique of communication between two
entities. However, within TCP/IP RFCs, the term “handshake” is most used to
reference the TCP three-way handshake.
• A simple handshaking protocol might only involve the receiver sending a message
meaning “I received your last message and I am ready for you to send me another
one.” A more complex handshaking protocol might allow the sender to ask the
receiver if it is ready to receive or for the receiver to reply with a negative
acknowledgement meaning “I did not receive your last message correctly, please
resend it” (e.g., if the data was corrupted in route).

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Handshaking Example
• Supposing that we have a printer connected to a system. The printer
can print 100 characters/second, but the microprocessor can send
much more information to the printer at the same time.
• That’s why, just when the printer gets it enough data to print it places
a logic 1 signal at its Busy pin, indicating that it is busy in printing.
• The microprocessor now tests the busy bit to decide if the printer is
busy or not. When the printer will become free it will change the busy
bit and the microprocessor will again send enough amounts of data to
be printed. This process of interrogating the printer is called
handshaking.
• Handshaking facilitates connecting relatively heterogeneous systems
or equipment over a communication channel without the need for
human intervention to set parameters.
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 Drawbacks of Programmed and
Interrupt-Driven I/O
• Programmed and Interrupt-Driven I/O suffer from two inherent
drawbacks:
1. The I/O transfer rate is limited by the speed with which the processor can
test and service a device.
2. The processor is tied up in managing an I/O transfer; a number of
instructions must be executed for each I/O transfer.

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Interrupt
• The interrupt is a signal emitted by hardware or software when a
process or an event needs immediate attention.
• It alerts the processor to a high-priority process requiring interruption of the
current working process.
• In I/O devices one of the bus control lines is dedicated for this purpose and is
called the Interrupt Service Routine (ISR).

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 Hardware Interrupt
• In a hardware interrupt, all the devices are connected to the
Interrupt Request Line.
1. A single request line is used for all the n devices. To request an
interrupt, a device closes its associated switch.
2. When a device requests an interrupt, the value of INTR is the logical
OR of the requests from individual devices.

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Direct Memory Access
• When large volumes of data are to
be moved, a more efficient
technique is DMA involves an
additional module on the system
bus.
• The DMA module in given Figure
can mimic the processor and,
indeed, of taking over control of
the system from the processor.
• It needs to do this to transfer data
to and from memory over the
system bus required: direct
memory access (DMA).

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Contd..
• DMA module must use the bus only when the processor does not need it.
• It must force the processor to suspend operation temporarily (i.e. Cycle
Stealing).
• When the processor wishes to read or write a block of data, it issues a
command to the DMA module, by sending to the DMA module the
following information:
1. Whether a read or write is requested, using the read or write control line
between the processor and the DMA module.
2. The address of the I/O device involved, communicated on the data lines.
3. The starting location in memory to read from or write to, communicated on the
data lines and stored by the DMA module in its address register.
4. The number of words to be read or written, again communicated via the data
lines and stored in the data count register.
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Contd..
The processor then continues with other work. It has delegated this I/O
operation to the DMA module.
• The DMA module transfers the entire block of data, one word at a
time, directly to or from memory, without going through the
processor.
• When the transfer is complete, the DMA module sends an interrupt
signal to the processor.
• Thus, the processor is involved only at the beginning and end of the
transfer.

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Contd..
If multiple interrupts have occurred, how does the processor decide
which one to process.
• A more efficient technique is to use a daisy chain, which provides, in effect, a
hardware poll.
• For interrupts, all I/O modules share a common interrupt request line.
• The interrupt acknowledge line is daisy chained through the modules. When
the processor senses an interrupt, it sends out an interrupt acknowledge.
• This signal propagates through a series of I/O modules until it gets to a
requesting module. The requesting module typically responds by placing a
word on the data lines.
• This word is referred to as a vector and is either the address of the I/O
module or some other unique identifier.
• In either case, the processor uses the vector as a pointer to the appropriate
device-service routine. This avoids the need to execute a general
interrupt-service routine first. This technique is called a vectored interrupt.
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Vectored Interrupts
• In vectored interrupts, a device requesting an interrupt
identifies itself directly by sending a special code to the
processor over the bus.
• This enables the processor to identify the device that
generated the interrupt. The special code can be the starting
address of the ISR or where the ISR is located in memory and is
called the interrupt vector.

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Bus Arbitration
There is another technique that makes use of vectored interrupts, and
that is bus arbitration.
• With bus arbitration, an I/O module must first gain control of the bus
before it can raise the interrupt request line.
• Thus, only one module can raise the line at a time. When the
processor detects the interrupt, it responds on the interrupt
acknowledge line.
• The requesting module then places its vector on the data lines.

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Buffering
A buffer is a temporary storage location for data while the data is being
transferred. A buffer is often used for the following purposes:
• Small I/O requests can be collected into a buffer, and the overhead of making many
relatively expensive system calls can be greatly reduced.
• A collection buffer of this type can be sized and handled so that the actual physical
I/O requests made to the operating system match the physical characteristics of the
device being used.
• Many data file structures, such as the f77 and cos file structures, contain
control words. During the write process, a buffer can be used as a work
area where control words can be inserted into the data stream (a process
called blocking).
• The blocked data is then written to the device. During the read process, the
same buffer work area can be used to examine and remove these control
words before passing the data on to the user (deblocking ).

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Contd..
• When data access is random, the same data may be requested many times.
• A cache is a buffer that keeps old requests in the buffer in case these requests are
needed again. A cache that is sufficiently large and/or efficient can avoid a large
part of the physical I/O by having the data ready in a buffer.
• When the data is often found in the cache buffer, it is referred to as having a high
hit rate. For example, if the entire file fits in the cache and the file is present in the
cache, no more physical requests are required to perform the I/O. In this case, the
hit rate is 100%.
• Running the disks and the CPU in parallel often improves performance; therefore,
it is useful to keep the CPU busy while data is being moved. To do this when
writing, data can be transferred to the buffer at memory-to- memory copy speed
and an asynchronous I/O request can be made. The control is then immediately
returned to the program, which continues to execute as if the I/O were complete
(a process called write-behind). A similar process can be used while reading; in
this process, data is read into a buffer before the actual request is issued for it.
When it is needed, it is already in the buffer and can be transferred to the user at
very high speed. This is another form or use of a cache.
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Contd..
• It is the process of transferring data between a program and an
external device, The process of optimizing I/O consists primarily of
making the best possible use of the slowest part of the path between
the program and the device.
• The slowest part is usually the physical channel, which is often slower
than the CPU or a memory-to-memory data transfer.
• The time spent in I/O processing overhead can reduce the amount of
time that a channel can be used, thereby reducing the effective
transfer rate. The biggest factor in maximizing this channel speed is
often the reduction of I/O processing overhead.

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Interrupt overhead
The interrupt overhead is caused by context switching.
• On interrupt handler entry, the context of the current process and its thread must be
saved.
• On exit, it must be restored.

Another negative effect of context switching is cache usage.

• On handler entry, memory locations different from the memory locations in the cache are
used, and therefore cache updates are required.
• In a similar way, the interrupted process suffers from the interrupt: the cache it was using is
disturbed, and cache updates are required.

• Supposed that a request can be served in 11.5 ms, and that an interrupt is serviced in 32.5ms .
Therefore, we can calculate the interrupt overhead for an interrupt that services one packet: 32.5
- 11.5 = 21 ms.

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