Circuits, devices and systems series 9

VLSI
TESTING
digital and mixed
analogue/digital
techniques

STANLEY L. HURST

the institution of electrical engineers

IEE CIRCUITS, DEVICES AND SYSTEMS SERIES 9

Series Editors: Dr D. G. Haigh

Dr R. S. Soin
DrJ. Wood

VLSI
TESTING
digital and mixed
analogue/digital
techniques
Other volumes in this series:
Volume 1 GaAs technology and its impact on circuits and systems
D. G. Haigh and J. Everard (Editors)
Volume 2 Analogue IC design: the current-mode approach
C. Toumazou, F. J. Lidgey and D. G. Haigh (Editors)
Volume 3 Analogue-digital ASICs R. S. Soin, F. Maloberti and
J. Franca (Editors)
Volume 4 Algorithmic and knowledge-based CAD for VLSI
G. E. Taylor and G. Russell (Editors)
Volume 5 Switched-currents: an analogue technique for digital technology
C. Toumazou, J. B. Hughes and N. C. Battersby (Editors)
Volume 6 High frequency circuits F. Nibler and co-authors
Volume 7 MMIC design I. D. Robertson (Editor)
Volume 8 Low-power HF microelectronics G. A. S. Machado (Editor)
VLSI
TESTING
digital and mixed
analogue/digital
techniques

STANLEY L. HURST

The Institution of Electrical Engineers

Published by: The Institution of Electrical Engineers, London,
United Kingdom

© 1998: The Institution of Electrical Engineers

Reprinted with corrections 1998

This publication is copyright under the Berne Convention and the

Universal Copyright Convention. All rights reserved. Apart from any fair
dealing for the purposes of research or private study, or criticism or
review, as permitted under the Copyright, Designs and Patents Act, 1988,
this publication may be reproduced, stored or transmitted, in any forms or
by any means, only with the prior permission in writing of the publishers,
or in the case of reprographic reproduction in accordance with the terms
of licences issued by the Copyright Licensing Agency. Inquiries
concerning reproduction outside those terms should be sent to the
publishers at the undermentioned address:

The Institution of Electrical Engineers,

Michael Faraday House,
Six Hills Way, Stevenage,
Herts. SG1 2AY, United Kingdom

While the author and the publishers believe that the information and
guidance given in this work is correct, all parties must rely upon their own
skill and judgment when making use of it. Neither the author nor the
publishers assume any liability to anyone for any loss or damage caused
by any error or omission in the work, whether such error or omission is
the result of negligence or any other cause. Any and all such liability is
disclaimed.

The moral right of the author to be identified as author of this work has
been asserted by him/her in accordance with the Copyright, Designs and
Patents Act 1988.

British Library Cataloguing in Publication Data

A CIP catalogue record for this book

is available from the British Library

ISBN 0 85296 901 5

Typeset by Euroset, Alresford

Printed in England by Short Run Press Ltd., Exeter

If you truly want to understand something,
try changing it
Kurt Lewin
 Contents

Preface xi

Acknowledgments xiii
List of symbols and abbreviations xv
1 Introduction 1
1.1 The need for testing 1
1.2 The problems of digital testing 7
1.3 The problems of analogue testing 9
1.4 The problems of mixed analogue/digital testing 11
1.5 Design for test 11
1.6 Printed-circuit board (PCB) testing 13
1.7 Software testing 15
1.8 Chapter summary 16
1.9 Further reading 16
2 Faults in digital circuits 19
2.1 General introduction 19
2.2 Controllability and observability 20
2.3 Fault models 25
2.3.1 Stuck-at faults 26
2.3.2 Bridging faults 30
2.3.3 CMOS technology considerations 31
2.4 Intermittent faults 35
2.5 Chapter summary 38
2.6 References 40

3 Digital test pattern generation 43

3.1 General introduction 43
3.2 Test pattern generation for combinational logic circuits 47
3.2.1 Manual test pattern generation 48
3.2.2 Automatic test pattern generation 48
viii Contents

3.2.2.1 Boolean difference method 51

3.2.2.2 Roth's D-algorithm 55
3.2.2.3 Developments following Roth's D-algorithm 63
3.2.3 Pseudorandom test pattern generation 67
3.3 Test pattern generation for sequential circuits 70
3.4 Exhaustive, nonexhaustive and pseudorandom test pattern generation 73
3.4.1 Exhaustive test pattern generators 73
3.4.2 Nonexhaustive test pattern generators 74
3.4.3 Pseudorandom test pattern generators 75
3.4.3.1 Linear feedback shift registers (LFSRs) 76
3.4.3.2 Cellular automata (CAs) 90
3.5 /DD(Zand CMOS testing 95
3.6 Delay fault testing 105
3.7 Fault diagnosis 108
3.8 Chapter summary 110
3.9 References 112

4 Signatures and self test 119

4.1 General introduction 119
4.2 Input compression 120
4.3 Output compression 124
4.3.1 Syndrome (ones-count) testing 125
4.3.2 Accumulator-syndrome testing 128
4.3.3 Transition count testing 129
4.4 Arithmetic, Reed-Muller and spectral coefficients 130
4.4.1 Arithmetic and Reed-Muller coefficients 131
4.4.2 The spectral coefficients 133
4.4.3 Coefficient test signatures 138
4.5 Signature analysis 141
4.6 Online self test 153
4.6.1 Information redundancy 153
4.6.1.1 Hamming codes 157
4.6.1.2 Two-dimensional codes 160
4.6.1.3 Berger codes 161
4.6.1.4 Residue codes 163
4.6.2 Hardware redundancy 169
4.6.3 Circuit considerations 175
4.7 Self test of sequential circuits 188
4.8 Multiple-output overview 191
4.9 Chapter summary 193
4.10 References 195

5 Structured design for testability (DFT) techniques 201

5.1 General introduction 201
5.2 Partitioning and ad hoc methods 201
5.3 Scan-path testing 206
5.3.1 Individual I/O testing 211
5.3.2 Level-sensitive scan design (LSSD) 211
5.3.3 Further commercial variants 218
5.3.4 Partial scan 225
5.4 Boundary scan and IEEE standard 1149.1 230
5.5 Offline built-in self test 241
5.5.1 Built-in logic block observation (BILBO) 242
5.5.2 Cellular automata logic block observation (CALBO) 264
 Contents ix

5.5.3 Other BIST techniques 274

5.6 Hardware description languages and test 286
5.7 Chapter summary 289
5.8 References 291
Testing of structured digital circuits and microprocessors 297
6.1 Introduction 297
6.2 Programmable logic devices 298
6.2.1 Programmable logic arrays 298
6.2.1.1 Offline testable PLA designs 306
6.2.1.2 Online testable PLA designs 311
6.2.1.3 Built-in PLA self test 314
6.2.2 Programmable gate arrays 320
6.2.3 Other programmable logic devices 323
6.3 Read-only memory testing 329
6.4 Random-access memory testing 331
6.4.1 Offline RAM testing 333
6.4.2 Online RAM testing 337
6.4.3 Buried RAMs and self test 345
6.5 Microprocessors and other processor testing 347
6.5.1 General processor test strategies 350
6.5.2 The central processing unit 352
6.5.3 Fault-tolerant processors 355
6.6 Cellular arrays 362
6.7 Chapter summary 371
6.8 References 372

Analogue testing 381

7.1 Introduction 381
7.2 Controllability and observability 382
7.3 Fault models 385
7.4 Parametric tests and instrumentation 386
7.5 Special signal processing test strategies 392
7.5.1 DSP test data 392
7.5.2 Pseudorandom d.c. test data 395
7.6 The testing of particular analogue circuits 398
7.6.1 Filters 398
7.6.2 Analogue to digital converters 403
7.6.3 Digital to analogue converters 414
7.6.4 Complete A/D subsystems 419
7.7 Chapter summary 421
7.8 References 422
Mixed analogue/digital system test 427
8.1 Introduction 427
8.2 Mixed-signal user-specific ICs 430
8.3 Partitioning, controllability and observability 436
8.4 Offline mixed-signal test strategies 441
8.4.1 Scan-path testing 441
8.4.2 Built-in self-test strategies 446
8.4.3 Built-in analogue test generators 450
8.5 Boundary scan and IEEE standard 1149.4 457
8.6 Chapter summary 470
8.7 References 471
x Contents

9 The economics of test and final overall summary 477

9.1 Introduction 477
9.2 A comparison of design methodologies and costs 478
9.3 The issues in test economics 484
9.4 Economic models 489
9.4.1 Custom ICs 489
9.4.2 The general VLSI case 490
9.4.3 Test strategy planning resources 496
9.5 Final overall summary 499
9.5.1 The past and present 499
9.5.2 The future 503
9.6 References 510
Appendix A Primitive polynomials for n< 100 515

Appendix B Minimum cost maximum length cellular automata for n < 100 519

Appendix C Fabrication and yield 523

Index 527
 Preface

Historically, the subject of testing has not been one which has fired the
imagination of many electronic design engineers. It was a subject rarely
considered in academic courses except, perhaps as the final part of some
laboratory experiment or project, and then only to confirm the correct (or
incorrect!) working of some already-designed circuit. Hov/ever, the vast
increase in on-chip circuit complexity arising from the evolution of LSI and
VLSI technologies has brought this subject into rightful prominence, making
it an essential part of the overall design procedure for any complex circuit or
system.
The theory and practice of microelectronic testing has now become a
necessary part of both IC design and system design using ICs. It is a subject
area which must be considered in academic courses in microelectronic
design, and which should be understood by all practising design engineers
who are involved with increasingly complex and compact system
requirements.
Written as a self-contained text to introduce all aspects of the subject, this
book is designed as a text for students studying the subject in a formal taught
course, but contains sufficient material on more advanced concepts in order
to be suitable as a reference text for postgraduates involved in design and test
research. Current industrial practice and the economics of testing are also
covered, so that designers in industry who may not have previously
encountered this area may also find information of relevance to their work.
The book is divided into nine principal chapters, plus three appendices.
Chapter 1 is an introductory chapter, which explains the problems of
microelectronic testing and the increasing need for design for test (DFT)
techniques. Chapter 2 then continues with a consideration of the faults which
may arise in digital circuits, and introduces the fundamentals of
controllability, observability, fault models and exhaustive versus non-
exhaustive test. This consideration of digital circuit testing continues in
xii Preface

Chapter 3, where circuit simulation, automatic test pattern generation

(ATPG), fault coverage, the particular test requirements of CMOS
technology and other fundamentals are covered.
Chapter 4 surveys some of the techniques which have been proposed to
simplify the testing procedures for combinational logic networks, largely with
the objective of providing a simple final faulty/fault-free answer from the test.
These include signature analysis and other methods which usually involve
some form of counting of the logic signals which are generated during the
test procedure. The following chapter, Chapter 5, continues these consider-
ations, introducing structured DFT techniques such as scan testing which
forms the basis of most of the currently-employed VLSI test techniques.
Chapter 6 is a survey of the means of testing very specific digital
architectures, including microprocessors, ROM, RAM and PLA circuits,and
also cellular arrays.
Chapters 7 and 8 move on from the considerable volume of development
for testing digital circuits to analogue and mixed analogue/digital circuit test.
This is a more recent area of concern than the digital area, but one of rapidly
increasing importance in view of the growing mixed analogue/digital signal
processing interests — 'systems on a chip'. Chapter 7, therefore, considers
analogue testing fundamentals, including instrumentation and how much
parametric testing the system designer may need to do on bought-in micro-
electronic parts. Chapter 8 then considers mixed analogue/digital testing,
including partitioning and the possibility of applying some of the established
digital DFT techniques to the analogue area. Other concepts still being
researched will also be mentioned.
Finally, Chapter 9 looks at a wider scene rather than at specific test
methodologies. This includes a consideration of the economics of test and
design for test, and future possible expectations.
The book assumes that readers are already familiar with basic electronic
circuits, both digital and analogue, and with microelectronic fabrication
technologies, both bipolar and MOS. The importance of computer-aided
design (CAD) in circuit and system synthesis is also assumed to be known.
The mathematics involved in some sections should be well within the
knowledge of the majority of readers, and therefore the text as a whole
should be straightforward to follow, and hopefully helpful to many.

Stanley L. Hurst
 Acknowledgments

I would like to acknowledge the work of the many pioneers who have
contributed to our present state of knowledge about and application of
testing methodologies for microelectronic circuits and systems, oftimes with
belated encouragement from the manufacturing side of industry.
Conversations with many of these people over the years have added greatly to
my awareness of this subject area, and the many References given in this text
are therefore dedicated to them.
On a more personal note, may I thank former research colleagues at the
University of Bath, England, and academic colleagues in electronic systems
engineering at the Open University who have been instrumental in helping
my appreciation of the subject. Also very many years of extremely pleasant co-
operation with the VLSI design and test group of the Department of
Computer Science of the University of Victoria, Canada, must be
acknowledged. To them and very many others, not excluding the students
who have rightfully queried many of my loose statements, specious arguments
or convoluted mathematical justifications, my grateful thanks.
Finally, I must acknowlege the cheerful help provided by the administrative
and secretarial staff of the Faculty of Technology of the Open University, who
succeeded in translating my original scribbles into recognisable text. In
particular, may I thank Carol Birkett, Angie Swain and Lesley Green for their
invaluable assistance. Any errors remaining in the text are entirely mine!

S.L.H.
 List of symbols and abbreviations

The following are the symbols and abbreviations that may be encountered in
VLSI testing literature. Most but not necessarily all will be found in this text.

ABSC analogue boundary scan cell

ADC analogue to digital converter
AI artificial intelligence
ALU arithmetic logic unit
ASIC application-specific intregrated circuit (see also
CSIC and USIC)
ASM algorithmic state machine
ASR analogue shift register
ASSP application-specific standard part
A-to-D analogue to digital
ATE automatic test equipment
ATPG automatic test pattern generation

BIC built-in current (testing)

BiCMOS bipolar/CMOS technology
BDD binary decision diagram
BILBO built-in logic block observation
BIST built-in self test
BJT bipolar junction transistor
BSC boundary scan cell
BSDL boundary scan description language
BSR boundary scan register

C capacitor
CA cellular automata
CAD computer-aided design
xvi List of symbols and abbreviations

CALBO cellular automata logic block observation

CAE computer-aided engineering
CAM computer-aided manufacture
CAT computer-aided test
CCD charge-coupled device
CFR constant failure rate
CML current-mode logic
CMOS complementary MOS
CPU central processing unit
CSIC custom or customer-specific IC
CTF controllability transfer factor
CUT circuit under test

DA design automation
DAC digital to analogue converter
DBSC digital boundary scan cell
DDD defect density distribution
DEC double error correction
DED double error detection
DFM design for manufacturing
DFR decreasing failure rate
DFT design for test, or design for testability
DIL or DIP dual-inline package, or dual-inline plastic package
DL default level
DMOS dynamic MOS
DR data register
DRC design rule checking
DSP digital signal processing
D-toA digital to analogue
DUT device under test

EAROM electrically alterable ROM

ECAD electronic computer-aided design
ECL emitter-coupled logic
EEPROM electrically erasible PROM
EPLD electrically programmable logic device
EPROM erasible programmable ROM
E2PROM electrically erasible PROM
ERC electrical rules checking
eV electron volt

FC fault cover or coverage

FET field effect transistor
FFT fast Fourier transform
FPGA field-Droerammable 2ate arrav
 List of symbols and abbreviations xvii

FPLA field-programmable logic array

FPLS field-programmable logic sequencer
FRAM ferroelectric random-access memory
FRU field replacable unit
FTD full technical data (cf. LTD)

GaAs gallium arsenide

GDSII graphics design style, version II (a mask pattern
standard)
Ge germanium
GHz gigahertz
GPIB general purpose instrumentation bus, electrically
identical to HPIB bus

HDL hardware description language

HILO a commercial simulator for digital circuits

IC integrated circuit
Q
quiescent current in CMOS
IEE Institution of Electrical Engineers
IEEE Institute of Electrical and Electronics Engineers
IFA inductive fault analysis
IFR increasing failure rate
IGFET insulated gate FET
I/O input/output
IR instruction register
ISL integrated Schottky logic
quiescent current in CMOS

JEDEC Joint Electron Device Engineering Council

JFET junction FET
JIT just in time (manufacture)
JTAG Joint Test Action Group

k 1000
K 1024
kHz kilohertz

L inductor, or length in MOS technology

X lambda, a unit of length in MOS layout design
LAN local area network
LASAR logic automated stimulus and response
LCA logic cell array
LCC leaded ceramic chip carrier
LCCC leadless ceramic chip carrier
xviii List of symbols and abbreviations

LFSR linear feedback shift register

LSB least significant digit
LSI large scale integration
LSSD level-sensitive scan design
LSTTL low-power Schottky TTL
LTD limited technical data (cf. FTD)

MCM multichip module

MHz megahertz
mil one thousandth of an inch
MIPS million instructions per second
MISR multiple input signature register
MOS metal-oxide-semiconductor
MOST MOS transistor
MPGA mask-programmable gate array
MPLD mask-programmable logic device
ms millisecond
MSB most significant bit
MSD most significant digit
MSI medium scale integration
MTBF mean time between failure
MTTR mean time to repair

NFF no fault found

nMOS n-channel MOS
NRE nonrecurring engineering
ns nanosecond (10~9)

OEM original equipment manufacturer

op. amp. operational amplifier
OTA operational transconductance amplifier
OTF observability transfer function

PAL programmable array logic

PCB printed-circuit board
PDM process device monitor (see also PED and PMC)
PED process evaluation device (see also PDM and PMC)
PG pattern generation
PGA pin grid array, or programmable gate array
PLA programmable logic array
PLCC plastic leaded chip carrier
PLD programmable logic device
PLS programmable logic sequencer
PMC process monitoring circuit (see also PDM
and PED)
 List of symbols and abbreviations xix

pMOS p-channel MOS

PODEM path-oriented decision making (algorithm)
POST power-on self test
PRPG pseudorandom pattern generation
PROM programmable read-only memory
ps picosecond (10~12 s)
PSA parallel signature analyser
PUC per-unit cost

QCM quiescent current monitoring

QIL quad inline (package)
QTAG Quality Test Action Group

R resistor
RAM random-access memory
RAPS random path sensitising
RAS random access scan
ROM read-only memory
RTL register transfer language
RTOK retest OK

S-A or s-a stuck-at

s-a-0 stuck-at 0
s-a-1 stuck-at 1
SAFM stuck-at fault model
SASP signature analysis and scan path
SDI scan data in
SDO scan data out
SEC single error correction
SED single error detection
SEM scanning electron microscope
SIA Semiconductor Industry Association
SisN4 silicon nitride
SiO2 silicon dioxide
SMD surface mount device
SNR signal to noise ratio
SOI silicon-on-insulator
SOS silicon-on-sapphire
SPICE simulation program, integrated circuit emphasis
SRAM static read-only memory
SSI small scale integration
SSR serial shadow register
STL Schottky transistor logic
STR structured test register
STTL Schottky TTL
xx List of symbols and abbreviations

TC test coverage
TAP test access port
TCK, TMS, TDI, TDO boundary-scan terminals of IEEE standard 1149.1
TDD test directed diagnosis
TDL test description language
TMR triple modular redundancy
TPG test pattern generation (see also ATPG)
TPL test programming language
TQM total quality management
TTL transistor-transistor logic

UCA uncommitted component array

ULSI ultra large scale integration
UP microprocessor
USIC user-specific IC (preferable term to ASIC)
UUT unit under test

vBB d.c. base supply voltage

d.c. collector supply voltage
d.c. drain supply voltage
d.c. emitter supply voltage
d.c. gate supply voltage
V ss d.c. source supply voltage
VDU visual display unit
VHDL very high speed hardware description language
VHSIC very high speed IC
VLSI very large scale integration
VMOS a MOS fabrication technology

W width in MOS technology

WSI wafer scale integration

production or wafer yield

 Chapter 1
Introduction

1.1 The need for testing

The design and production of the majority of manufactured products usually
involves a rigorous design activity followed by detailed testing and evaluation
of prototypes before volume production is begun. Once in production,
continuous quality control of components and assembly is desirable, but
comprehensive testing of each finished item is not usually affordable.
However, the more sophisticated the product, or the components used within
the product, then the more need there will be to try to ensure that the end
product is fully functional. The ability to test end products as com-
prehensively as possible within a given budget or time constraint is therefore
a universal problem.
Electronics, and here more specifically microelectronics, has the
fundamental feature that, in contrast to mechanical and electromechanical
devices, visual inspection is of very little use. Parametric or functional testing
must be used. The range of testing involves both the IC manufacturer and the
original equipment manufacturer (OEM), in total including the following
principal activities:
(i) tests by the IC manufacturer (vendor) to ensure that all the fabrication
steps have been correctly implemented during wafer manufacture (IC
fabrication checks);
(ii) tests to ensure that prototype ICs perform correctly in all respects (IC
design checks);
(iii) tests to ensure that subsequent production ICs are defect free (IC
production checks);
(iv) possibly tests by the OEM of incoming ICs to confirm their functionality
(acceptance tests);
(v) tests by the OEM of final manufactured products (product tests).
2 VLSI testing: digital and mixed analogue/digital techniques

The first of these five activities is the sole province of the vendor, and does not
involve the OEM in any way. The vendor normally incorporates 'drop-ins'
located at random positions on the wafer, these being small circuits or
geometric structures from which the correct resitivity and other parameters
of the wafer fabrication can be verified before any functional checks are
undertaken on the surrounding circuits. This is illustrated in Figure 1.1. We
will have no occasion to consider wafer fabrication tests any further in this
text.

Figure 1.1 The vendor's check on correct wafer fabrication, using drop-in test circuits
at selected points on the wafer. These drop-ins may be alternatively known
as process evaluation devices (PEDs), process device monitors (PDMs),
process monitoring circuits (PMCs), or similar terms by different IC
manufacturers (Photo courtesy Micro Circuit Engineering, UK)

In the case of standard off the shelf ICs, available for use by any OEM, the
next two test activities are also the sole responsibility of the vendor. However,
in the case of customer-specific ICs, usually termed ASICs (application-
specific ICs) or more precisely USICs (user-specific ICs), the OEM is also
involved in phase (ii) in order to define the functionality and acceptance
details of the custom circuit. The overall vendor/OEM interface details
therefore will generally be as shown in Figure 1.2.
The final two phases of activity are clearly the province of the OEM, not
involving the vendor unless problems arise with incoming production ICs.
Such testing will be unique to a specific product and its components,
although in its design the requirements of testing, and possibly the
incorporation of design for test (DFT) features such as will be covered later
in this text, must be considered.
 Introduction 3

chip design activity

including simulation
and agreed test -OEM and vendor
specifications

vendor
package prototype
quantity chips

ok
^prototype\ not ok
chip tests

incoming
not ok \ c h i p tests

release to vendor for

production quantities
ok

wafer fabrication

production wafers

wafer probing, vendor

packaging and test of
production quantity
chips

test and approval of

production chips OEM
before product
assembly

Figure 1.2 The IC vendor/OEM test procedures for a custom IC before assembly and
test in final production systems. Ideally, the OEM should do a 100 %
functional test of incoming ICs in a working equipment or equivalent test
rig, although this may be impractical for VLSI circuits
4 VLSI testing: digital and mixed analogue/digital techniques

From this discussion it is evident that the system designers cannot be

divorced from testing considerations. In the case of very small circuits and
systems containing, say, only a few hundred logic gates or a very small number
of analogue circuits, the problem is not too difficult. With such circuits the
OEM can often undertake a 100 % fully-functional test of incoming ICs
and/or completed products, particularly if the production volume is not
excessive, but as complexity increases or production rises then the pressure
to do a restricted number of tests escalates rapidly. For example, it would be
impractical to test a microprocessor-based piece of equipment through all the
conceivable conditions which it may encounter in practice, and some subset
of tests must be defined that will give an acceptable probability that the
product as a whole is fault free.
The development of VLSI has clearly played the biggest part in
highlighting both the need for testing, and the difficulties of doing so with
the limited number of pins which are present on a packaged VLSI circuit If
wafer manufacture and the subsequent chip scribing, bonding and packaging
were perfect, then there would be no need for production IC testing — every
circuit would be fully functional, assuming that the prototype ICs had been
100 % checked and approved. Such absolute perfection cannot be achieved
with complex production processes where a submicron sized defect may
cause functional misbehaviour, and hence some testing of all production ICs
is necessary.
However, unless a fully-exhaustive test of each IC is undertaken, there will
always remain the possibility that a circuit will pass the chosen tests but will
not be completely fault free. The lower the yield of the production process or
the less exhaustive the testing, then the greater will be the probability of not
detecting faulty circuits during test.
This probability may be mathematically analysed. Suppose that the
production yield of fault-free circuits on a wafer is F, where Fhas some value
between Y= 0 (all circuits faulty) and Y= 1 (all circuits fault free). Suppose,
also, that the tests applied to each circuit have a fault coverage (fault
detection efficiency) of FQ where /Ualso has some value between 0 (the tests
do not detect any of the possible faults) and 1 (the tests detect all possible
faults). Then the percentage of circuits that will pass the tests but which will
still contain some fault or faults (the defect level after test, DL) is given by:

This equation is shown in Figure 1.3.

The significance of this very important probability relationship is as
follows. Suppose that the production yield was 50 % (F= 0.5). Then if no
testing was done at all (FC = 0), 50 % of the ICs would clearly be faulty when
they came to be used. If testing is now done and the efficiency of the tests is
only 80 % (FC- 0.8), then the percentage of faulty circuits when used would
now be about 15 % (85 % fault free, 15 % faulty). This is still about one in
 Introduction 5
100 .- • «

V = O.C 1
90
~
80

70 • — ^
V fl 1n \

e
60

50
\ l\ \

^ y = 0.25 X
\
I
40 \

^ ^

A
30 Y - n so
-3
\ \

20
— — - ^
\ \

--—^>
\

Y = 0.90 y = o 75^—• — — ^
10 =—=
r—
- . —

• — • , .
• — - — —
—

0 Y = 0.99
10 20 30 40 50 60 70 80 90 100

fault detection coverage (FC), %

Figure 1.3 The defect level, DL, of a circuit after test with different manufacturing
yieldsY and fault detection coverage, FC. OnlyY = 1.0 or FC = 1.0 will
guarantee 100 % fault-free circuits (no defects) after test

seven ICs faulty, which is far too high for most customers. Hence to ensure a
high percentage of fault-free circuits after test, either the manufacturing yield
For the fault coverage FQ or both, must be high.
This, therefore, is the dilemma of testing complex integrated circuits, or
indeed any complex system. If testing efficiency is low then faulty circuits may
escape through the test procedure. On the other hand, the achievement of
near 100 % fault detection (FC= 1.0) may require such extensive testing as to
be prohibitively costly unless measures are taken at the design stage to
facilitate such a level of test.
Before we continue with the main principles and practice of integrated
circuit testing, let us consider a little further Figure 1.2 and problems which
can specifically arise with OEM use of custom ICs. During the design phase,
simulation of the IC will have been undertaken and approved before
fabrication was commenced. This invariably involves the vendor's CAD
resources for the final post-layout simulation check, and from this simulation
a set of test vectors for the chip may be automatically generated which can be
downloaded into the vendor's sophisticated general-purpose test equipment.
The vendor's tests on prototype custom ICs may therefore be based upon this
simulation data, and if the circuits pass this means that they conform to the
simulation results which will have been approved by the OEM.
6 VLSI testing: digital and mixed analogue/digital techniques

Unfortunately, history shows that very many custom IC designs which pass
such tests are subsequently found to be unsatisfactory under working product
conditions. This is not because the ICs are faulty, but rather that they were
not designed to provide the exact functionality required in the final product.
The given IC specification was somehow incomplete or faulty, perhaps in a
very minor way such as the active logic level of a digital input signal being
incorrectly specified as logic 1 instead of logic 0, or some product
specification change not being transferred to the IC design specification.
Other problems may also arise between parties, such as:
• a vendor's general-purpose computer-controlled VLSI test system, see
Figure 1.4, which although it may have cost several million dollars, may
not have the capability to apply some of the input conditions met in the
final product, for example nonstandard digital or analogue signals or
Schmitt trigger hysteresis requirements;
• similarly, some of the output signals which the custom circuit provides
may not be precisely monitored by the vendor's standard test system;
• the vendor may also only be prepared to apply a limited number of tests
to each production IC, and not anywhere near an exhaustive test;
• the vendor's test system may not test the IC at the operating speed or
range of speeds of the final product.
The main point we need to make is that in the world of custom
microelectronics the OEM and the vendor must co-operate closely and
intelligently to determine acceptable test procedures. When the OEM is using
standard off the shelf ICs then the responsibility for incoming component
and product testing is entirely his. However, in both cases the concepts and

Figure 1.4 A typical general-purpose VLSI tester as used by IC vendors and test
houses (Photo courtesy Avantest Corporation, Japan)
 Introduction 7

the theory and practice of microelectronic circuit testing such as we will be

considering later must be understood.

1.2 The problems of digital testing

Before continuing in the following detailed chapters with the theory and
practice of IC testing, let us broadly consider the problems which are present.
First, it may be appropriate to define three basic terms which arise in
digital circuit testing. These are:
(i) Input test vector (or input vector or test vector): this is a combination of
logic 0 and 1 signals applied in parallel to the accessible (primary)
inputs of the circuit under test. For example, if eight primary inputs are
present then one test vector may be 0 1 1 1 0 0 1 1 . (A test vector is the
same as a word, but the latter term is not commonly used in connection
with testing.)
(ii) Test pattern: a test pattern is an input test vector plus the addition of the
fault-free output response of the circuit under test to the given test
vector. For example, if there are four accessible (primary) outputs, then
with the above test vector the expected outputs might be 0, 0, 0, 1.
(iii) Test set: a test set is a sequence of test patterns, which ideally should
determine whether the circuit under test is fault free or not. As will be
seen later, a test set may be a fully-exhaustive, a reduced or minimum,
or a pseudorandom test set. Continuing from the above example, a test
set may be as shown in Table 1.1.

Table 1.1 An example of a test set for a combinational netxuork with eight inputs and
four outputs
Test vectors Output response
x
i x2 x3 x4 X
5 X
6 X
7 X
8 Y\ Y2 Y3 Yi
First test pattern 0 ) 1 1 0 0 I 1 0 0 0 1
Next test pattern 0 1 ! I 0 1 0 0 0 I 0 0
Next test pattern 1 I 1 i 0 1 0 0 0 1 i 0

Unfortunately, the terms 'vectors', 'patterns' and 'sets' are sometimes

loosely used, and care is therefore necessary when reading literature from
different sources. It should also be noted that these terms apply directly to
purely combinational networks; where sequential networks are involved then
clearly some additional information is needed, for example the number of
clock pulses and the initial state of the circuit at the beginning of the test.
8 VLSI testing: digital and mixed analogue/digital techniques

There is nothing fundamentally difficult in the functional testing of digital

networks; no parametric testing such as may be involved in analogue testing
(see later) is normally required. All that is necessary is to apply some input
test patterns and observe the resulting digital output signals. The problem,
basically, is the volume of data and the resultant time to test.
Take a simple combinational network with n primary inputs and m primary
outputs. Then to test this network exhaustively with every possible input
condition requires 2 n input test vectors, that is the complete truthtable of
the network. If n is, say, 32 and the test vectors are applied at a frequency of
10 MHz, this would take 232 x 10"7 seconds, which is about seven minutes, to
complete this simple exhaustive test. It would also require the m 2n output
signals to be checked for correct response during this test against some
record of the expected (fault free) output signals.
The presence of memory (storage) which is inherent in sequential
networks greatly increases this problem. For a network containing s storage
circuits (latches or flip-flops) there are 2s possible internal states of the
network. For a fully-exhaustive test, every possible input combination to the
primary inputs should be applied for each of these 2s internal states, which
with n primary inputs gives an exhaustive test set of2 n x2 5 = 2 n + * test vectors.
An often-quoted example of this is that of the arithmetic 16-bit
accumulator IC, which can add or subtract a 16-bit input number to/from
any 16-bit number already stored in the accumulator. This relatively simple
circuit has 19 inputs (16 bits plus three control signals) plus the 16 internal
latches. Hence n = 19 and s = 16, giving 219 x 216 = 235 = 34 359 738 368
possible different logic conditions for this circuit. If test vectors were applied
at 10 MHz, it would therefore take 235 x 10"7 seconds, which is about an hour,
to test this MSI circuit exhaustively, and of course the 23r> output signals on
each of the 16 output pins would need to be checked.
Normally all testing of ICs has to be performed through the input and
output terminals of the circuit, either the bonding pads around the
perimeter of each chip during the wafer stage testing by the vendor, or the
pins on the packaged IC during subsequent testing by vendor or OEM.
Hence, IC test procedures are often termed 'pin-limited' because of this
accessibility problem, all the test input signals and their response having to be
applied and detected at these relatively few points in comparison with the
very large numbers of gates and macros within the circuit.* The order of
application of test vectors to the circuit may also be important, which is an
aspect that will be considered later particularly in connection with CMOS
circuits where certain open-circuit faults may cause unexpected circuit action.
In summary, therefore, it is basically the number of tests which it may be
necessary to apply to test a digital circuit, together with the limited number
of accessible input and output pins, which complicates digital testing, rather
* It may be physically possible for the vendor to probe internal points on an IC before
packaging, particularly to look for inexplicable faults, but this is increasingly difficult
as device geometry shrinks in size, and can cause scar damage on the surface making
the chip subsequently imperfect. See Chapter 3, Section 3.7, for additional
information.
 Introduction 9

than any fundamental difficulty in the testing requirements. For circuits with
a small number of logic gates and internal storage circuits, the problem is not
acute; fully-exhaustive functional testing may be possible. As circuits grow to
LSI and VLSI complexity, then techniques to ease this problem such as will
be considered later become increasingly necessary.

1.3 The problems of analogue testing

In contrast to the very large number of logic gates and storage circuits
encountered in digital networks, purely analogue networks are usually
characterised by having relatively few circuit primitives such as operational
amplifiers, etc. The numbers complexity is replaced by the increased
complexity of each building block, and the need to test a range of parameters
such as gain, bandwidth, signal to noise ratio, common-mode rejection
(CMR), offset voltage and other factors. Although faults in digital ICs are
usually catastrophic in that incorrect 0 or 1 bits are involved, in analogue
circuits degraded circuit performance as well as nonfunctional operation has
to be checked.
Prototype analogue ICs are subject to comprehensive testing by the vendor
before production circuits are released. Such tests will involve wafer
fabrication parameters as well as circuit parameters, and the vendor must
ensure that these fabrication parameters remain constant for subsequent
production circuits. The vendor and the OEM, however, still need to test
production ICs, since surface defects or mask misalignments or other
production factors may still cause unacceptable performance, and therefore
some subset of the full prototype test procedures may need to be determined.
Completed analogue systems obviously have to be tested by the OEM after
manufacture, but this is unique to the product and will not be considered
here.
The actual testing of analogue ICs involves standard test instrumentation
such as waveform generators, signal analysers, programmable supply units,
voltmeters, etc., which may be used in the test of any type of analogue system.
Comprehensive general-purpose test systems are frequently made as an
assembly of rack-mounted instruments, under the control of a dedicated
microcontroller or processor. Such an assembly is known as a rack-and-stack
test resource, as illustrated in Figure 1.5. The inputs and outputs of the
individual instruments are connected to a backplane general purpose
instrumentation bus (GPIB), which is a standard for microprocessor or
computer-controlled commercial instruments. (The HP instrumentation bus
HPIB is electrically identical.)
In the case of custom ICs it is essential for the OEM to discuss the test
requirements very closely with the vendor. With very complex analogue
circuits a high degree of specialist ability may be involved, which can only be
acquired through considerable experience in circuit design.
10 VLSI testing: digital and mixed analogue/digital techniques

power supplies -• •
precision
.• • ' digitiser
voltmeter —
digital
' oscilloscope
1.3 GHz signal
analyser
connector • minicomputer
to device
under test
sweep oscillator - o
D D
hard disk
pulse generators-
relay actuators — • •« power supplies
• •

Figure 1.5 A rack-and-stack facility for the testing of analogue circuits, involving a
range of instrumentation with compute?' control of their operation (Photo
courtesy IEEE, ©1987 IEEE)
 Introduction 11

In summary, in analogue test it is circuit complexity rather than volume

complexity which dominates the problem. However, as will be covered in
later pages, the need for rapid acceptance testing of analogue ICs is
often an important factor, and concepts towards this objective will be
considered.

L4 The problems of mixed analogue/digital testing

Testing of the analogue part and testing of the digital part of a combined
analogue/digital circuit or system each require their own distinct forms of
test, as introduced in the two preceding sections.* Hence, it is usually
necessary to have the interface between the two brought out to accessible test
points so that the analogue tests and the digital tests may be performed
separately.
In the case of relatively unsophisticated mixed circuits containing, say, a
simple input A-to-D converter, some internal digital processing, and an
output D-to-A converter, it may be possible to define an acceptable test
procedure without requiring access to the internal interfaces. All such cases
must be individually considered, and so no hard and fast rules can be laid
down.
There are on-going developments which seek to combine both analogue
and digital testing by using multiple discrete voltage levels or serial bit
streams to drive the analogue circuits, or voltage-limited analogue signals for
the digital circuits. However, this work is still largely theoretical; more
successful so far in the commercial market has been the incorporation of
both analogue test instrumentation and digital test instrumentation within
one test assembly, as illustrated in Figure 1.6. Here the separate resources are
linked by an instrumentation bus, with the dedicated host processor or
computer being programmed to undertake the necessary test procedures.
When such resources are used it is essential to consider their capabilities, and
perhaps constraints, during the design phase of a mixed analogue/digital IC,
particularly as appropriate interface points between the two types of circuit
may still be required.

1.5 Design for test

From the previous sections it will be clear that the problems of test escalate as
the complexity of the IC or system increases. If no thought is given to 'how-

* We exclude here in our considerations the testing of individual A-to-D and D-to-A
converters, particularly high speed flash converters. The vendor testing of these and
similar mass-production circuits usually involves extremely expensive test resources
especially designed for this purpose, similar in appearance to the VLSI test equipment
shown in Figure 1.4.
12 VLSI testing: digital and mixed analogue/digital techniques

system software and

host computer

GPIB ^
anal<Dgue diejital
instrum 3ntation ^ synchronisation w 7 instrumentation

i i

integrated signal
distribution and
device f xturing

Figure 1.6 A mixed analogue/digital test resource, with the analogue and the digital
tests synchronised under host computer control. This can be a rack-and-
stack assembly, as in Figure 1.5 for the analogue-only case

shall-we-test-it' at the design stage then a product may result which cannot be
adequately tested within an acceptable time scale or cost of test.
Design for test (DFT) is therefore an essential part of the design phase of
a complex circuit. As we will see later, DFT involves building into the circuit
or system some additional feature or features which would not otherwise be
required. These may be simple features, such as:
• the provision of additional input/output (I/O) pins on an IC or system,
which will give direct access to some internal points in the circuit for
signal injection or signal monitoring;
• provision to break certain internal interconnections during the test
procedure, for example feedback loops;
• provision to partition the complete circuit into smaller parts which may be
individually tested;
or more complicated features such as reconfigurable circuit elements which
have a normal mode of operation and a test mode of operation.
As will be seen later, one of the most powerful test techniques for digital
VLSI circuits is to feed a serial bit stream into a circuit under test to load test
signals into the circuit. The resulting signals from the circuit are then fed out
in an output serial bit stream, and checked for correct response. Such
techniques are scan test techniques; they become essential when, for
example, the IC under test is severely pin-limited, precluding parallel feeding
in of all the desired test signals in a set of wide test vectors. One penalty for
having to adopt scan test methods is an increase in circuit complexity, and
hence chip size and cost. We will be considering all these factors in detail in
later chapters of this text.
 Introduction 13

1.6 Printed-circuit board (PCB) testing

All OEM systems employ some form of printed-circuit board (PCB) for the
assembly of ICs and other components. PCB complexity ranges from very
simple one- or two-sided boards to extremely complex multilayer boards
containing ten or more layers of interconnect which may be necessary for
avionics or similar areas.
PCB testing falls into three categories, namely:
(i) bare-board testing, which seeks to check the continuity of all tracks on
the board before any component assembly is begun;
(ii) in-circuit testing, which seeks to check the individual components,
including ICs, which are assembled on the PCB;
(iii) functional testing, which is a check on the correct functionality of the
completed PCB.

Bare-board testing
Simple one- or two-sided bare boards may be checked by visual inspection.
However, as layout size and complexity increases, then expensive PCB
continuity testers become necessary. Connections to the board under test are
made by a comprehensive 'bed-of-nails' fixture, which is unique for every
PCB layout, test signals being applied and monitored by a programmed
sequence from the tester's dedicated processor or computer. One hundred
per cent correct continuity is required from such tests.

In-circuit testing
In-circuit testing, the aim of which is to find gross circuit faults before
commencing any fully-detailed functional testing, may or may not be done. If
it is, then electrical connections to the individual components are again
made via a bed-of-nails fixture, the processor of the in-circuit tester being
programmed to supply and monitor all the required test signals.
The fundamental problem with in-circuit passive component measurement
is that the component being measured is not isolated from preceding and/or
following components on the board. For discrete components a
measurement technique as shown in Figure 1.7 is necessary. Here Zx and Z2
are the impedance paths either side of the component Zx being measured. By
connecting both of these paths to ground, virtually all the current flowing
into the in-circuit measuring operational amplifier comes from the test
source vs via the component Z r Current flowing through Z2 is negligible
because of the virtual earth condition on the inverting input of the
operational amplifier. Hence:

V
OUT = ~jT~ X
Rfi
14 VLSI testing: digital and mixed analogue/digital techniques

whence
v R
_ s jb

The PCB is not powered up for these component value tests.

To test active devices on the PCB, the board is powered up with its normal
supply or supplies. For operational amplifiers and other analogue devices,
test signals are applied to inputs, and output voltages measured. However, to
test the operation of onboard digital devices, it is necessary to impose 0 or 1
logic signals on gate inputs which may otherwise have the opposite logic value
on them. This is done by applying low source impedance logic 0 or logic 1
pulses, which are long enough to force the required value on inputs and
measure the resulting logic outputs, but not long enough to cause damage to
any preceding logic gates by what is effectively a short circuit of their output
to supply or ground potential.
In-circuit PCB testing matured in the days of analogue and simple digital
circuits, particularly SSI and MSI TTL circuits which could withstand test
pulses of about 10 jits duration to drive gate inputs to opposite logic levels.
However, it becomes impractical for PCBs with a high population of digital
ICs, particularly LSI and VLSI packages, and with present-day small geometry,
low-power gates and macros. Functional PCB testing therefore is currently
prevalent, following initial bare-board inspection and/or test.

Functional testing
In contrast to the bed of nails fixtures noted above, PCB functional testing
must access the circuit through its normal edge connector(s) or other I/O

V
SOURCE
(low impedance)
OUT

Figure 1.7 The technique used for the in-circuit testing of passive component values.
In practice additional complexity may be present to overcome errors due to
source impedance, lead impedance, offset voltages, etc.
 Introduction 15

terminals. Probing of internal tracks on the PCB may be done for specific
fault-finding purposes, but not during any automated test procedure.
With fully-assembled PCBs we are effectively doing a systems test. This will
be unique for every OEM product, and may involve an even greater
complexity of test than individual VLSI circuits. We will not pursue functional
PCB testing any further in this text, except to note that all the theory and
techniques which will be discussed in the following chapters apply equally to
complex PCB assemblies; design for test (DFT) techniques must be con-
sidered at the design stage, and PCB layouts must incorporate the necessary
provisions for the final functional tests. Scan testing (see Chapter 5) in
particular may need to be incorporated to give test access from PCB I/Os to
internal IC packages.

1.7 Software testing

Software is an essential element in perhaps the majority of present-day

systems, and can account for a greater design time and cost than the
hardware costs. Examples of software problems in complex systems such as
airport baggage handling, combined police, fire and ambulance control
systems and other similar distributed systems are increasingly known, and
have demonstrated that software design and test is critical to final system
performance.
The principal subject of this text, namely IC testing, has a long history
based upon research into electrical and electronic reliability and failure
mechanisms; software reliability, testing and failure, however, is a more recent
subject area. Indeed, until recently any system fault in service was assumed to
be a hardware failure, the software program (s) being considered fault free.
However, with increasing system complexity, larger distributed systems and
parallel processing, this is no longer the case.
The objectives of software testing are to ensure correct system operation
under:
• extreme conditions of input parameter values, timing and memory
utilisation;
• ranges of input sequences;
• fault conditions on input data;
• other abnormal as well as normal operating conditions.
The greatest problems are software sneak conditions, namely:
• sneak outputs, where the wrong output code is generated;
• sneak inhibits, where an input or output code is incorrectly inhibited;
• sneak timings, where an incorrect output code is generated due to some
timing irregularity;
• sneak messages, where a program message incorrectly reports a system
status.
16 VLSI testing: digital and mixed analogue/digital techniques

As with VLSI hardware testing, system complexity may make it impossible to

undertake a 100 % fully-functional test of the system under all possible system
conditions.*
Computer science is tackling this problem, and developing reliability
prediction and measurement modelling for software programs. It remains,
however, a complex and specialist area, but one about which designers of very
large software-based systems must be aware.

1.8 Chapter summary

This first chapter has been a broad overview of the problems of testing
circuits of VLSI complexity and systems into which they may be assembled.
As will be appreciated, the testing problem is not usually one of fundamental
technical difficulty, but much more one of the time and/or the cost neces-
sary to undertake a procedure which would guarantee 100 % correct
functionality.
The subsequent chapters of this text will therefore consider the types of
failures which may be encountered in microelectronic circuits, fault models
for digital circuits, the problems of observability and controllability and the
various techniques that are available to ease the testing of both digital and
mixed analogue/digital circuits. Finally, the financial aspects of testing which
reflect back upon the initial design of the circuit or system will be considered,
as well as the production quantities that may be involved.
We will conclude this chapter with a list of publications which may be
relevant for further general or specific reading. The more specialised ones
may be referenced again in the following chapters.

1.9 Further reading

1 ABRAMOVICI, M., BREUER, M.A., and FRIEDMAN, A.D.: 'Digital systems testing
and testable design' (Computer Science Press, 1990)
2 LALA, P.K.: 'Fault tolerant and fault testable hardware design' (Prentice Hall,
1985)
3 WILKINS, B.R.: 'Testing digital circuits: an introduction' (Van Nostrand
Reinhold, 1986)
4 FUJIWARA, H.: 'Logic testing and design for testability' (MIT Press, 1985)
5 MICZO, A.: 'Digital logic testing and simulation' (Harper and Row, 1986)
6 PYNN, C: 'Strategies for electronic test' (McGraw-Hill, 1986)
7 STEVENS, A.K/. 'Introduction to component testing' (Addison-Wesley, 1986)
8 PARKER, K.P.: 'Integrating design and test: using CAE tools for ATE pro-
gramming' (IEEE Computer Society Press, 1987)
9 YARMOLIK, V.N.: 'Fault diagnosis of digital circuits' (Wiley, 1990)

* The extreme case of this is possibly the Star Wars research and development
programme, which would have been impossible to test under operational conditions.
 Introduction 17

10 BARDELL, P.H., McCANNEY, W.H., and SAVIR, J.: 'Built-in test for VLSI:
pseudorandom techniques' (Wiley, 1987)
11 BENNETTS, R.G.: 'Design of testable logic circuits' (Addison-Wesley, 1984)
12 BATESON, J.: 'In-circuit testing' (Van Nostrand Reinholt, 1985)
13 GULATI, R.K., and HAWKINS, C.F.: lIDDQ testing of VLSI circuits' (Kluwer, 1993)
14 BLEEKER, H., Van den EIJNDEN, P., and De JONG, R: 'Boundary scan test: a
practical approach' (Kluwer, 1993)
15 RAJSUMAN, R.: 'Digital hardware testing: transistor-level fault-modeling and
testing' (Artech House, 1992)
16 MILLER, D.M. (Ed.): 'Developments in integrated circuit testing' (Academic
Press, 1987)
17 WILLIAMS, T.W. (Ed.): 'VLSI testing' (North-Holland, 1986)
18 RUSSELL, G., and SAYERS, I.L.: 'Advanced simulation and test methodologies for
VLSI design' (Van Nostrand Reinhold, 1989)
19 RUSSELL, G. (Ed.): 'Computer aided tools for VLSI system design' (Peter
Peregrinus, 1987)
20 MASSARA, R.E. (Ed.): 'Design and test techniques for VLSI and WSI circuits'
(Peter Peregrinus, 1989)
21 SOIN, R., MALOBERT, R, and FRANCA, J. (Eds.): 'Analogue digital ASICs: circuit
techniques, design tools and applications' (IEE Peter Peregrinus, 1991)
22 TRONTELJ, J., TRONTELJ, L., and SHENTON, G.: 'Analogue digital ASIC
design' (McGraw-Hill, 1989)
23 ROBERTS, G.W., and LU, A.K.: 'Analogue signal generation for the built-in-self-
test of mixed signal ICs' (Kluwer, 1995)
24 NAISH, P., and BISHOP, P.: 'Designing ASICs' (Wiley, 1988)
25 'Design for testability'. Open University microelectronics for industry publication
PT505DFT, 1988
26 HURST, S.L.: 'Custom VLSI microelectronics' (Prentice Hall, 1992)
27 NEEDHAM, W.M.: 'Designer's guide to testable ASIC devices' (Van Nostrand
Reinhold, 1991)
28 DI GIACOMOJ.: 'Designing with high performance ASICs' (Prentice Hall, 1992)
29 WHITE, D.E.: 'Logic design for array-based circuits: a structure design
methodology' (Academic Press, 1992)
30 BENNETTS, R.G.: 'Introduction to digital board testing' (Edward Arnold, 1982)
31 MAUNDER, C: 'The board designer's guide to testable logic circuits' (Addison-
Wesley, 1992)
32 O'CONNOR, P.D.T.: 'Practical reliability engineering' (Wiley, 1991)
33 CHRISTOU, A.: 'Integrating reliability into microelectronics manufacture'
(Wiley, 1994)
34 MYERS, G.J.: 'Software reliability: principles and practice' (Wiley, 1976)
35 MYERS, G.J.: 'The art of software testing' (Wiley, 1979)
36 SMITH, D.J., and W7OOD, K.B.: 'Engineering quality software' (Elsevier, 1989)
37 MITCHELL, R.J. (Ed.), 'Managing complexity in software engineering'
(Institution of Electrical Engineers, 1990)
38 SOMMERVILLE, I.: 'Software engineering' (Addison-Wresley, 1992)
39 SIMPSON, W.R., and SHEPPARD, J.W.: 'System test and diagnosis' (Kluwer, 1994)
40 ARSENAULT, J.E., and ROBERTS, J.A. (Eds.): 'Reliability and maintainability of
electronic systems' (Computer Science Press, 1980)
41 KLINGER, D.J., NAKADA, Y, and MENENDIZ, M.A. (Eds.): 'AT+T reliability
manual' (Van Nostrand Reinhold, 1990)
 Chapter 2
Faults in digital circuits

2.1 General introduction

In considering the techniques that may be used for digital circuit testing, two
distinct philosophies may be found, namely:
(a) to undertake a series of functional tests and check for the correct (fault-
free) 0 or 1 output response(s);
(b) to consider the possible faults that may occur within the circuit, and
then to apply a series of tests which are specifically formulated to check
whether each of these faults is present or not.
The first of the above techniques is conventionally known as functional
testing. It does not consider how the circuit is designed, but only that it gives
the correct outputs during test. This is the only type of test which an OEM can
do on a packaged IC when no details of the circuit design and silicon layout
are known.
The second of the above techniques relies upon fault modelling. The
procedure now is to consider faults which are likely to occur on the wafer
during the manufacture of the ICs, and compute the result on the circuit
output(s) with and without each fault present. Each of the final series of tests
is then designed to show that a particular fault is or is not present. If none of
the chosen set of faults is detected then the IC is considered to be fault free.
Fault modelling relies upon a choice of the types of fault(s) to consider in
the digital circuit. It is clearly impossible to consider every conceivable
imperfection which may be present, and therefore only one or two types of
fault are normally considered. These are commonly stuck-at faults, where a
particular node in the circuit is always at logic 0 or at logic 1, and bridging
faults, where adjacent nodes or tracks are considered to be shorted together.
We will consider these faults in detail in the following sections.
The potential advantage of using fault modelling for test purposes over
functional testing is that a smaller set of tests is necessary to test the circuit.
20 VLSI testing: digital and mixed analogue/digital techniques

This is aided by the fact that a test for one potential fault will often also test
for other faults, and hence the determination of a minimum test set to cover
all the faults being modelled is a powerful objective. However, in theory a
digital circuit which passes all its fault modelling tests may still not be fully
functional if some other, possibly obscure, fault is present, but the probability
of this is usually considered to be acceptably small.

2.2 Controllability and observability

Two terms need to be considered before discussing further aspects of digital
circuit testing. These are controllability and observability. These terms were
first introduced in the 1970s in an attempt to quantify the ease (or difficulty)
of testing a digital circuit, with the aim of bringing to the attention of the
circuit designer during the design phase potentially difficult to test circuit
arrangements so that circuit modifications could be considered.
The basic concept of controllability is simple: it is a measure of how easily
a node in a digital circuit can be set to logic 0 or to logic 1 by signals applied
to the accessible (primary) inputs. Similarly, the concept of observability is
simple: it is a measure of how easily the state of a given node (logic 0 or logic
1) can be determined from the logic signals available at the accessible
(primary) outputs.
Consider the small circuit in Figure 2.1. Nodes 1, 2, and 3 are immediately
controllable, since they are connected directly to primary inputs. Node 7, on
the other hand, is clearly not so readily controllable; it requires either node
6 to be held at logic 0 and node 5 switched from 0 to 1 (toggled), or vice
versa, which in turn must be traced back to the primary inputs. One test set
for node 7 would be to set inputs Fand G to logic 1 and toggle input E, giving
the two test vectors:

input test vector

m m m E F G m m m node 7
• • • 0 1 1 • • • 1
• • • ! ! ! • • • 0

Clearly, the further a node is from the primary inputs the more indirect it is
to control the logic value of that node.
Some nodes in a working circuit may not be controllable from the primary
inputs. Consider the monitoring circuit shown in Figure 2.2a. With a healthy
circuit the outputs from the two subcircuits will always be identical, and no
means exists of influencing the output of the monitoring circuit. An addition
such as shown in Figure 2.2b is necessary in order to provide controllability of
the monitoring circuit response.
 Faults in digital circuits 21

E o
F o
primary
inputs

Figure 2.1 A simple circuit to illustrate controllability

monitoring circuit to check

equality between circuits
A and B (equality checker)

equality
- • check
output

I node not
I controllable
i from inputs
i
i

equality
•• check
output

node now
controllable
from input

Figure 2.2 An example of a circuit node that is not controllable from a primary input
a basic system with duplicated circuits A and B
b an addition necessary to give controllability
22 VLSI testing: digital and mixed analogue/digital techniques
Monitoring circuits and also circuits containing redundancy both present
inherent difficulties in controllability; additional primary inputs just for test
purposes become necessary. Another possible difficulty may arise in the case
where the IC contains a ROM structure, the outputs of which drive further
logic circuits. Here the ROM programming may preclude the application of
certain desirable test signals to the further logic, limiting the possible
controllability of the latter.
The controllability of circuits containing latches and flip-flops (sequential
circuits) is also often difficult or impossible, since a very large number of test
vectors may have to be applied to change the value of a node in or controlled
by the sequential circuits. Additionally there will often be certain states of the
circuit which are never used, for example in a four-bit BCD counter which
only cycles through ten of the possible 16 states. It is, therefore, frequently
necessary to partition or reconfigure counter assemblies into a series of
smaller blocks, each of which can be individually addressed under test
conditions. (This is one of the design for test philosophies that we will
consider in greater detail in a later chapter.)
Turning to observability, consider the simple circuit shown in Figure 2.3.
Suppose it is necessary to observe (monitor) the logic value on node 2. In
order that this logic value propagates to the primary output Z, to give a
different logic value at Z depending upon whether the node is at logic 0 or
logic 1, it is clear that nodes 1 and 4 must be set to logic 1 and node 6 to logic
0. Hence, the primary signals must be chosen so that these conditions are
present on nodes 1, 4 and 6, in which case output Zwill be solely dependent
upon node 2. Node 2 will then be observable. This procedure is sometimes
termed sensitising, forward driving or forward propagating the path from a
node to an observable output.
The general characteristics of controllability and observability for any
given network are therefore as shown in Figure 2.4. Provided that there is no
redundancy in the network, that is all paths must at sometime switch in order
to produce a fault-free output, then it is always possible to determine two (or

•— ' H invertion of node 2

1

2
—^~\jL,

w. -7
^/
fi L observable
output

Figure 23 A simple circuit to illustrate observability

 Faults in digital circuits 23

more) input test vectors which will check that each internal node of the
circuit correctly switches from 0 to 1 or from 1 to 0, or fails to do so if there
is a fault at the node. However, the complexity of determining the smallest set
of such vectors to test all internal nodes is high, way beyond the bounds of
computation by hand except in the case of extremely simple circuits. If
sequential circuits are also present, then there is the additional complexity of
ensuring that the sequential circuits are in their required states as well.
Many attempts have been made to quantify the controllability and
observability of a given circuit, to allow difficult to test circuits to be identified
and hopefully modified during the design phase1"10. The software packages
which were developed include TMEAS, 19791 TEST/80, 19793, SCOAP,
19804, CAMELOT, 19816, VICTOR, 19827, and COMET, 19828. These are
discussed in Bennetts11, Bardell et al12 and Abramovici et #Z.1S. The basic
concepts used in the majority of these developments involve (i) the com-
putation of a number intended to represent the degree of difficulty in setting
each internal node of the circuit under test to 0 and 1 (O-controllability and
1-controllability) and (ii) the computation of another number intended to
represent the difficulty of forward propagating the logic value on each node
to an observable output. The difficulty of testing the circuit is then related to
some overall consideration of these individual numerical values. Further
developments in the use of this data so as to ease the testing difficulty were
also pursued14.
In the majority of these developments, controllability was normalised to the
range 0 to 1, with 0 representing a node which was completely uncontrollable
from a primary input, to 1 representing a node with direct controllability.
Typically, a controllability transfer factor, CTF, for every type of combinational
logic gate or macro is derived from the expression:

CTF = 1 - (2.1)

CO n
CO
<5

input pins output pins

increasing distance from inputs increasing distance from outputs

Figure 2.4 The general characteristic of both controllability and observability
24 VLSI testing: digital and mixed analogue/digital techniques

where N(0) and N(l) are the number of input patterns for which the
component output is logic 0 and logic 1, respectively, in other words N(0) is
the number of Os in the truth table or Karnaugh map for the component, and
iV(l) is the number of Is. Components such as an inverter gate or an
exclusive-OR gate have a value of CTF= 1, since they have an equal number
of Os and Is in their truthtable; n-input AND, NAND, OR and NOR gates,
however, have a controllability transfer factor value of l/2 n ~ 1 , as may readily
be shown by evaluating the above equation.
The controllability factor, CY, of a component output with inputs which are
not directly accessible from primary inputs is then computed by the equation:
Wouiput= (CTFx CYmpuls) (2.2)
where CTF is the controllability transfer factor for the component and
CYinputs is the average of the CTFs on the component input lines. (For
components with inputs which are directly accessible CYinputs= 1, and hence
CY0Utput = CTF for this special case.) Hence, working through the circuit the
controllability value of every node from primary input to primary output can
be given a numerical value.
In a similar manner to determining the controllability transfer factor value
for each type of gate or macro, in considering observability an observability
transfer factor, OTF, is determined for each component. This factor is the
relative difficulty of determining from a component output value whether
there is a faulty input value (error) on an input to the component. An
inverter gate clearly has an observability transfer factor value of 1; for rc-input
AND, NAND, OR and NOR gates the value is l/2 n " 1 , the same as the CTF
value. The exact equation for OFT may be found in the literature11"13, and
does not necessarily have the same value as CTFTor all logic macros.
The observability factor, OF, for each node in a circuit is next determined
by working backwards from primary outputs through components towards
the primary inputs, generating the observability value OFfor every node. The
value of OYis given by an equation similar to eqn. 2.2, namely:
OYmputs= (OTF x OYoutputs) (2.3)
where OTF is the observability transfer factor for each component, and
OY outputsx% t n e average of the observability values for the individual output
nodes of the component or macro.
This computation of controllability and observability values, however, is
greatly complicated by circuit factors such as reconvergent fan-out, feedback
paths and the presence of sequential circuits. Combining the two values so as
to give a single measure of testability, 7T, is also problematic. The simple
relationship:

TVnode= (CY^x OYnode) (2.4)

may be used, with an overall circuit testability measure given by:
 Faults in digital circuits 25

TV"
1 (M nodes \ node >
*overall " " ~ (2.5)
number of nodes
but this in turn is not completely satisfactory since it does not, for example,
show any node(s) which are not controllable or observable, i.e. nodes which
have a value TYnode = 0. Although these and other numerical values for
controllability and observability generally follow the relationships shown in
Figure 2.4, experience has shown that quantification has relatively little use.
In particular:
• the analysis does not always give an accurate measure of the ease or
otherwise of testing;
• it is applied after the circuit has been designed, and does not give any
help at the initial design stage or direct guidance on how to improve
testability;
• it does not give any help in formulating a minimum set of test vectors for
the circuit.
Hence, although controllability and observability are central to digital
testing, programs which merely compute testability values have little present-
day interest, particularly with VLSI circuits where their computational
complexity may become greater than that necessary to determine a set of
acceptable test vectors for the circuit, see later. SCOAP4, CAMELOT6 and
VICTOR7 possibly represent the most successful programs which were
developed. For further comments see Savir15, Russell16, and Agrawal and
Mercer17.
We will have no need to refer again to testability quantification in this text,
but the concept of forward propagating test signals from primary inputs
towards the primary outputs and backward tracing towards the inputs will
arise in our further discussions.

2.3 Fault models

The consideration of possible faults in a digital circuit is undertaken in

order to establish a minimum set of test vectors which collectively will test
that the faults are or are not present. If none of the predefined faults are
detected, then the circuit is considered to be fault free. This procedure is
sometimes termed structurally-based test pattern generation; when the test
vectors are automatically generated from the circuit layout (or from any
other data) the term automatic test pattern generation (ATPG) is commonly
used.
The faults in digital circuits which are usually considered are:
(i) stuck-at faults;
(ii) bridging faults;
26 VLSI testing: digital and mixed analogue/digital techniques

(iii) stuck-open faults;

(iv) pattern sensitive faults.
The first two of these categories apply to any fabrication technology, and will
be considered in the following two sections. The third category is normally
considered in the context of CMOS technology, where it results in a
potentially unique fault condition as will be considered in section 2.3.3. The
fourth category is normally considered in connection with specific devices
with a regular silicon layout, such as ROMs and RAMs, and consideration of
this will therefore be deferred until Chapter 6.

2.3.1 Stuck-at faults

The most common model that as been used for faults in digital circuits is the
single stuck-at fault model. This assumes that any physical defect in a digital
circuit results in a node in the circuit (a gate input or output) being fixed at
logic 0, stuck-at 0, or fixed at logic 1, stuck-at 1. This fault may be in the logic
gate or macro itself, or some open circuit or short circuit in the inter-
connections such that the node can no longer switch between 0 and 1. The
abbreviations s-a-0 and s-a-l are usually used for these two stuck-at conditions,
and will be adopted from here on.
Consideration of the possible faults in a digital circuit will show that the
stuck-at model is very powerful. Even if a particular node is stuck outside its
normal 0 or 1 voltage tolerance, subsequent logic gates will generally inter-
pret this value as either logic 0 or 1. It has also been proved by Kohavi and
Kohavi18 that if a test set which detects all possible single stuck-at faults in any
two-level combinational circuit is determined, then this exhaustive test set will
also detect all possible multiple stuck-at faults. In other words, it is not
possible for two or more stuck-at faults in a two-level circuit to mask each
other and give a fault-free output for all the input test vectors. However, for
circuits with more than two levels of combinational logic this is no longer
necessarily true, although in practice it is found that the single stuck-at test
vectors do always test for a high percentage of possible multiple stuck-at
faults, the precise coverage being circuit and layout dependent.*
For a three-input NAND gate there are eight possible single stuck-at faults,
as shown in Table 2.1. However, it will be seen that four of these are
indistinguishable at the gate output, each giving a s-a-l condition on the
output node. A total of four test input vectors as shown in Table 2.2 will detect
(but not identify) the presence of all eight possible stuck-at faults. Similar
developments can be shown for all other combinational gates and macros,
each requiring less than 2 n input test vectors to test for all possible stuck-at
faults on a n-input component.

* For a function with TVnodes a total of 2iV*single stuck-at faults have to be considered,
but the theoretical number of possible multiple stuck-at faults is 3^-2^1. This is
clearly a very large number to consider.
 Faults in digital circuits 27

Table 2.1 All possible stuck-at faults on a three-input NAND gate; the wrong outputs
have been circled
Inputs Output Z
ABC Fault-free A A 8 8 C C Z Z
s-a-0 s-a-l s-a-0 s-a-l s-a-0 s-a-l s-a-0 s-a-l

0 0 0 I I I I I I I © I
0 0 1 I I I I I I I © I
0 1 0 I I I I I I I © I
0 1 1 I I © I I I I © I
1 0 0 I I I I I I I © I
1 0 1 I I I I ® I I © I
110 I I I I I I © © I
I I I 0 © O Q O C D O O ®

Table 2.2 The minimum test set for detecting all possible stuck-at faults in a three-input
NAND gate
Input Healthy Wrong Faults detected
test vector output output by test vector
ABC

0 1 1 1 0 A s-a-1 or Z s-a-0
1 0 1 1 0 8 s-a-1 or Z s-a-0
1 1 0 1 0 C s-a-1 or Z s-a-0
1 1 1 0 1 A or 8 or C s-a-0 or Z s-a-1

3 i/p NOR gate

Automatic test pattern generation (ATPG) programs for determining a

minimum set of test vectors based upon this single stuck-at model have been
extensively developed. These programs, see Section 3.2 later, generate
appropriate input vectors which:
(a) attempt to drive the node under consideration to logic 1 when a s-a-0
check is being made;
(b) attempt to drive the node to logic 0 when a s-a-l check is being made;
(c) propagate the signal on this node to a primary output so that its logic
state can be checked.
For example, in the circuit shown in Figure 2.5, when it is required to check
that the output of the inverter gate Gl is not stuck-at 0, the input test vector
shown must be applied. This vector will attempt to set this output node to
logic 1, and whatever logic signal is at the node will be propagated to the
primary output, giving 0 in the presence of the stuck-at fault and 1 if the node
is not stuck-at 0. Note that this fault is indistinguishable from the Inverter
input node stuck-at 1, or the lower input of the NAND gate G4 stuck-at 0, or
 o/p=0 if sa-0
o/p=1 if NO sa-0
28 VLSI testing: digital and mixed analogue/digital techniques
for the same TV
single stuck-at 0 fault

observable output
(0 in the presence of
the stuck-at 0 fault)
don't
care

Figure 2.5 A simple example showing the test vector required to test for and propagate
the output of gate Gl stuck-at 0 to the primary output, the three lower
inputs being all don yt cares

its output stuck-at 1. Hence, in total there is a great deal of commonality in

the set of test vectors for checking the individual nodes s-a-0 or s-a-l, from
which a minimum test set can be compiled by the ATPG program.
A more complex example is shown in Figure 2.6. Here 15 input test vectors
are sufficient to check for all possible s-a-0 and s-a-l faults in the circuit. The
amount of work involved in deriving a minimum test set clearly increases
sharply when there are more than two levels of logic (excluding input
inverters) in the circuit, and when there is a high fan-out from the logic gates.
A further problem that we have not considered is where there is feedback
in the circuit and where sequential circuits (latches and/or flip-flops) are
present. This greatly complicates the problem, although it is always possible
to find a test for a node s-a-0 or s-a-l provided that the node at some time
controls the value of a primary output.
If it is not possible to find any test for a node s-a-0, then we can apply a
steady logic 0 at this node without affecting the output function; similarly if
no test for s-a-l can be found then we can apply a steady logic 1 at the node
without affecting the output function. In both cases there must be some
redundancy in the existing circuit at this point; Figure 2.7 is an illustration of
this. It should, therefore, be appreciated that if redundancy is deliberately
introduced into a circuit this will inevitably complicate the subsequent circuit
testing; for example, if in an asynchronous logic design an additional prime
implicant term is introduced specifically to eliminate a potential race hazard
in the circuit, then either no s-a-0 or no s-a-l tests will be possible for this
additional logic gate.
In summary, the use of stuck-at fault modelling is a powerful tool, but is not
necessarily the best approach for the testing of present-day very complex
VLSI circuits. For further details, see existing literature13'16'18"25.
 Faults in digital circuits 29

Inputs Faults covered

10x0*0xxxCM* 1/0 2/1 20/0 24/1 29/0

00x0*0xxx01x 1/1 24/0 29/1
11 x O x O x x xO1 x 2/0 17/0 20/1 24/0 29/1
Ox 1 1 x O x O x x 11 3/0 4/0 13/1 18/1 19/0 21/1 23/1 2G/0 27/1 28/0 29/1
0101 x 0 x O i l 11 3/1 13/0 18/0 19/1 21/0 23/0 26/1 27/0 23/1 29/0
01 xOO1 x 01 1 1 1 5/1 14/0 19/1 21/0 23/0 26/1 27/0 28/1 29/0
Ox x x 11 111 1 11 7/0 8/0 15/1 21/0 23/0 26/1 27/0 28/1 29/0
Ox x x 1 101 x x 1 1 7/1 15/0 21/1 23/1 26/0 27/1 28/0 29/1
01x0x0 xxOilx 9/1 16/0 25/1 28/0 29/1
01 x O x Q x x 101 x 10/1 16/0 22/0 25/1 28/0 29/1
O l x O x O x x 1101 11/1 26/0 27/1 28/0 29/1
l i l l x x x O x x x i 17/1 20/0 24/1 2P/0
Ox x x i i x O x O x O 12/1 22/1 25/0 27/0 28/1 29/0
011010x01111 4/1 6/1 9/0 10/0 1 1/0 13/0 14/0 16/1 18/0 19/1 21/0 23/0 25/0 26/1 27/0 28/1 29/0
01 x O l l l O x x 1 1 5/0 6/0 8/1 12/0 M / 1 15/0 19/0 21/1 23/1 26/0 27/1 28/0 29/1

Figure 2.6 A further example giving a minimum test set of 15 test vectors which test
all the circuit nodes for possible s-a-0 and s-a-l faults. The Xs in the input
vectors are don't cares; 1/0, 2/1, etc. in the faults-covered listing means
node 1 s-a-0 tested, node 2 s-a-l tested, and so on {Acknowledgement,
Oxford University, UK)

A o
B o-

C o

D
E
F

Figure 2.7 An example of overlooked redundancy in a combinational network. It is

left as an exercise for the reader to try to establish stuck-at tests for the
nodes around gate G2, and the reason for any failure to establish such
tests
30 VLSI testing: digital and mixed analogue/digital techniques

23.2 Bridging faults

Unlike stuck-at faults, where a node is considered to be stuck-at one or other
logic value, bridging faults may result in a node being driven to 0 or 1 by the
action at some other node(s). Since this depends upon the driving
impedance of the logic signals on the lines which are bridged, no precise
decisions can be made on what the effect of bridging faults will be without
some consideration of (i) the technology, (ii) where the faults are in the
circuit layout and (iii) how extensive is the bridging. In TTL, for example, a
logic 0 signal on two nodes which are shorted will normally dominate; in
ECL a logic 1 signal will dominate, although in CMOS an intermediate logic
value can result. Also, when shorted nodes individually have the same logic
value (0 or 1) then the circuit output(s) will be correct and no fault can be
observed; it is only when they differ that some logic conflict has to be
resolved.
The number of bridging faults which are theoretically possible between any
two lines in a circuit of n lines is:
n(n-l)

This assumes that a short may occur between any two lines, but in practice
shorts between physically adjacent lines are clearly more realistic. However,
if bridging between more than two lines is considered, then the number
of theoretically possible bridging faults escalates rapidly13. In general, the
number of feasible bridging faults between two or more lines is usually
greater than the theoretical number of possible stuck-at faults in a
circuit, and although it is straightforward to derive a single test vector that
will cover several stuck-at faults in the circuit, this is not so for bridging
faults.
A further difficulty with bridging faults is that a fault may result in a
feedback path being established, which will then cause some sequential
circuit action. Hence, bridging faults have been classified as sequential
bridging faults or combinational bridging faults, depending upon the nature
of the fault. A sequential bridging fault may also result in circuit oscillation if
the feedback loop involves an odd number of inversions in an otherwise
purely combinational network.
Extensive consideration has been given to bridging faults, including the
consideration that bridged lines are logically equivalent to either wired-OR or
wired-AND functions25"33, but no general fault model is possible which caters
for the physical complexity of present-day VLSI circuits. It has been suggested
that most (but not all) shorts in combinational logic networks are detected by
a test set based upon the stuck-at model, provided that the latter is designed
to cover 99 % or more of the possible stuck-at circuit faults12. This statement,
however, is increasingly debatable as chip size increases and where CMOS
technology is involved, see the following discussions.
 Faults in digital circuits 31

233 CMOS technology considerations

CMOS technology is the most pervasive of present-day microelectronic
technologies, and it is therefore very relevant to consider specifically the
faults which may be present in CMOS gates and interconnections.
The stuck-at fault model will clearly be appropriate should, say, a gate input
be bridged to Vcc (logic 1) or ground (logic 0). However, it has been
estimated that over one-third of the faults which occur in CMOS circuits are
not covered by this classical stuck-at fault model34, and, therefore, a
consideration of other possible failure modes is essential.
The circuits of typical CMOS NAND and NOR logic gates are shown in
Figure 2.8. The circuit arrangement of the p-channel field-effect transistors
(FETs) is always the dual of the circuit arrangement of the n-channel FETs,
that is a parallel connection of p-channel FETs is mirrored by a series
connection of n-channel FETs, and vice versa.* When the circuit is healthy,
there is always a conducting path from either V^/)Or from ground to the gate
output, but no conducting path from VDD to ground except partially during
output transitions. Under steady-state conditions, the current taken from the
supply is virtually zero, since gate input resistance is extremely high (tens or
hundreds of megohms), and the inherent circuit capacitances at gate output
connections are either charged to VDD via the conducting p-channel FETs or
discharged to 0 V via the conducting n-channel FETs.
However, consider a fault in the p-channel transistor Tl in Figure 2.8a
such that it becomes open circuit. With inputs AB = 0 0 , 1 0 and 1 1 the gate
output will be unaffected since there is always a healthy conducting path from
either VDD or 0 V to the gate output. With input 0 1, however, there will be
no conducting path through Tl, and hence no path to the output from
either supply rail. The gate output will therefore be floating.
If under test conditions the input test vectors are applied in the order 0 0,
0 1,10 and 1 1, the first vector 0 0 will establish logic 1 at the gate output
through the working transistor T2. When the input changes to 0 1 there will
be no immediate change in the gate output, since the circuit capacitance will
maintain the output voltage at the logic 1 level. Should the input 0 1 be held
for a long time (possibly minutes), then eventually the output voltage will
decay sufficiently so that it is no longer an effective logic 1 signal to the
following gates, but if (as is invariably the case) the input vector is quickly
changed to 1 0 then no fault will have been detected. The output has
remembered the correct logic value, and the fault is said to be a memory
fault.
However, if the input test vector 0 1 had been preceded by the test vector
1 1, then the gate output would not have been precharged to logic 1, and
on input 0 1 would remain at logic 0. Therefore, to detect this particular

* Because the resistance of p-type FETs is higher than that of similar dimension n-type
FETs, it is preferable to series the n-channel FETs and parallel the p-channel FETs.
Hence, NAND gates rather than NOR gates become the preferred basic logic element.
32 VLSI testing: digital and mixed analogue/digital techniques

AB

/777

/Z?7

Inputs State of the transistors Output

state
B T1 T2 T3 T4
0 0 on on off off 1
0 1 on off off on 1
1 0 off on on off 1
1 1 off off on on 0

Figure 2.8 CMOS technology

a a two-input NAND gate drawn conventionally and in an alternative way
which emphasises the paths from VDD and ground to the gate output;
b two-input NOR gate, again drawn conventionally and in an alternative
form;
c the fault-free action of the 2-input NAND gate.
Note that the capacitor shown in a and b represents the lumped
capacitance at the gate output
 Faults in digital circuits 33

open-circuit fault it is necessary for the test vector sequence to be 1 1 followed

by 0 1. Should T2 rather than Tl be the open-circuit path, then it requires 1
1 followed by 1 0 to detect this fault.
A different problem can arise with a fault in the series connection of the n-
channel FETs in Figure 2.8a. Here an open-circuit fault in either transistor
will prevent the gate output from being discharged to 0 V, but a short circuit
on a transistor can prevent the output from being fully charged to VDD via the
conducting p-channel transistor(s). However, when the n-channel transistors
are in parallel, as in the NOR gate of Figure 2.8&, open-circuit faults are now
memory faults, with short-circuit faults in the p-channel transistors
preventing the output from being fully discharged to 0 V via the conducting
n-channel transistor(s).
CMOS short-circuit faults, therefore, do not have the memory character-
istic of open-circuit faults, but instead allow a conducting path to be
established between VDD and ground on certain input vectors. For example,
in Figure 2.8a should T3 be short circuit then on the test vector 0 1 there will
be a path through Tl, T3 and T4, giving rise to an ambiguous output voltage
and an excessive current flow from VDD to ground. A check for this condition
is now usually made by IDDQ testing, which will be covered in Chapter 3.
A fully-exhaustive test set for single open-circuit and short-circuit faults
in a two-input NAND gate is therefore as shown in Table 2.3, where pairs of
test vectors may be regarded as an initialisation vector followed by a test
vector.

Table 2.3 An exhaustive test set for single open-circuit (O/C) and short-circuits (S/C)
faults in a two-input CMOS NAND gate
Input test Healthy gate Check
vector AB output Z
00 1 V/Vf= 1/0
0 1 1 T3 S/C check*
1 1 0 T l orT2 S/C check*;T3 orT4 O/C check
1 0 1 T2 O/C check
00 1
1 0 1 T4 S/C check*
1 1 0 (as test vector 1 1 above)
01 1 Tl O/C check
00 1
* excessive current if transistor short circuit V/Vf= 1/0
Bridging faults within CMOS gates also cause failures which may not be
modelled by the stuck-at fault model, particularly where more complex
CMOS structures are present. Consider the circuit shown in Figure 2.9. The
bridging fault shown will connect the gate output to ground under the input
conditions of AB + CD + AD + BC = 1 instead of the normal conditions of
AB + CD = 1. However when input conditions AD or BC = 1 are present, there
34 VLSI testing: digital and mixed analogue/digital techniques

DD

Figure 2.9 A possible bridging fault within a complex CMOS gate, the fault-free
output being Z = (AB + CD)
a the circuit topology
b the equivalent Boolean circuit

will be a conducting path from VDD to ground, and therefore excessive

dissipation will be present under these conditions. Notice that the equivalent
Boolean circuit for this complex gate, shown in Figure 2.9b, cannot model
this internal bridging fault, either as a stuck-at or bridging failure, and hence
fault modelling is generally inappropriate.
 Faults in digital circuits 35

The faults peculiar to CMOS structures were first described by Wadsack in

197835 and have been intensively considered since that date36"40. As will be
appreciated, the problems with CMOS testing are inherently related to the
fact that every CMOS logic gate consists of two dual parts, the p-channel and
the n-channel logic, and a fault in one half but not in the other half gives rise
to problems such as those which we have just considered.
The further problem of open or short circuits in FET transmission gates,
such as shown in Figure 2.10, does not appear to have received a great deal
of specific attention40'41, but the prevailing approach is that all CMOS faults
are best tested by functional testing and IDDQ current testing, rather than by
the theory and application of any form of fault modelling.
We will return to this important subject of CMOS testing again in the
following chapter.

2.4 Intermittent faults

Nonpermanent faults in a circuit or system are faults that appear and

disappear in a random way. There is, therefore, no predetermined set of
tests which can be formulated to detect such malfunctioning. Unfortunately,

master slave

alternative
symbol for
transmission
gates

clock

Figure 2.10 A CMOS D-type master-slave circuit using tranmission gate

configurations, where each ^-channel or n-channel FET may be con-
sidered open circuit or short-circuit under fault conditions. Note, if
entirely separate clock signals are supplied to the master and slave
circuits, it is possible to cause the complete circuit from D to Q to be
conducting (transparent) in test mode conditions, which may be useful
for test purposes but at the expense of doubling the clock lines in the
routed IC
36 VLSI testing: digital and mixed analogue/digital techniques

it has been reported that a major portion of digital system faults when
in service are intermittent (temporary) faults, and that the investigation of
such faults accounts for more than 90 % of total maintenance
expenditure42'43.
Nonpermanent faults may be divided into two categories, namely:
(i) transient faults, which are nonrecurring faults generally caused by some
extraneous influence such as cosmic radiation, power supply surges or
electromagnetic interference;
(ii) intermittent faults, which are caused by some imperfection within the
circuit or system and which appear at random intervals.
In practice it may not always be clear from the circuit malfunctioning which
of these categories is present, particularly if the occurrence is infrequent.
By definition it is not possible to test for transient faults. In VLSI memory
circuits a-particle radiation can cause wrong bit patterns in the memory
arrays, and in other latch and flip-flop circuits it is possible to encounter
latch-up due to some strong interference. However, once the memory or
storage circuits have been returned to normal, no formal analysis of the exact
cause of the malfunctioning is possible. Experience and intuition are the
principal tools in this area.
Intermittent faults, however, may possibly be detected if tests are repeated
enough times. This may involve repeating again what the system was doing
and the state of its memory at the time of the transitory fault, if known.
Alternatively, some abnormal condition may be imposed upon the circuit or
system, such as slightly increasing or decreasing the supply voltage, raising the
ambient temperature or applying some vibration, with a view to trying to
make the intermittent fault a permanent one which can then be investigated
by normal test means.
Since intermittent faults are random, they can only be modelled math-
ematically using probabilistic methods. Several authorities have considered
this, and developed probabilistic models intended to represent the behaviour
of a circuit or system with intermittent faults12'34'42"49. All assume that only
one intermittent fault is present (the single fault assumption), and develop
equations which attempt to relate the probability of a fault being present
when a test is being applied, and/or estimate the test time necessary in order
to detect an intermittent fault in the circuit under test.
An example of this work is that of Savir12'44'45. Two probabilities are first
introduced, namely:
(i) the probability of the presence of a fault, fi9 in the circuit, expressed as
PFi= probability (faulty is present);
(ii) the probability of the activity of the fault, fi9 expressed as
PA{- probability (faulty is active, faulty being present).
The circuit is assumed to have a fault set/1? f2, ..., fm, with only one fault, fi9
being present at a time. It should be appreciated that faulty- can be present
 Faults in digital circuits 37
but not affect the circuit output because that part of the circuit containing
the fault is not actively controlling the present output; probability PAi
therefore has a (usually very considerable) lower value than PF{. Also PFiy
i = 1 to m, forms the fault probability distribution
m

£«$ = l (2-6)

but this does not hold for PA^

A further probability PEt, termed the error probability is then introduced,
PE± being the conditional probability of an incorrect output being given by
the application of a randomly chosen input test vector, given that the faulty-
is active. Thus the probability, PDt, of detecting the faulty- by one randomly
chosen input test vector is given by:
PDt - PAt. PEl (2.7)
This mathematical development continues with an aim of determining
expressions for the mean time, MTi} which may be necessary to detect faulty-
with a given confidence limit and for other factors, for example:

where k is the time between test vectors, from which the lowest upper bound
on the number of tests, T, necessary to detect faulty with a given confidence
limit, cf[, is expressed by:

T= (2.9)
loge(l-PDt)

Further developments consider the effect of intermittent faults in disjoint

subsets, that is groups of faults which may be considered separately from
other groups of faults. However, although these mathematical considerations
throw light on, and to some extent quantify, the difficulties of testing for
intermittent faults, it is generally impossible to estimate real values for the
probability parameters Pi^ and PA^. Thus it is not possible to compute any
meaningful results that will directly help the test or maintenance engineer in
the detection of such faults in a given situation.
Alternative developments using Marcov models and probability matrices50
have been pursued by other authorities34'51"53, but again no real values are
generally available to use in the algebraic developments. We are, therefore,
left with the following strategies for intermittent fault detection which do not
involve any probabilistic modelling:
(i) repeatedly apply the tests which have been derived for the circuit or
system to detect permanent faults;
38 VLSI testing: digital and mixed analogue/digital techniques

(ii) build into the circuit or system some self-checking monitoring such as
parity checks (see Chapter 4), which will detect some if not all of the
possibly intermittent faults and ideally provide a clue to their location
in the circuit;
(iii) in the case of computer systems, continuously run a series of check tests
when the computer is idle, and from these hopefully build up
information pointing to the intermittent fault source when particular
check tests fail;
(iv) as previously mentioned, subject the circuit or system under test to
some abnormal working condition in an attempt to make the
intermittent fault permanent.
In the case of circuits used in safety critical applications, redundancy
techniques which will mask the effect of intermittent faults must be used. If it
is then found that, say, one of three systems operating in parallel is
occasionally out of step with the other two, this is an indication that there is
an intermittent fault in the first circuit, with possibly some clue to its source.

2-5 Chapter summary

This chapter has introduced the basic concepts of controllability and
observability of nodes within a digital circuit, but has shown that
quantification of these two parameters does not have a great practical
significance, particularly for VLSI circuits. Modelling the faults that can arise
in digital circuits, with a view to establishing tests which specifically detect
whether such faults are or are not present, has a longer record of success, the
stuck-at fault model being particularly significant.
Other fault models to cover bridging faults and intermittent faults have not
achieved the same success as the stuck-at model, largely because of the
complexities of modelling these other fault conditions. However, practical
experience, particularly with bipolar technology, has shown that the stuck-at
model will also detect most bridging faults and may detect intermittent faults
if applied a sufficient number of times. On the other hand, CMOS
technology exhibits some unique fault characteristics which are not
amenable to simple fault modelling.
In looking at all these fault models, it will be seen that they concentrate on
the gate level of the circuit design, and do not directly consider the overall
primary input/primary output functionality of the circuit. But as more and
more complexity is built into circuits, it has become no longer feasible to start
at gate level, or use gate level simulation. Instead, present-day VLSI test
philosophies concentrate on the functional or behavioural level, with
functional testing being adopted without specific reference to internal circuit
design and layout details54"56. Later chapters will, therefore, be largely
concerned with functional testing techniques, including self test, and little
reference will then be made to fault modelling except in very specific cases
such as memory or array structures.
 Faults in digital circuits 39

Finally, although this chapter has been particularly concerned with faults
in and fault models for digital circuits, no mention has yet been made of the
possible physical causes of such failures. A major problem here is that IC
manufacturers are reluctant to reveal exact details of their fabrication
defects; those statistics which are available are usually obsolete due to the
rapid and continual developments in fabrication technology and expertise.
There is a considerable volume of information available on the potential
causes of IC failure58"64. We must, however, distinguish between:
(a) some major failure during manufacture, such as incorrect mask
alignment or a process step incorrectly carried out, which it is the
province of the professional production engineer to detect and correct
before chips are bonded and packaged;
(b) the situation where wafer processing is within specification, but circuits
still need to be tested for individual failings.
The latter category of random scattered failures is our concern.
Considering the possible failure mechanisms which can occur in VLSI
circuits, these may be chip related, that is some fault within the circuit itself,
or assembly related, that is some fault in scribing, bonding and encapsulating
the chip, or operationally related, for example caused by interference or oc-
particle radiation. Further details of these categories may be found discussed
in Rajsuman^8 and in Prince64 for memory circuits, but no up to date global
information on the frequency of occurrence of these failures is available. An
early failure mode statistic quoted by Glazer and Subak-Sharpe59 gives the
following breakdown:
metalisation failures, 26 % of all failures;
bonding failures, 33 %;
photolithography defects, 18 %;
surface defects, 7 %;
others, 16 %.
Metalisation defects still seem to be a prominent category of defect, caused
particularly by microcracks in metal tracks where they have to descend into
steep narrow vias to make contact with an underlying layer of the planar
process, together with the difficulties of cleaning out etched vias before
metalisation. Dielectric breakdown also remains a problem should a SiO2
insulation layer be of imperfect thickness*, and chip bonding is still at times
a known cause of failure.
These failings may readily be related to the stuck-at fault model and open-
circuit faults, but from the test engineer's point of view (as distinct from the
IC manufacturer's point of view) the precise cause of a functional fault is of
academic interest only. We shall, therefore, have no occasion to look deeper

* The dielectric breakdown strength of SiO2 is about 8x 166V/cm, and the usual
thickness of a SiO2 layer is about 200 A0 = 2 x 10"6 cm. There is, therefore, not a very
great safety factor if the SiO2 is too thin.
40 VLSI testing: digital and mixed analogue/digital techniques

into failure mechanisms in this text, but the reader is referred to the
references cited above for more in-depth information if required.

2.6 References
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IEEE conference on Design automation, 1979, pp. 156-161
2 STEVENSON, J.E., and GRASON, J.: 'A testability measure for register transfer
level digital circuits'. Proceedings of IEEE international symposium on Fault
tolerant computing, 1976, pp. 101-107
3 BREUER, M.A., and FRIEDMAN, A.D.: TEST/80—a proposal for an advanced
automatic test generation system'. Proceedings of IEEE Autatestcon, 1979, pp.
205-312
4 GOLDSTEIN, L.M., and THIGAN, EX.: 'SCOAP: Sandia controllability and
observability analysis program'. Proceedings of 17th IEEE conference on Design
automation, 1980, pp. 190-196
5 KOVIJANIC, P.G.: 'Single testability figure of merit'. Proceedings of IEEE
international conference on Test, 1981, pp. 521-529
6 BENNETTS, R.G., MAUNDER, CM., and ROBINSON, G.D.: 'CAMELOT: a
computer-aided measure for logic testability', lEEProc. K, 1981, 128, pp. 177-189
7 RATIU, I.M., SANGIOVANNI-VINCENTELLI, A. and PETERSON, D.O.:
'VICTOR: a fast VLSI testability analysis programme'. Proceedings of IEEE
international conference on Test, 1982, pp. 397-401
8 BERG, W.C., and HESS, R.D.: 'COMET: a testability analysis and design
modification package'. Proceedings of IEEE international conference on Test,
1982, pp. 364-378
9 DEJKA, W.J.: 'Measure of testability in device and system design'.
Proceedings of IEEE Midwest symposium on Circuits and systems, 1977, pp. 39-52
10 FONG, J.Y.O.: 'A generalised testability analysis algorithm for digital logic circuits'.
Proceedings of IEEE symposium on Circuits and systems, 1982, pp. 1160-1163
11 BENNETTS, R.G.: 'Design of testable logic circuits' (Addison-Wesley, 1984)
12 BARDELL, P.H., McANNEY, W.H., and SAVIR, J., 'Built-in test for VLSI:
pseudorandom techniques' (Wiley, 1987)
13 ABRAMOVICI, M., BREUER, M.A. and FRIEDMAN, A.D.: 'Digital system testing
and testable design' (Computer Science Press, 1990)
14 CHEN, T-H., and BREUER, M.A.: 'Automatic design for testability via testability
measures', IEEE Trans., 1985, CAD-4, pp. 3-11
15 SAVIR, J.: 'Good controllability and observability do not guarantee good
testability', IEEE Trans., 1983, C-32, pp. 1198-1200
16 RUSSELL, G. (Ed.): 'Computer aided tools for VLSI system design' (Peter
Peregrinus, 1987)
17 AGRAWAL, V.D., and MERCER, M.R.: 'Testability measures—what do they tell
us?'. Proceedings of IEEE international conference on Test, 1982, pp. 391-396
18 KOHAVI, I., and KOHAVI, Z.: 'Detection of multiple faults in combinational
networks', IEEE Trans., 1972, C-21, pp. 556-568
19 HLAVICKA, J., and KOLTECK, E.: 'Fault model for TTL circuits', Digit. Process.,
1976, 2, pp. 160-180
20 HUGHES, J.L., and McCLUSKEY, E.J.: 'An analysis of the multiple fault detection
capabilities of single stuck-at fault test sets'. Proceedings of IEEE international
conference on Test, 1984, pp. 52-58
21 NICKEL, V.V.: 'VLSI—the inadequacy of the stuck-at fault model'. Proceedings of
IEEE international conference on Test, 1980, pp.378-381
 Faults in digital circuits 41

22 KARPOVSKI, M, and SU, S.Y.H.: 'Detecting bridging and stuck-at faults at the
input and output pins of standard digital computers'. Proceedings of IEEE
international conference on Design automation, 1980, pp. 494-505
23 SCHERTZ, D.R., and METZE, G.: 'A new representation of faults in
combinational logic circuits', IEEE Trans., 1972, C-21, pp. 858-866
24 BATTACHARYA, B.B., and GUPTA, B.: 'Anomalous effect of a stuck-at fault in a
combinational circuit', Proc. IEEE, 1983, 71, pp. 779-780
25 TIMOC, C, BUEHLER, M., GRISWOLD, X, PINA, C, SCOTT, E, and HESS, L.:
'Logical models of physical failures'. Proceedings of IEEE international
conference on Test, 1983, pp. 546-553
26 KARPOVSKI, M., and SU, S.Y.H.: 'Detection and location of input and feedback
bridging faults among input and output lines', IEEE Trans., 1980, C-29, pp.
523-527
27 ABRAHAM, J.A., and FUCHS, W.K.: 'Fault and error models for VLSI', Proc. IEEE,
1986, 75, pp. 639-654
28 MEI, K.C.Y.: 'Bridging and stuck-at faults', IEEE Trans., 1974, C-23, pp. 720-727
29 FRIEDMAN, A.D.: 'Diagnosis of short-circuit faults in combinational circuits',
IEEE Trans., 1974, C-23, pp. 746-752
30 ABRAMOVICI, M., and MENON, P.R.: 'A practical approach to fault simulation
and test generation for bridging faults', IEEE Trans., 1985, C-34, pp. 658-663
31 XU, S., and SU, S.Y.H.: 'Detecting I/O and internal feedback bridging faults',
IEEE Trans., 1985, C-34, p. 553-557
32 KODANDAPANI, KX., and PRADHAM, D.K: 'Undetectability of bridging faults
and validity of stuck-at fault tests', IEEE Trans., 1980, C-29, pp. 55-59
33 MALAIYA, Y.K.: 'A detailed examination of bridging faults'. Proceedings of IEEE
international conference on Computer design, 1986, pp. 78-81
34 LALA, P.K.: 'Fault tolerant and fault testable hardware design' (Prentice Hall,
1985)
35 WADSACK, R.L.: 'Fault modelling and logic simulation of CMOS and MOS
integrated circuits', BellSys. Tech.]., 1978, 57, pp. 1449-1474
36 GALIAY, J., CROUZET, Y, and VERGNIAULT, M.: 'Physical versus logic fault
models in MOS LSI circuits', IEEE Trans., 1980, C-29, pp. 527-531
37 EL-ZIQ, Y.M., and CLOUTIER, R.J.: 'Functional level test generation for stuck-
open faults in CMOS VLSI'. Proceedings of IEEE international conference on
Test, 1981, pp. 536-546
38 CHIANG, K.W., and VRANESIC, Z.G.: 'Test generation for complex MOS gate
networks'. Proceedings of IEEE international symposium on Fault tolerant
computing, 1982, pp. 149-157
39 RENOVELL, M., and CAMBON, G.: 'Topology dependence of floating gate faults
in MOS integrated circuits', Electron. Lett, 1986, 22, pp. 152-157
40 JAIN, S.K., and AGRAWAL, V.D.: 'Modelling and test generation algorithms for
MOS circuits', IEEE Trans., 1985, C-34, pp. 426-433
41 REDDY, M.K., and REDDY, S.M.: 'On FET stuck-open fault detectable CMOS
memory elements'. Proceedings of IEEE international conference on Test, 1985,
pp. 424-429
42 LALA, P. K., and MISSEN, J.I.: 'Method for the diagnosis of a single intermittent
fault in combinational logic circuits', Proc. IEE, 1979, 2, pp. 187-190
43 CLARY, J.B., and SACANE, R.A.: 'Self-testing computers', IEEE Trans., 1979, C-28,
pp.49-59
44 SAVIR, J.: 'Detection of single intermittent faults in sequential circuits', IEEE
Trans., 1980, C-29, pp. 673-678
45 SAVIR, J.: 'Testing for single intermittent failures in combinational circuits by
maximizing the probability of fault detection', IEEE Trans., 1980, C-29, pp.
410-416
42 VLSI testing: digital and mixed analogue/digital techniques

46 TASAR. O., and TASAR, V.: 'A study of intermittent faults in digital computers'.
Proceedings of MIPS conference, 1977, pp. 807-811
47 McCLUSKEY, E.J., and WAKERLY, J.F.: 'A circuit for detecting and analysing
temporary failures'. Proceedings of IEEE COMCON, 1981, pp. 317-321
48 MALAIYA, Y.K., and SU, S.Y.H.: 'A survey of methods for intermittent fault
analysis'. Proceedings of national Computer conference, 1979, pp.577-584
49 STIFLER, J.I.: 'Robust detection of intermittent faults'. Proceedings of IEEE
international symposium on Fault tolerant computing, 1980, pp. 216-218
50 SHOOMAN, M.L., 'Probabilistic reliability: an engineering approach' (McGraw-
Hill, 1968)
51 KOREN, L, and KOHAVT, Z.: 'Diagnosis of intermittent faults in combinational
networks', IEEE Trans., 1977, C-26, pp. 1154-1158
52 SU, S.Y.H., KOREN, I., and MALAIYA, Y.K.: 'A continuous parameter Marcov
model and detection procedure for intermittent faults', IEEE Trans., 1978, C-27,
pp. 567-569
53 KRISHNAMURTHY, B., and TALLIS, I.G.: 'Improved techniques for estimating
signal probabilities', IEEE Trans., C-38, pp. 1041-1045
54 BREUER, M.A., and PARKER, A.C.: 'Digital circuit simulation: current states and
future trends'. Proceedings of IEEE conference on Design automation, 1981, pp.
269-275
55 RENESEGERS, M.T.M.: The impact of testing on VLSI design methods', IEEEJ.,
1982, SC-17, pp. 481-486
56 'Test synthesis seminar digest of papers'. IEEE international conference on Test,
Washington, DC, USA, October 1994
57 BERTRAM, W. J.: 'Yield and reliability', in SZE, S.M. (Ed.): 'VLSI technology'
(McGraw-Hill, 1983)
58 RAJSUMAN, R.: 'Digital hardware testing: transistor level fault modelling and
testing' (Artech House, 1992)
59 GLASER, A.B., and SUBAK-SHARPE, G.E.: 'Integrated circuit engineering: design
fabrication and applications' (Addison-Wesley, 1979)
60 GALLACE, L.J.: 'Reliability', in Di GIACOMO, J. (Ed.): 'VLSI handbook'
(McGraw-Hill, 1989)
61 GULATI, R. K., and HAWKINS, C.F. (Eds.): 'I D D Q testing of VLSI circuits' (Kluwer,
1993)
62 CHRISTOU, A.: 'Integrating reliability into microelectronics and packaging'
(Wiley, 1994)
63 SABNIS, A.G.: 'VLSI reliability' (Academic Press, 1990)
64 PRINCE, B.: 'Semiconductor memories' (Wiley, 1995, 2nd edn.)
 Chapter 3
Digital test pattern generation

3.1 General introduction

The final objective of testing is to prevent faulty circuits from being
assembled into equipment, or to detect circuits which have developed faults
subsequent to their commitment. Our discussions here are largely in the
context of LSI/VLSI circuits, but apply equally to digital systems which have
comparable controllability and observability limitations.
Digital testing may be considered to have three purposes, namely:
(i) fault detection, which is to discover something wrong in a circuit or
system, ideally before it has caused any trouble;
(ii) physical fault location, which is the location of the source of a fault
within an integrated circuit;
(iii) component fault location, which is the location of a faulty component
or connection within a completed system.
This is illustrated in Figure 3.1. It is the top part of this diagram with which
we will be largely concerned; fault location is IC or system specific, requiring
intimate knowledge and expertise covering the particular component or
system.
Every digital test involves a situation such as shown in Figure 3.2a. At each
step every output test response has to be checked, which requires prior
knowledge of what the fault-free responses should be. For very simple circuits,
particularly of SSI and MSI complexity, the procedure shown in Figure 3.26
may be used; for more complex circuits the healthy output responses may be
held in memory as shown in Figure 3.2c.
In the situation shown in Figure 3.26 the input test set is usually fully
exhaustive, testing the circuit through all its possible input/output
conditions. However, as shown in Chapter 1, this becomes increasingly
impractical as circuit size escalates, and some more restricted test set to save
testing time is then required.
44 VLSI testing: digital and mixed analogue/digital techniques
, ,

test strategies
and procedures

••• • w

IC fault detection system fault detection

! __^—- vendor \^— OEM

fault location,
fault location,
objective replacement
objective to improve
and repair of system
IC yield

Figure 3.1 The heirarchy of digital testing objectives. Many test procedures are equally
applicable to IC and system test, but some may be IC or system specific.
Analogue testing, see later, has an identical heirarchy

One objective of digital testing, therefore, is to determine a nonexhaustive

test set for the circuit under test which will adequately test the circuit within
an acceptable time and cost. This reduced test set may be based upon fault
models, particularly the stuck-at model, or upon other procedures such as we
will consider later. However, it is often required to estimate how effective this
nonexhaustive test set is in detecting possible faults in the circuit under test.
This requires a fault simulation procedure, which is a parallel activity to test
pattern generation, and which may involve a very great deal of additional
computational effort1"6.
Early methods of fault simulation considered single stuck-at faults one at a
time. If there were /possible single stuck-at faults to be considered, then /
computer models of the circuit under test were generated, each containing
one fault source. The proposed test set was applied to each fault model in
turn, and a count, t, made of the number of faulty circuits which were not
detected by the proposed test set. From this procedure a value for the fault
coverage, usually known as the test coverage, TQ of the proposed test set was
calculated using the equation:
f-t xlOO% (3.1)
TC =
T
If the value for TC was unacceptably low, additional test vectors were sought
specifically to cover some of the faults that had escaped detection. This is
illustrated in Figure 3.3.
 Digital test pattern generation 45

accessible accessible
primary inputs pr mary outputs

\
input r x1 • output
network

: ""' f 1
test -7 under ^ test
set test response

n binary m binary
inputs outputs

outputs
input test set / circuit or network
/ under test
total agreement = pass
" ^ any disagreement = fail
gold circuit

some minimun input

test set

circuit or network
computer-controlled under test
test facility, for agreement = pass
digital inputs
example, see disagreement = fail
expected digital outputs
Figure 1.4

healthy response
from store

Figure 3.2 Digital testing procedures

a the basic: procec
procedure
b output response on every input test vector checked against a known-
good circuit, known as a gold circuit
c output response on every input test vector checked against the stored
healthy values held in the computer memory

This serial fault simulation procedure rapidly became very inefficient as

circuit size increased, and was superseded by three alternative techniques4
namely:
• parallel fault simulation;
• deductive fault simulation;
• concurrent fault simulation.
46 VLSI testing: digital and mixed analogue/digital techniques

generate set
of test vectors, T

evaluate fault
coverage of T using
fault simulation data

no / sufficient yes
\ ^ fault coverage?
1
\ /

modify or done
enhance test
setT

Figure 3.3 The general concept of determining the fault coverage of a given test set
from fault simulation. An eventual modification to increase FC may be by
interactive intervention by the test designer

All of these differ from the serial fault simulation method by simultaneously
simulating a set of faults rather than just one fault at a time. In parallel fault
simulation, one n-bit word in the simulation program (where n = 8, 16 or 32
bits) is used to define the logic signal on a node when the node is fault free
and when n - 1 chosen faults are present within the circuit. Since the
computer operates on words rather than bits, logical operations between
words corresponding to the logic of the circuit between the nodes (i.e. AND,
NAND, OR, NOR, etc.), allows the simultaneous simulation of the n copies of
the circuit to be implemented on each input test vector, thus speeding up the
simulation by a factor of about n compared with the one at a time serial fault
simulation. The main problem is that the circuit being simulated must be
expressed in Boolean terms, which means that memory and large sequential
circuit blocks are impractical or impossible to handle.
Deductive fault simulation, however, relies upon fault list data, that is the
input/output relationship of logic gates and macros under healthy and
chosen fault conditions. A fault list is associated with every signal line within
the circuit, including fault data flow through storage and memory elements.
For each input test vector fault lists are serially propagated through the
circuit to the primary output(s), all the faults covered by the test vector being
 Digital test pattern generation 47

noted after each pass. The time taken for one pass through the simulator is
much greater than the time for one pass through a parallel simulator, but a
large number of circuit faults will be covered on each pass. Dynamic memory
capacity, however, has to be very large in order to handle all the continuously
changing data in the propagation of the fault lists.
Concurrent fault simulation is the preferred present method of fault
simulation. It avoids the complexity of implementing deductive fault simu-
lation, yet retains a speed advantage over series and parallel fault simulation.
Here a comprehensive concurrent fault list for each line is compiled for each
test vector, which includes a chosen fault on the line plus all preceding faults
which propagate to this line; if a preceding fault produces a response which
is the same as the healthy response on this line to the test vector, the former
is deleted from this concurrent fault list. By completing this procedure from
primary inputs to primary outputs, a record is built up of the number of the
chosen faults detected by the given set of test vectors, and hence the fault
coverage; only those paths in the circuit which differ between the faulty and
the fault-free state need be considered in each simulation.
Further details of fault simulation procedures may be found in the
literature3'7"13. It must, however, be appreciated that when using any fault
model simulation to determine a fault model coverage value, FMQ for a given
set of test vectors, the resultant value only relates to the set of faults which
have been chosen in the simulation. Thus, FMC = 100 % only indicates that
all the faults introduced in the fault simulation will be detected, which is not
the same as saying that the circuit is completely fault free. The implication of
this is that the value of FMC is not necessarily the same as the value of fault
coverage, FC, introduced in Chapter 1, see Figure 1.3, and in theory should
not be used in the defect level equation DL = (1 - Yl~FC). However, if FMC is
nearly 100 %, then it is often assumed that FMC- FC, and this value of FMC
may be used in the equation for DL A more direct use for FMC is as a useful
parameter in the development and grading of automatic test pattern
generation (ATPG) algorithms, see later. We will use the designation FC
rather than FMC subsequently, but the distinction when used in the equation
for DL should not be forgotten.

3.2 Test pattern generation for combinational logic circuits

Test pattern generation is the design process of generating appropriate input
vectors to test a given digital design, whether it is a printed-circuit board
(PCB) or an individual IC. As previously noted, exhaustive testing is usually
prohibitively long unless steps are taken to partition the circuit or system into
smaller parts, in which case exhaustive testing of each partition may become
acceptable. However, assuming that this cannot be or is not done, then some
method of generating a reduced (nonexhaustive) test set has to be
undertaken.
48 VLSI testing: digital and mixed analogue/digital techniques

The generation of an acceptable reduced set of test vectors may be done in

the following ways:
(i) manual generation;
(ii) algorithmic generation;
(iii) pseudorandom generation.

3.2.1 Manual test pattern generation

Manual TPG is a method which the original circuit designer or OEM may
adopt, knowing in detail the functionality of the circuit or system involved.
The test patterns may be specified by considering a range of functional
conditions, and listing the input test vectors and healthy output responses
involved in these situations. Alternatively, the input vectors that will cause all
the gates to switch at least once may be considered. If a working breadboard
prototype has been made, then this may be used to assist the OEM in this
manual compilation, or alternatively the CAD program used in the design
may assist.
This strategy of relying upon the circuit designer to propose some
minimum set of test vectors can be a reasonable procedure to undertake for
circuits containing, say, a thousand but not tens of thousands of gates. It is a
procedure which has been and still is widely used in custom microelectronics
(ASICs or USICs), where the IC vendor is manufacturing a specific circuit to
meet the OEM's requirements14. The vendor will take the OEM's suggested
test vectors, and check that they are acceptable to both parties by performing
some CAD simulation; this may take the form of checking how many of the
internal nodes of the circuit are toggled by the suggested test vectors rather
than by considering any functionality of the tests. If this toggle coverage is
considered to be inadequate (or incomplete), additional test vectors will be
requested from the OEM to remedy the shortfall. It should be appreciated
that the computer processing time for this procedure is relatively small,
certainly far less than the excessive times which can build up when automatic
test pattern generation is attempted, see the following section.

3.2.2 Automatic test pattern generation

Automatic (or algorithmic) test pattern generation, usually abbreviated to
ATPG, becomes increasingly necessary as the gate count in the circuit
increases to the thousands upwards. ATPG programs normally use a gate-level
representation of the circuit, with all nodes or paths enumerated.
Figure 3.3 illustrated the concept of determining the fault coverage of a
given test set for a given circuit; here we will be considering starting with a
proposed fault in the circuit and finding a test for this fault, this procedure
being repeated for all the chosen set of faults in the circuit, see Figure 3.4.
The first test vectors that are determined tend to cover a number of faults,
see Figure 2.6 for example and Figure 3.13 later, and hence the initial fault
 Digital test pattern generation 49

prepare the
required fault list

select fault; determine

test pattern to detect
this fault

update fault coverage;

delete faults covered from
outstanding faults list

FC= 100%

print out achieved

fault coverage value FC
Figure 3.4 The ATPG procedure starting with a given fault list for the circuit and
finishing with a set of test patterns and their fault coverage value, FC

coverage can be rapid. However, for complex circuits the processing time to
find the tests for the final remaining faults may become unacceptably long,
particularly if feedback loops or other circuit complications are present. If
any redundancy is present then the ATPG program will, of course, never
succeed in finding a test for certain nodes. Hence, economics may dictate the
termination of an ATPG program when FC has reached an acceptable level,
say 99.5 %, or has run for a given time, leaving the outstanding faults to be
considered by the circuit designer if necessary. For very complex VLSI circuits
even ATPG programs are now proving to be inadequate, being replaced by
self test and other test strategies such as will be considered in later chapters.
All ATPG programs based upon fault models assume that a single fault is
present when determining the test vectors. The usual fault model is the stuck-
at model, which as we have seen does in practice cover a considerable
50 VLSI testing: digital and mixed analogue/digital techniques

number of other types of faults, but not all. The results of an ATPG program
cannot, therefore, guarantee a defect-free circuit.
A basic requirement in test pattern generation is to propagate a fault at a
given node in the circuit to an observable output, such that the output is the
opposite value in the presence of the fault compared with the fault-free
output under the same input test vector. This procedure may be termed path
sensitising or forward driving. A second requirement is that the test input
vector shall establish a logic value on the node in question which is opposite
to the stuck-at condition under consideration, i.e. to test for a s-a-0 fault at
node .x the test vector will give a logic 1 at the node under fault-free
conditions, and vice versa.
The principle of propagating a stuck-at fault condition on a node to an
observable output has been illustrated in Chapter 2, Figure 2.5. In this earlier
example a single path was sensitised to the primary output, but in more
complex circuits it may be necessary to consider more than single-path
sensitisation. Consider, for example, a simple part of a larger circuit as shown
in Figure 3.5, and let us consider the signals required to drive a stuck-at 0
fault on line Q through Gl to the observable output node. Clearly we require
P= 1, Q = 1 and R = 0 to establish this single path. However, if due to the
preceding logic it is not possible to have R = 0 when Q= 1, then this single
path sensitisation is not possible. But making P= 1, Q= 1, /?= 1 will allow the
fault to be detected at the output, the parallel paths through Gl and G2 both
being sensitised. This is known as parallel reconvergence with dual-path
sensitisation.
In Figure 3.5 the two paths which reconverge always took the same logic
value when testing for stuck-at 0. However, it is possible to encounter recon-
vergence where the two converging signals are always opposite to each other
under test conditions. (This is sometimes termed negative reconvergence, as
distinct from positive reconvergence where the signals are the same.) This
form of reconvergence is not testable, and indicates some local redundancy

Figure 3.5 A fragment of a combinational logic to illustrate dual-path sensitization

and positive reconvergence
 Digital test pattern generation 51

left in the circuit design. The more complex the combinational logic network,
the more likely it will be that reconvergence is present in the circuit. Hence,
the need to sensitise more than one path from a stuck-at node is often
encountered, which necessitates effective algorithms that can handle this
situation.
Most test pattern generation algorithms but not all have as their underlying
basis the procedure which we have now indicated, namely:
(i) choose a faulty node in the circuit;
(ii) propagate the signal on this node to an observable output;
(iii) backward trace to the primary inputs in order to determine the logic
signals on the primary inputs which correctly propagate this fault signal
to the observable output.
Additionally the procedure should:
(iv) ensure that the derived test vectors cater for all possible fan-out and
reconvergence effects in the circuit, with the possibility of multiple-path
sensitisation;
(v) keep a record of what additional faulty nodes are covered by each test
vector when generating a test for a chosen node (i.e. the fault cover of
each test vector), so that duplication of effort is minimised.
Here we will consider two methods which have been used for test pattern
generation, the first of which does not in fact use the above signal
propagation procedure, and the second which does use such a procedure.

3.2,2.1 Boolean difference method

The Boolean difference method is one test pattern generation technique
which does not rely upon path sensitisation, but instead is functionally based
using Boolean algebraic relationships to determine the test vectors. The
method is based upon the principle of using two Boolean expressions for the
combinational network, one of which represents the fault-free behaviour of
the circuit and the other the behaviour under a single complementary fault
condition. If these two functions are then exclusive-ORed together and the
result is not logic 0 this fault can be detected; if the result is logic 0, which
means that the two functions are identical under this fault condition, then
this fault cannot be detected1'2'15'16.
The formal definition of the Boolean difference of a given function/(X) of
n independent input variables x± to xn with respect to one of its input variables
xi is defined as:

-j-f(X) = f{xl,...,xi,...,xn)®f{xl,...,xi,...,xn) (3.2)

axi
If (d/dx^fiX) = 1 then the fault on input line x{ can be detected, if 0 it cannot
be detected since J[X) is then independent of xi. Notice that this operator is
52 VLSI testing: digital and mixed analogue/digital techniques

not a true differential operator in the full mathematical sense, since it does
not distinguish between a change of f(X) from 0 to 1 or vice versa, and hence
it is defined as a difference operator rather than a differential operator. Also
notice that the functions being exclusive-ORed together in eqn. (3.2)
represent the complete truthtable of J{X), and are not concerned with just
one input combination.
Further properties of the Boolean difference operator are as follows15:
• function complementation:

-Lf(X) = -j-f{X) (3.3)

dxi dxi

literal complementation:

d ,.,,„,, d

difference of Boolean difference:

• difference of Boolean product:

J-{f(X).g(X)\
1
= I f(X).-±g(X) ]0L(X).-±/(X)l©(j-fiX).J-g(X)) (3.6)
«fc,- ' { dx, ) { dx, ) [dx, dx, )

• difference of a Boolean sum:

-j-{f{X) + g(X)} = f JOT), y - g w l e (jffi.JLf{x)) © (-f(X) .-Lg(x)}(5.7)

dx^ * { dxt ) { dxt ) \dx} dxx )
• if the function g(X) is independent of x,, then eqns. (3.6) and (3.7)
collapse to:

y{f()g()} g ( ) ^ f ( ) (3.8)
dXj dXj

and

~ lf(X) + g(X)\ = i(X) — f(X) (3.9)

L J
dx{ rf^
and similarly should j\X) be independent of x{.
The test vector for primary inputs stuck-at 0 or stuck-at 1 are given by the
following:
 Digital test pattern generation 53

xz. — f(X), forx, s - a - 0 (3.10)

d
and

xi. — f{X)forxi 5-a-l (3.11)

dxt
For example, consider the circuit shown in Figure 3.6a. The Boolean
difference with respect to xl is given by the following algebraic development:

f(X) = (
dxxxx d

. (x2x4)\® \(x2x4) (x^Xz + x2x3x4)\

dxx j [ dxx J
d _ d

<*,-_«.
= (#2*4) (#1x2*3 +*2x3;c4) since {x2x4) is zero
^/xj " dxx

= (x2x4).(x2x3x4) .(x2xs)
- (#2 + *4 ) (*2 + *3 +
= x2x33c4 (3.12)
Thus, the test vector x^x^x4 will test for Xj s-a-0, and x^x^x4 will test for xx
s-a-1.
This result is very easily confirmed by looking at the Karnaugh map ofJ[X)
given in Figure 3.66, and considering the xx = 0 and xx = 1 halves of the map.
These two decompositions of J{X) differ only in the minterms x^x^x4 and
x 1X2X5X4, being/(X) = 0 in the former a n d / ( X ) = 1 in the latter. Hence the
Boolean difference (d/dxx)f(X) is x2x?>x4, giving the stuck-at test vectors for xx
shown above.
If the Boolean difference method is used to generate test vectors for
internal nodes of the circuit, the output function must be expressed in terms
54 VLSI testing: digital and mixed analogue/digital techniques

*3*4\ 00 01 11 10 XOXA
• 00 01 11 10
\ 4 \ 00 01 11 10
00 1 1 00 1 1 00 1 1 1

01 01 01 1 1 1 1

11 1 1 11 11 1 1 1 1

10 1 J] 1 10 1 1 10 1 1 1

^ f{x2x3x4) Xj f(x2x3x4)

Figure 3.6 A simple circuit to illustrate the use of the Boolean difference
a circuit, f(X) = x^x^x^ + #2*3 x4 + xgc^
b Karnaugh map off(X)t showing the decomposition about xx
c output function when internal node / is stuck at 0, the difference
between this function and the fault-free output being as indicated
d as c but /stuck at 1
of the internal node being considered. For example, should internal node /
in Figure 3.6 be considered, the output function becomes

f(X) = + x4l + x2xx

2 4

whence

dl dl

(3.13)

Therefore to test for /s-a-0 we have:

I X-^X<2 "i" X4 I
 Digital test pattern generation 55

and for /s-a-1 we have

=
X2X^ • X^X2

Figures 3.6^ and dwill confirm these results.

It will be seen that the Boolean difference method generates all the
possible test vectors for each faulty node considered, covering both s-a-0 and
s-a-1 faults. Should an algebraic expression reduce to 0 this indicates a
redundant line in the circuit under consideration. However, because Boolean
algebraic manipulations are tedious to handle with conventional computer
programs, the method requires a excessive amount of computer time and
memory to handle circuits of more than a few hundred logic gates, and as a
result algorithms which generate tests for more than one node at a time and
which we will consider shortly prove more satisfactory.
Further developments in the Boolean difference method may be found16.
It is also possible to consider more than one node simultaneously faulty using
higher-ordered Boolean difference equations, which if all possible single and
multiple stuck-at nodes are considered requires the evaluation of 2A Boolean
difference equations, where Nis the number of nodes or lines in the circuit.
This is even more impractical than the single stuck-at fault condition which
involves only iV Boolean difference equations. A more powerful technique
for handling this method has also been investigated; this uses the Gibbs
dyadic differentiator and logic values o f - 1 , +1 rather than 0, 1, and can
incorporate matrix manipulations in the computational procedures17"19.
However, no breakthrough in using these further developments has been
reported, leaving the Boolean difference method as a good educational
exercise but with little VLSI application.

5.2.2.2 Roth's D-algorithm

In contrast to the educationally-interesting Boolean difference method,
Roth's D-algorithm20 forms the underlying concept of many practical ATPG
programs. It sensitises all paths from the site of a chosen fault to an
observable output, and therefore inherently caters for reconvergent fan-out
situations. It does, however, operate at the individual gate level, and requires
knowledge of all the gates and their interconnection topology which
functionally-based ATPG programs do not necessarily need.
The D-algorithm involves five logic states, namely
0 = normal logic zero
1 = normal logic one
D = a fault-sensitive state of a line or node, where D = 1 under fault-free
conditions but is 0 under the particular fault condition being considered
D = a fault-sensitive state of a line or node, where D= 0 under fault-free
conditions but is 1 under the particular fault condition being considered
X = an unassigned logic value, which can take any value 0, 1, D or D
56 VLSI testing: digital and mixed analogue/digital techniques

Thus D identifies a line or node which is 1 under fault-free conditions and

changes to 0 under the chosen fault condition, and D identifies a line or node
which changes from 0 to 1 under fault conditions. D and D are always
opposite logic values.
Using these five logic states, the primitive D-cubes of failure for any type of
logic gate may be defined* Table 3.1 gives the relationships for all three-input
Boolean gates. The D-cube 1 1 1 D, see first line of Table 3.1, gives the input
pattern necessary to prove whether the output line of an AND gate is fault
free or stuck-at 0; D = 1 if no fault is present, and is 0 with the stuck-at fault.
Similarly, X X 1 D checks for a s-a-l fault at the output of a three-input NOR
gate. Similar tables may be compiled for all other gates and combinational
macros.

Table 3.1 The primitive D-cubes offailure for three-input Boolean logic gates, giving
the input signals necessary to distinguish the presence of the output line
stuck-at
Required inputs to detect faulty output Corresponding D-cubes of failure
inputs output
A 8 c Z A 8 C Z
A N D gate 1 1 1 s-a-0 1 1 1 D
0 X X s-a-l 0 X X D
X 0 X s-a-l X 0 X 0
X X 0 s-a-l X X 0 D
N A N D gate 1 1 1 s-a-l 1 1 1 D
0 X X s-a-0 0 X X D
X 0 X s-a-0 X 0 X D
X X 0 s-a-0 X X 0 D
OR gate 0 0 0 s-a-l 0 0 0 D
1 X X s-a-0 1 X X D
X 1 X s-a-0 X 1 X D
X X 1 s-a-0 X X 1 D
NOR gate 0 0 0 s-a-0 0 0 0 D
1 X X s-a-l 1 X X D
X 1 X s-a-l X 1 X D
X X 1 s-a-l X X 1 D

The requirements for propagating (sometimes termed D-drive) any D value

through following fault-free gates are given in Table 3.2. This information is
known as the propagation (or propagating) D-cubes for each type of gate. For
example, with a single stuck-at 0 signal on input x% of a three-input NAND

* In this context, a cube is an ordered set of symbols such that each symbol position
defines a particular input or output node, and the value of the symbol identifies its
logic state.
 Digital test pattern generation 57

gate we have the D-cube 1 D 1 D, see the top line of Table 3.2. Notice also
that:
(i) the propagating Z>cubes also define the propagation when more than
one input is D or D, which can arise in a circuit with reconvergent fan-
out from the original D (or D) source. However, should D and D both
converge on a Boolean gate there will be no further propagation of the
D or D value; D and D on an AND gate will always give an output 0 and
on an OR gate an output 1, and hence the D and 5 values will be lost.
(ii) for the propagation of a D (or D) value through a Boolean gate there is
only one possible input condition; there is therefore no choice of logic
0 or 1 signals on the gate inputs to propagate the D signal (s).

Table 3.2 The propagation D-cubes for (a) three-input AND and NAND gates, and (b)
three-input OR and NOR gates, the gates being fault free
a
Gate inputs, x ( x 2 x 3 Gate output f[X)
AND gate NAND gate
I I D or I D I or D I I D D
I I D or I D I or O i l D D
I D D o r D I D o r D D I D 0
I D D or D I D or D D I D D
ODD D D
D D D D D

b
Gate inputs, X| x 2 x 3 Gate output f(X)
OR gate NOR gate

0 0 D or 0 D 0 or D 0 0 D D
0 0 D or 0 D 0 or D 0 0 D D
0 D D or D 0 D or D D 0 D D
0 D D or D 0 D or D D 0 D D
D D D D D
D D D D D

The propagating Z>cubes represent a subset of all the possible five-valued

input/output relationships of combinational logic gates, being the subset in
which D (or D) is driven from gate input(s) to gate output. For two-input
Boolean gates we have the full relationships shown in Figure 3.7, with six
input conditions being fault propagating. For three-input Boolean gates
there are 5 x 5 x 5 = 125 possible input conditions, but only fourteen are fault
propagating.
A simple example of D propagation is shown in Figure 3.8. The chosen
fault source on the output line from G3 is driven to both primary
(observable) outputs by the signals shown. Should G4, G5 and G6 be other
58 VLSI testing: digital and mixed analogue/digital techniques

than the two-input gates shown here, then the propagation Z>cubes for these
gates would define the required logic signals for forward driving the D or D
conditions. All possible paths from the D or D source towards the primary
outputs are normally considered 16 ' 18 , although only one primary output
needs to be finally monitored for the stuck-at test.

AND OR inverter

^ o 1 X D D ^ 0 1 X D D A Z
0 0 0 0 0 0 1 X D D 0 1

0 1 X D D 1 1 1 1 1 1 0

X X X X X X 1 X X X X X
0 D X D 0 D D 1 X D 1 D D
0 D X 0 D 5 D 1 X 1 D D D

NAND NOR

equivalent three-input
1 X D D 0 1 X D D AND gate
1 1 1 1 1 1 0 X D 0 , j

1 0 X D D 0 0 0 0 0
1 X X X X X 0 X X X
1 D X D 1 D D 0 X D 0
1 D X 1 D D 0 X 0 D

Figure 3.7 Roth s five-valued D-notation applied to two-input Boolean logic gates. The
relationships for three (or more) input gates may be derived by considering
a cascade of two-input gates, since commutative and associative
relationships still hold

Roth's full algorithm for test pattern generation thus consists of three
principal operations as shown in Figure 3.9, namely:
(i) choose a stuck-at fault source, and from the primitive D-cubes of failure
data identify the signals necessary to detect this fault;
(ii) forward drive this fault D or D through all paths to at least one primary
output, using the information contained in the propagation D-cubes;
(iii) perform a consistency operation, that is backward trace from a primary
output to which D or D has been driven, to the primary inputs,
allocating further logic 0 and 1 values as necessary to give the final test
input vector.
 Digital test pattern generation 59

MX)

chosen fault source,

stuck-at 1 = O

Figure 3.8 An example using Roths notation, shoxving a stuck-at 1 fault being
driven to both primary outputs. D represents the same logic value on all
lines so marked, with the line marked D having the opposite logic value.
The numbers in parentheses are used later in the text

This procedure is repeated until all the chosen stuck-at paths have been
covered.
In undertaking the Zklrive, the operation known as D-intersection is
performed for each gate encountered from the source fault to the primary
output(s). This is an algebraic procedure which formally matches the
logic signals on the gates with the appropriate propagation Z>cube data.
Recall that the propagation data for any D or D gate input is unique. The
i>drive procedure for the simple circuit shown in Figure 3.8 would therefore
proceed as shown in Table 3.3, having first identified all the paths in the
circuit.

Table 3.3 The D-drive conditions for Figure 3.8

Circuit path I 2 3 4 5 6 / 8 9 10 1 1 12
Select (7) stuck-at I Q * 9 *
Intersect with G4 propagation D-cube 0 # • • D 1 D • • •
Intersect with G5 propagation D-cube 0 • • • D 1 D 0 D •
Intersect with G6 propagation D-cube 0 • • • I I D 1 f) 0 D D

The consistency operation to follow this D-drive evaluation is shown in Table

3.4. No inconsistencies are found, and hence the stuck-at fault at (7) can be
detected by the input test vector #1X2*3*4*5*6, giving a logic 0 at the primary
output f (X) if the fault is present.
60 VLSI testing: digital and mixed analogue/digital techniques

start

select stuck-at fault

from fault list

choose primitive D-cube

of failure to sensitise
the chosen stuck-at fault

D-drive to
primary outputs

backward trace to primary

inputs to establish test
input vector

any
inconsistencies
in backward allocate
trace? other 0, 1
list input test vector conditions
and all stuck-at
fault lines covered

all
no stuck-at
faults covered?

end
Figure 3.9 The outline schematic of Roth s D-algorithm ATPG procedure
 Digital test pattern generation 61

Table 3.4 The backward tracing consistency operation for Table 3.3
Circuit path 1 2 3 4 5 6 7 8 9 10 1 1 12
End of D-drive 0 # # # 1 1 D 1 D 0 D D
Check (8) is at 1 from G2; OK if (4) = 1 0 • • 1 1 1 D 1 D 0 D D
Check (10) is at 0 from G1
O K i f ( l ) (2) &(3) = 0 0 0 0 1 1 I D 1 D 0 D D
In this example no inconstancies are encountered in completing the
backward tracing operation. However, if we had started with the equally valid
primitive i>cube of failure for gate G3 of xx xb = 1 0 or 1 1 instead of 0 1, then
we would have encountered an inconstancy in gate Gl when backward
tracing from node 10 to the inputs. Hence, in practice, we may have to
recompute the 2>drive conditions trying alternative primitive />cubes as the
starting point.
Further difficulties with the Z>algorithm arise when exclusive-OR/NOR
gates or local feedback conditions are encountered. The problem with
exclusive gates is that there is not a unique input condition for propagating
a D or D signal, see Table 3.5, and reconvergence of D or D or D and D will
be nonpropagating.

Table 3.5 The propagation D-cubes for two-input exclusive gates

Gate inputs, x ( x2 Gate output f[X)

ex-OR ex-NOR

0 D or D 0 D D
0 D or D0 D D
1D or D 1 D D
1D or D 1 D D

To summarise the principal characteristics of Roth's algorithm:

(i) the algorithm guarantees to find a test for any stuck-at fault in a circuit
if such a test exists; if a stuck-at 0 fault cannot be detected then a steady
logic 0 signal could be substituted at this node without affecting any
primary output; similarly, if a stuck-at 1 fault cannot be detected a steady
logic 1 signal could be substituted; if neither a s-a-0 or a s-a-l fault can
be detected then this node is completely redundant and could be
removed from the circuit.*
(ii) the test vector for the detection of any given stuck-at fault source is also
the test vector for all the following stuck-at conditions encountered in
the D-drive from the fault source to the observable output; for example
the test vector x^x^x^x^x^x^ in the above example will detect s-a-l
* There are many published examples of circuits which purport to show why a stuck-
at fault cannot be detected by fault modelling. What is not always clear is that these
are usually examples where there is redundancy in the circuit which the author may
not mention.
62 VLSI testing: digital and mixed analogue/digital techniques

conditions on lines (9) and (12) and s-a-0 on line (11) as well as the
fault source on line (7).
(iii) it is the difficulty of assigning input signals for a given gate output in
the backward tracing operation which largely causes problems; unlike
the forward D-drive operation there can be a choice of gate input
signals for a given output, since 2n - 1 input combinations of any n-
input Boolean gate give rise to the same gate output condition, and
hence several retries of the algorithm to find a consistent backward
tracing operation may be necessary.
A more detailed analysis and discussion of the D-algorithm may be found in
the appendix of Bennetts2(k*; other texts have worked examples1'2'11'20'21
and software code fragments11. However, it remains a difficult topic to learn,
partly because of the terminology which was introduced in the original
disclosures, and because of the supporting mathematics based upon the so-
called calculus of D-cubes. Nevertheless, it remains a foundation stone in
ATPG theory.
Finally, for interest, the Boolean difference technique applied to the
circuit of Figure 3.8 would give the Boolean difference functions:

— fi(X) = x2x2 + x2xs + X}X2 + x^x4 (3.14)

dF
and
— MX) = xlXe + x2x6 + x4x6 + * 5 * 6 (3.15)
or
for the two outputs f\(X) and ^(X) with respect to the fault source F on
line (7).
Hence the tests for a stuck-at 1 fault on line (7) would be:
(xx + x5) {x{x2 + x2x3 + xxx2 + xlx4)
= x-{x2 or x^x2x^ or x2x%x5 or xxx2xb or xxx4x5
at output /i(X), and
(*! + X5) (tfjXg + X2Xd + X4X6 + X5XQ)
= tfjXg o r x5x6
at output f2 (X). The tests for a stuck-at 0 fault on line (7) similarly would be:
(xx + x5) {x{x2 + x2xs + xxx2 + xlx4)
2itfi{X) and

at^(X). Notice that our Roth's algorithm example merely identified one of
the possible test vectors which detect the s-a-1 fault on line (7).

* The terminology 'dual' used in Reference 20c should be read with care. It is not the
Boolean dual/Z)(X) of/(X) where fD(X) is the complement o f / ( ^ with jill gate inputs
individually complemented, but is the changing of all DstoD and all Ds to D in any
given propagation Z>cube, leaving the 0s and Is unchanged.
 Digital test pattern generation 63

3.2.2.3 Developments following Roth's D-algorithm

Although Roth's algorithm guarantees to find a test for any stuck-at fault
if a test exists, and is found to be more computational efficient than the
Boolean difference method, a very great deal of CPU time is still involved
which precludes its use for circuits containing thousands of logic gates.
A later modification by Roth et aV20a improved the situation to some
degree by performing the consistency backward tracing as the D-drive
progresses, rather than waiting until the D-drive has reached a primary
output, but alternative developments have now built upon these pioneering
approaches.
A modification of the Z>algorithm which works from the primary outputs
backwards to determine a sensitive path was the LASAR (logic automated
stimulus and response) algorithm22"24. Essentially, this algorithm assigned a
logic value to a primary output, and then followed paths back through the
circuit assigning gate input values which gave the required output value.
However, this algorithm in turn has been succeeded by the PODEM (path
oriented decision making) algorithm25"27, which has formed a basis for many
still-current ATPG programs.
PODEM uses the basic concept of using five logic values 0, 1, X, D and D
and a Z>drive operation as introduced by Roth, but operates in a dissimilar
manner by initially backward tracing from each chosen fault source
(sometimes termed the target fault) towards the primary inputs before
commencing a Z>drive towards the primary outputs. The procedure is as
follows.
(i) set all nodes (lines) in the circuit to X (unassigned);
(ii) choose a stuck-at 0 (D) or a stuck-at 1 (JD) gate output fault from the
fault list; assign this node to 1 if s-a-0 is chosen and to 0 if s-a-l is chosen
(these are the logic levels necessary for the stuck-at test); leave all
remaining nodes at X;
(iii) choose one of the gate input nodes, and assign a logic 0 or 1 to it which
is appropriate for testing the chosen stuck-at gate output (see the
primitive D-cubes of failure given in Table 3.1);
(iv) backward trace from this assigned gate input node to a primary input or
inputs, allocating 0 or 1 as appropriate to the primary input(s) which
give this gate input condition; leave all unassigned primary inputs and
other circuit nodes at X;*
(v) simulate the circuit with these 0, 1, X values, and check whether the
required logic 1 (now identified as D) or logic 0 (now identified as D)
is established at the chosen fault source;
* Care should be taken with the terminology that may be found in existing literature.
The term 'backtrace' is what we are here calling backward trace, and is a consideration
of the signals on certain nodes in the circuit working backwards towards the primary
inputs. The term 'backtrack', however, which we will not use here, is a starting again
(retry) of a procedure or part of a procedure, which may proceed backwards towards
the primary inputs or forwards towards the primary outputs.
64 VLSI testing: digital and mixed analogue/digital techniques

(vi) if it is established, which means that the primary input assignment of 0,

1, X is appropriate for the stuck-at test of the target fault, proceed to
(viii) below;
(vii) if it is not established, repeat (iii), (iv) and (v) (possibly several times)
with alternative assignments until the correct primary assignment for
the chosen stuck-at condition is achieved (note, if no primary assign-
ment can be found for the chosen fault, then this fault is untestable);
(viii) with this partial input test vector 0, 1, X, ZMrive the chosen stuck-at gate
output node to a primary output by randomly allocating 0 and 1 to the
remaining X inputs, until D (or D) is detected at an output by
simulation of each situation;
(ix) when successful accept this primary input assignment of 0, 1, X as the
test vector for the chosen stuck-at fault;
(x) repeat procedures (i) to( viii) until all stuck-at nodes in the fault list
have been covered, returning all nodes to X at the beginning of each
test.
This procedure is summarised in Figure 3.10.
Like Roth's original Z>algorithm, PODEM guarantees to find a test vector
for any stuck-at fault in the circuit, if such a test is possible. The initial choice
of the partial primary input assignment 0, 1, X before undertaking the
2>drive operation is found to be particularly effective in reducing the total
computational effort for the complete circuit under test compared with
Roth's original procedure.
There are additionally further mechanisms built into the full PODEM
procedure which are not detailed in Figure 3.10. These include:
(a) recognition of AND, NAND, OR and NOR gates for both the backward
tracing and subsequent Zklrive operations;
(b) where one gate input in the backward tracing operation is sufficient, the
gate input which has the easiest controllability from the primary inputs
is first assigned; where all gate inputs have to be assigned then the
hardest controllability paths to the primary inputs are chosen so as to
cover them at this early stage of the procedure;
(c) the simulator used is a simple zero-delay, five-valued simulator, which
can rapidly check the 0, 1, X, D, D values without involving any timing
or possible circuit race conditions.
The full three-part schematic diagram for PODEM may be found in
Reference 26, and republished in References 1 and 2. A more readily-
followed three-part schematic and worked examples may be found in
Bottorff28. A further detailed worked example may also be found in Refer-
ence 27, which includes a circuit known as the Schneider counter example
shown in Figure 3.11; the stuck-at 0 fault on gate output G2 would be
detected by first completing the backward trace from the fault source, giving:
X} X2 #3 X4 = X 0 0 X
 Digital test pattern generation 65

I start

initialise ail circuit nodes

including primary inputs to X

select stuck-at fault on a

gate output from the fault list (D or D)

assign necessary gate input(s) to

0 or 1 to test for the selected stuck-at fault
repeat,
select
next fault
from fault backward trace from assigned gate input(s)
list to establish necessary 0, 1 primary inputs

simulate the circuit try

simulation new
with these 0, 1, X inputs
assignment

JS1(=0)
yes; now D (or D) or 0 (= D) now establishe no; still X
at the selected
yes; output ault source?
D(orD)
D (or D) already
driven to a primary
utput?
randomly assign further primary
inputs from X to 0 or 1 until
simulation
D (or D) is driven to a primary
output on resimulation

ok; accept this

test vector

all
faults in fault
list now
covered?

Figure 3.10 Outline schematic of the PODEM ATPG program, starting with all
nodes and primary inputs at X. Exit paths (not shown) are present if no
test for a given stuck-at fault is possible
66 VLSI testing: digital and mixed analogue/digital techniques

stuck-at 0 node

Figure 3.11 Schneider's symmetrical circuit example, which is frequently used to

demonstrate test pattern generation aspects. See also the example given
in Figure 3.8

Attempting a single-path 2>drive from this fault source to the primary output
via gate G5 or gate G6 would reveal an inconsistency; for example, driving
through G5 only would result in 0 D 0 1 on gate G8 with the input test vector
0 0 0 1, or driving through gate G6 only would result in 1 0 D 0 with the input
test vector 10 0 0, neither of which would give a D output. The only test
possible is the test vector 0 0 0 0, which drives D through both G5 and G6 to
G8. The PODEM algorithm, however, would have found this test almost
immediately by trying this test vector from the given starting point of X 0 0 X.
Notice that with this fairly trivial example there are only four possible test
vectors to try, namely 0 0 0 0, 0 0 0 1 , 1 0 0 0 and 1 0 0 1 . Also the actual
circuit is highly artificial, being merely Z= x1x2%*4 + *i*2*3*4 which changes
to x^x^x^x4 under the given stuck-at fault condition.
A further development by IBM of PODEM-X has been used for the test
pattern generation of circuits containing tens of thousands of gates26.
PODEM-X incorporates an initial determination of a small set of test vectors
which will cover a high percentage of faults in the fault list, leaving the
PODEM procedure to cover the remainder. This will be considered further in
section 3.2.3. However, a more distinct variation of the PODEM algorithm is
the FAN (fan-out oriented) ATPG program of Fujiwara and Shimono29,
which specifically considered the fan-out nodes of a circuit, and uses multiple-
path forward and backward tracing.
The major introduction in FAN is when considering a backward trace from
a given D or D node. The procedure is broadly as follows:
 Digital test pattern generation 67

(i) from a given fault source, backward trace appropriate 0 or 1 assigned

logic values until a gate output is reached which has fan-out, i.e. one or
more extra paths is fed from this node in addition to the path from the
chosen fault source; stop the backward trace at this point if
encountered; otherwise continue right back to the primary inputs (this
is unlike PODEM, which always continues back to the primary inputs
irrespective of fan-out conditions);
(ii) with this assigned set of 0, 1 and X signals forward trace to determine
all the resulting 0, 1 and X signals, including the fan-out branches if the
backward trace was halted at a fan-out node;
(iii) if D (or D) is driven to a primary output continue with (v) below; if D
(or D) is not yet driven to a primary output, backward trace as in (i)
above from all gates to which D or D has now been driven (the D-
frontier), assigning 0 or 1 as appropriate to drive each D or D forward;
(iv) Repeat (ii) and (iii) until D (or D) is driven by a forward trace to a
primary output;
(v) with D (or D) at a primary output, backward trace to assign all
remaining necessary 0 and 1 signals from the fan-out nodes to the
primary inputs, leaving any unrequired inputs at X.
It will therefore be seen that the FAN algorithm proceeds in steps of forward
and backward tracing, attempting at each step to assign consistent 0 and 1
logic values to the nodes which are instrumental in propagating D or D
towards a primary (observable) output. However, the steps are more complex
than indicated here, since conflicts of assigned 0 and 1 logic values may
arise which necessitate retries with different assigned values where a choice
is possible, but unlike PODEM such conflicts are largely localised and
resolved by retry at each step. It is therefore claimed that FAN is three to four
times more efficient than PODEM for circuits containing thousands of logic
gates.
The FAN algorithm is summarised in Figure 3.12. A full three-part
schematic may be found in Reference 29 and reprinted in Reference 1. A
comprehensive but simplified schematic may also be found in Reference 28.

3.2.3 Pseudorandom test pattern generation

The ATPG algorithms of the previous section are deterministic, being based
upon the choice and detection of a single stuck-at fault by an appropriate
input test vector. Although each test considers one fault as the starting point
for the determination of a test vector, each test vector covers more than one
stuck-at node, and a final consolidation to the minimum number of test
vectors (the minimum test set) to cover the complete stuck-at fault list can be
implemented. See Figure 2.6 for example.
Deterministic ATPG algorithms provide the smallest possible test set to
cover the given fault list. The disadvantage is the complexity and cost of
68 VLSI testing: digital and mixed analogue/digital techniques

start

initialise all circuit nodes

including primary inputs to X

select stuck-at fault on

gate output from the fault list D (or D)

assign necessary gate input(s) to

0 or 1 to test for the selected stuck-at fault

backward trace from assigned gate try new

repeat, input(s) to fan-out node(s), or primary assignment(s)
select next inputs if no fan-out node encountered
fault from
fault list
forward trace all 0, 1, X signals to
simulation
driveD (or D) towards primary outputs

any
logic value
inconsistencies?

has
D (or D) reached
a primary output?

backward trace from all fan-out nodes backward trace from furthestmost
and other lines to establish primary inputs D (or D) nodes, assigning Jogic 0, 1
so as to propagate D or D further

end
Figure 3.12 Outline schematic of the FAN ATPG program, starting ivith all nodes
and primary inputs at X. Exit paths (not shown) are present if no test
for a given stuck-at fault is possible

generating this minimum test set.* On the other hand a fully exhaustive test
set will incur no ATPG costs, but will usually be too long to employ for large
circuits. There is, however, an intermediate possibility which has been used.

* It has been reported28 that millions of retries have been found necessary in some
circuits of VLSI complexity before the test vectors to cover the complete set of faults
were determined.
 Digital test pattern generation 69

It is intuitively obvious that fault coverage increases with the number of

input test patterns which are applied, up to the full fault coverage; a single
randomly chosen input test vector is also likely to be a test for several faults in
a complex circuit. Hence if a sequence of random or pseudorandom input
test vectors (see later) is used, it is probable that a number of circuit faults will
be covered without incurring any ATPG cost.
The relationship between the number of applied random test vectors and
the resultant fault coverage has been studied21 >30"33. Tests made by
Eichelburger and Lindbloom32 on two combinational circuits containing
approximately 1000 gates are shown in Table 3.6. From this work the
expected fault coverage, FQ achieved by the application of N random test
vectors is given by the relationship:

(3.14)
where X is a constant for the particular circuit under test. The general
characteristic of this relationship is shown in Figure 3.13, which confirms the
intuitive concept that it is relatively easy to begin the fault coverage but
becomes increasingly difficult to cover the more difficult remaining faults in
the fault list.

Table 3.6 The fault coverage obtained on two circuits by the application of random test
vectors. Note, a fully-exhaustive functional test set would contain 263 and
2 test vectors, respectively
Circuit No. of primary inputs No. of gates % fault coverage obtained
with N random test patterns
N = 100 1000 10000

(a) 63 926 86.1 94.1 96.3

(b) 54 1103 75.2 92.3 95.9

A truly random sequence of test vectors, which includes the possibility of

the same vector occurring twice within a short sequence, is difficult to
generate. Also, it is usually unproductive to apply the same test vector more
than once in a test procedure. Hence it is more practical to consider the use
of pseudorandom patterns, which are very easy to generate. The theory of
pseudorandom pattern generation will be given in Section 3.4; suffice here to
note that in a n-bit vector there can be a maximum of 2W-1 sequences before
the sequence repeats, with each bit in the sequence having the same number
of changes between 0 and 1. Hence 0s and Is are equally probable on each
bit.
Therefore, for a circuit with n primary inputs, it is appropriate to take a
very small subset of the 2n -1 pseudorandom sequence to use as the random
test set. The number of faults that are covered by this test is determined by
normal simulation, leaving the small percentage of faults which have not
been detected to be covered by using PODEM or FAN or some other
70 VLSI testing: digital and mixed analogue/digital techniques

100-i

no. of applied test vectors

Figure 3.13 The general characteristics of fault coverage versus the number of
random test vectors applied to the circuit

deterministic ATPG procedure. Prior analysis by probability theory34"38 of the

effectiveness of the pseudorandom vectors in testing a given circuit is not
particularly useful, since with a complex circuit the computational effort
involved could be comparable with performing a deterministic ATPG
computation for the whole circuit, which is the thing we are trying to avoid
having to do.
A slightly different approach has been attempted in the RAPS (random
path sensitising) procedure, which is combined with PODEM in the PODEM-
X procedure to complete the test coverage26'39. RAPS selects at random a
primary output and allocates again at random a logic 0 or 1 to it. From this
assignment a backward trace is made to determine the necessary primary
inputs. This is repeated until a number of input test vectors are generated.
The global fault coverage of this randomly generated input test set is then
computed by simulation, leaving the remaining clean-up faults on the fault
list to be covered by PODEM.
A particular characteristic of this approach is the very small number of
random input test vectors used, being a very small multiple of the number of
primary outputs irrespective of the complexity of the network. This is due to
the complete sensitisation of multiple paths from outputs back to inputs
during each random test vector determination. A worked example of this may
be found in Reference 27.

3.3 Test pattern generation for sequential circuits

So far our considerations have involved combinational circuits only, which
have been flattened to gate level with stuck-at conditions considered at every
node. In general, the latch and flip-flop elements of a sequential network
cannot be broken down to individual gate level without breaking all the
inherent feedback connections—if they could then the test pattern
 Digital test pattern generation 71

generation problem would become purely combinational with perhaps

limited controllability and observability—and therefore we have to consider
the possible states of the circuit as well as the combinational aspects. It will
also be recalled from earlier in this text that to consider the exhaustive test of
a circuit containing n logic gates and s latches or flip-flops would theoretically
require 2n+s input test vectors, which is an impossibly high number to
consider for LSI and VLSI circuits.
The classic model for any sequential network is shown in Figure 3.14. If the
present primary outputs zx to zm are a function of the present secondary
inputs yi to ys (the memory states) and the present primary inputs x{ to xn,
then the model is a Mealy model; if the outputs are a function of ^ to j^only
then the model is a Moore model. In both cases it is not possible to define the
fault-free outputs resulting from a primary input test vector without
knowledge of the internal states of the memory. Also it will be appreciated
that the two halves shown in Figure 3.14 are in practice often inextricably
mixed, with XVJ and yi lines buried within the circuit unless some specific
silicon layout is present.
The basic difficulty with testing the circuit model of Figure 3.14 is that the
logic values y} to ys are generally unknown. If they were observable then
testing of the top half of the circuit could be entirely combinational, and
testing of the bottom half would be by monitoring yl to ys during an
appropriate set of primary input test vectors. However, assuming y± to ys are
inaccessible, developments as follows must be considered.
The first problem is to initialise the memory elements to a known state
before any meaningful test procedure can continue. This may be done in the
following ways:

(i) Apply a synchronising input sequence to the primary inputs which

will force a fault-free circuit to one specific state irrespective of
its initial starting state1'40. This is only possible in special cases where
the states always home to a given state and remain there in the
presence of a certain input vector—a counter which free runs but is
stopped when it reaches 1 1 1 1... by a certain input vector is a trivial
example.
(ii) Apply a homing input sequence to the primary inputs which finally
gives a recognisable output sequence from a fault-free circuit
irrespective of its initial starting state1'40"43. Depending upon which
output sequence is recognised, the final state (but not the initial state)
of the circuit is known.
(iii) A special case of the homing input sequence is the distinguishing input
sequence, where the circuit output response is different for every
possible starting state41. If this is possible, then both the initial and final
states of the circuit are known. Most sequential circuits, however, do not
have a distinguishing input sequence, although all do have one or more
homing input sequences.
72 VLSI testing; digital and mixed analogue/digital techniques

primary J '^ ^ primary

inputs \ xC2 combinational
\n
logic
y, I—•

( X)
X
'

secondary storage
inputs (memory) secondary
elements outputs

Figure 3.14 The model for sequential logic netzvorks, where all combinational logic
gates are lumped into one half of the model and all memory elements are
lumped into the other half

(iv) Finally, a separate asynchronous reset (clear) may be applied to all

internal latches and flip-flops to reset them to the 0 0 0 ... 0 0 state, or
they may all be reset or set on the application of a specific input test
vector which the circuit designer has built into the circuit design.*
A discussion of the procedures (i) to (iii) above may be found in Rajsuman1
and in Lala2. It has been shown42 that for any machine containing s memory
(storage) elements and which therefore has 5, S< 25, states, the upper bound
on the length of a homing sequence is given by S(S- l)/2. This is a very
high, possibly prohibitively high, number as s increases, and hence current
design practice is to ensure that initialisation before test can be directly
accomplished by means of specific test input signal (s).
With the circuit initialised to a known starting state the primary outputs
may be checked for correctness, with appropriate primary test input vectors
if necessary. If this test fails, the circuit is faulty and no further testing need
be continued unless some diagnostic information is also sought. It has also
been suggested that the successful completion of a homing sequence,
particularly if a long sequence, is itself a good test for the complete circuit,
any deviation indicating some failure in the combinational or sequential
elements. However, it is difficult to determine the fault cover that a homing
test provides, and additional testing from the starting point of the initialised
circuit is usually required.
In spite of research and development activities20d it is here that viable
ATPG programs are not available, use of the stuck-at model becoming
difficult because of feedback complexities. Some efforts have been made to
partition the sequential circuit of Figure 3.14 into an interactive cascade of
one-state circuits21, effectively spreading out the synchronous machine
* This is a design for test feature, one of many such considerations which we will
consider in detail in Chapter 5.
 Digital test pattern generation 73

linearly in time instead of going around the one circuit model on each clock
pulse, but unfortunately this introduces the equally difficult problem of
having to model multiple stuck-at combinational faults. From the dates of the
references which we have cited it will be seen that there is very little new
reported work in this area; the only realistic way of continuing from the
initialisation stage is a functional approach, verifying the sequential circuit
operation by consideration of its state table or state diagram or ASM
(algorithmic state machine) chart, rather than by any computer modelling
and simulation technique 2>43.
This functional approach in turn becomes impractical as circuit size
increases to, say, 20 or more storage elements and possibly tens of thousands
of used and unused circuit states. For VLSI it is now imperative to consider
testing requirements at the circuit design stage, and build in appropriate
means of testing large sequential circuits more easily than would otherwise be
the case. This will be a major topic in Chapter 5; as will be seen partitioning,
re-configuration and other techniques may be introduced, giving both a
normal operating mode and a test mode for the complete circuit design.

3.4 Exhaustive, nonexhaustive and pseudorandom test pattern

generation

An ATPG program that produces a set of test vectors which detects all the
faults in a given fault list for a circuit has obvious advantages, since it provides
a minimum length test vector sequence to test the circuit to a known standard
of test. The difficulty and cost of generating this test set, which is a one-off
operation at the design stage, must be set against the resulting minimum
amount of data to be stored in the test system, see Figure 3.2c, and the
minimum time to test each production circuit.
In general, the order of generating and applying the test vectors in a system
such as in Figure 3.2c is fully flexible, the test vectors and expected (healthy)
output responses being stored in ROM. However, deterministic test pattern
generation based upon (usually) the stuck-at model does not generally
require any specific ordering of the test vectors, each test being independent
of the other tests. Unfortunately the difficulties of determining this test set for
complex VLSI circuits has become too great to undertake, and therefore
present test philosophies are moving away from the cost of ATP generation to
design for test strategies with the use of exhaustive, nonexhaustive or pseudo-
random test patterns. The cost of test pattern generation in the latter cases is
now usually some relatively simple hardware circuitry, such as we shall
consider below.

3.4.1 Exhaustive test pattern generators

If the circuit or system under test is sufficiently small or if it has been
appropriately partitioned into blocks which can be independently tested (see
74 VLSI testing: digital and mixed analogue/digital techniques

Chapter 5), then exhaustive testing applying every possible input

combination is conceptually and physically the easiest means of test. A basic
system such as that shown in Figure 3.15 would be appropriate. No ATPG
costs are involved, the only test design activity being the determination of the
healthy output responses to the test vectors.
The simplest hardware generator that can be used in this situation is a
normal binary counter, which with n stages produces the usual 2n output
vectors. Other binary counter arrangements, such as a Gray cyclic binary
counter, have little practical advantage over a simple binary counter, because
we are aiming for the full 2n possible output vectors.
The disadvantage of this simple exhaustive test pattern generation is
that the order of application of the test vectors is fixed. Also with a natural
binary sequence the most significant bit only changes from logic 0 to 1 once
in the complete 2n sequence. The questions that should be asked when
considering the use of a hardware binary counter test generator are
therefore:
(i) first of all, is it feasible to employ a fully exhaustive test set for the
circuit (or partition of the circuit) under test, or will this be too long a
test sequence?
(ii) is there any special circuit requirement which requires the test vectors
to be applied in some specific order?
(iii) does it matter if the frequency of changing from logic 0 to 1 of the
individual bits in the input test vector is dissimilar?
(iv) is there any special necessity to repeat short sequences of test vectors
within the total test40?
It may well be that one or more of these special considerations rules out the
use of a simple binary counter for a given circuit. However, in practice it is
usually preferable to use pseudorandom test vector hardware generation, as
will be considered in section 3.4.3 below, except perhaps for fairly trivial
applications of MSI complexity.

3.4.2 Nonexhaustive test pattern generators

The above fully-exhaustive test set would check all possible input/output
functional relationships of a combinational circuit* This test set would
undoubtedly toggle most of the internal nodes of the circuit more than once,
and hence it may be acceptable to use a nonexhaustive test pattern sequence
for the circuit test.
If BCD counters instead of normal binary counters are used, then the
reduction in input test vectors is as shown in Table 3.7. The hardware to
generate BCD coding is only marginally more complicated than a simple
binary counter, and hence there is little hardware penalty in this alternative.

* We are ignoring in our present discussions the peculiar problems of CMOS testing,
which will be considered further in Section 3.5.
 Digital test pattern generation 75

Table 3.7 The number of test vectors available from binary and BCD counters
No. of input bits No. of input test vectors
fully exhaustive binary binary-coded decimal

16 10 (I decade)
256 100 (2 decades)
n = 16 65536 10000 (4 decades)
4.3 x I0 9 I x I0 8 (8 decades)

However, there is not a very substantial saving in this alternative, and fault
coverage is now unknown. If some other subset of a full binary sequence is
considered then the greater the reduction in the number of test vectors the
lower the potential fault coverage. A more satisfactory nonexhaustive test set
strategy is that discussed in Section 3.2.1, where the circuit designer specifies
from his or her knowledge of the circuit a set of vectors which will exercise
the circuit with certain key or critical input/output functional requirements,
or alternatively will cause all or most of the internal gates to change state.
This procedure will produce a nonexhaustive set of test vectors. As covered
in Section 3.2.1, the effectiveness of this suggested test set may be
investigated by a computer check to determine how many of the internal
nodes of the circuit are toggled by this set of vectors; if this coverage is near
100 % then the probability of passing faulty circuits when under test will be
acceptably small.
The source of the test vectors for nonexhaustive tests such as above cannot
be made using simple hardware in the form of binary or BCD counters.
Instead we have to revert to supplying these vectors from a programmable
source such as ROM. This is back to the test set arrangement illustrated in
Figure 3.2^ rather than the simple hardware generation of Figure 3.15.
circuit or
network
under test
hardware
test pattern <\ | compantor
generator
/ healthy
/ response

input test vectors

Figure 3.15 Hardware test pattern generation, similar to the general cases shown in
Figure 3.2a and b. The input test sequence is usually exhaustive

3A3 Pseudorandom test pattern generators

By far the most common hardware generation is now one or other form of
pseudorandom test pattern generator. Such generators may be standalone
generators, as in Figure 3.16, or reconfigurations of flip-flops within the
circuit under test such that they become in-circuit pseudorandom test
generators when in test mode.
76 VLSI testing: digital and mixed analogue/digital techniques

pseudorandom circuit or
test pattern network output
generator under test check
/

/
input test vectors

Figure 3.16 Test generation using a pseudorandom test pattern generator. The
output check is often by signature analysis (see later) rather than by
comparison against a healthy response

We will be considering the place of pseudorandom generators extensively in

later chapters, particularly when considering signature analysis and built-in
self test. At this stage we will merely consider the theory and circuit
configurations involved, so that when we later use them in specific test
strategies we will have the necessary knowledge of their action. It is possible
to use a pseudorandom generator instead of a binary counter for simple
exhaustive testing as in Figure 3.15, but there is no fundamental advantage in
so doing compared with the use of a simple natural binary counter.
There are two principal forms of pseudorandom generators, namely:
(i) linear feedback shift registers, usually known as LFSRs;
(ii) one-dimensional linear cellular automata, usually known as CAs.
As will be seen, both have a basic shift register construction with exclusive-OR
gates to derive their particular output sequences. LFSRs are more generally
known and used than CAs, but the latter are becoming more widely
appreciated and researched. We will look at both in turn.

3.4.3.1 Linear feedback shift registers (LFSRs)

The principle of linear feedback shift registers is shown in Figure 3.17.
The LFSR is a normal shift register configuration, which when clocked
progresses its stored pattern of Os and Is from left to right, but which
has feedback exclusive-ORed from selected stages (taps) along the register
to form the serial input to the first stage.* When the feedback taps are appro-
priately chosen a n-stage LFSR will autonomously count in a pseudorandom
manner through 2n - 1 states before repeating its sequence; this is known as
a maximum length pseudorandom sequence, or M-sequence, and contains
all possible states of the register except for one forbidden state.

* The terminology linear is because the exclusive logic relationship realises the mod2
addition of binary values, which is a linear relationship that preserves the principle of
superposition. For example, (0 0 1 1 0 1 0 0 1 ) 0 0 0 1 0 = 1 0 0 0; 1 0 0 0 0 (0 0 1 1
0 1001) = 0 0 1 0 , and so on. No information is lost going throilgh an exclusive-OR
(or exclusive-NOR) gate.
 Digital test pattern generation 77

t ttM M ttM t l t t t
16-bit linear feedback shift register

12 16

Figure 3.17 The linear feedback shift register consisting of n D-type flip-flops in
cascade, with feedback arranged to generate a maximum length pseudo-
random sequence when clocked. Sixteen stages are indicated here, which
would give a maximum length sequence of216 - 1 = 65,535 states before
the sequence repeats. Alternative feedback connections to those shown
here are also possible, see Appendix A

Figure 3.18 gives a small example of a maximum length pseudorandom

sequence; for convenience only four stages are involved, giving a maximum
length sequence of 15. It will be noted that the all-zeros state of the counter
is absent, this being the forbidden state with this particular configuration as
may readily be seen by noting that when all Os are present in the register then
the feedback signal to the first stage is also 0. It therefore requires an
initialisation signal, a seed signal of ...1..., to initiate the pseudorandom
sequence. Many texts imply that the forbidden output of an M-sequence must
always be 0 0 0 ... 0, but this is only so if the LFSR outputs and the feedback
taps are taken from output Qand not Q of each flip-flop, that all shift register
interconnections are logically Q to D between consecutive stages, and that
exclusive-OR and not exclusive-NOR relationships are present in the
feedback circuits. For example, in Figure 3.18 if the second output had been
taken from Q2 instead of Q2> leaving the rest of the circuit unchanged, the
forbidden vector output would clearly then have been 0 10 0 instead of
0 0 0 0. However, 0 0 0 ... 0 0 is the normally encountered forbidden state,
and we will have no occasion to consider otherwise in the following
discussions.
If we analyse the vectors produced by an autonomous maximum length
LFSR generator, we can list the following properties:
(i) Starting from any nonforbidden state the LFSR generates 2n - 1 vectors
before the sequence is repeated—this is obvious because the period of
the M-sequence is 2n - 1.
(ii) In the complete M-sequence the number of Is in any bit differs
from the number of 0s by one, the Is appearing 2n~l times and the 0s
2n~1 - 1times—again,this is obvious from the period of the sequence.
78 VLSI testing: digital and mixed analogue/digital techniques

i
D Q D Q D Q D 0

clock -
P
>ck

-rr—'
0 o-

r -rQ
wk
Q
|
5

Figure 3.18 An example autonomous maximum length pseudorandom sequence

generator using four D-typeflip-flops.(Alternative taps are possible)
a circuit
b state table
c state diagram to emphasise the difference between the pseudo-
random sequence and a simple binary sequence
 Digital test pattern generation 79

Considering any one of the n bits and visualising its value written in a
continuous circle of 2n- 1 points, we may consider the runs of consecutive Os
and 1 in the sequence, the length of a run being the number of Os or Is in a
like-valued group. Then:
(iii) In the complete M-sequence there will be a total of 2n~l runs in each bit;
one half of the runs will have length 1, one quarter will have length 2,
one eighth will have length 3, and so on as long as the fractions 1/2,
1/4, 1/8, ... are integer numbers, plus one additional run of nls. In the
example of Figure 3.18 there are 23 = 8 runs, four of length 1, two of
length 2, one of length 3 plus one run of four Is in each bit.
(iv) From (iii), it follows that the number of transitions between 0 and 1 and
vice versa of each bit in a complete M-sequence is 2n~l.
(v) Every M-sequence has a cyclic shift and add property such that if the
given sequence is term-by-term added mod2 to a shifted copy of itself,
then a maximum length sequence results which is another shift of the
given sequence. For example, if the M-sequence shown in Figure 3.186
is added mod2 to the same sequence shifted up six places, it can easily
be shown that this results in the sequence which is a cyclic shift of eight
states from the given sequence.
(vi) Finally, if the autocorrelation of the M-sequence of Os and Is in each bit
is considered, that is knowing a particular entry has the value 0 (or 1)
how likely is any other entry in the same sequence to be 0 (or 1), we
have the autocorrelation function:

where I is the shift between the entries in the same sequence being
compared, l < T < 2 n - 2 , i.e. when T = l adjacent entries in the
sequence are being compared:
p=2n-l
and ax = 1 if the two entries being compared have the same value 0
or 1, = -1 if the two entries being compared have differing values.*
The value of C(T) for any M-sequence and any value of I is:

C(r)
v}
p
This may be illustrated by taking the Qi sequence in Figure 3.186 and
considering a shift of, say, three positions. This gives the results tabulated in

* We may express C{x) more explicitly than above using logic values of +1 and -1
instead of 0 and 1. This will be introduced in Chapter 4, but we have no need to do
so at the present.
80 VLSI testing: digital and mixed analogue/digital techniques

Table 3.8, with the total agreements and disagreements being 7 and 8
respectively, giving the autocorrelation value of-1/15.
It will also be appreciated that the shift register action between stages of a
LFSR means that all the n bits in the sequence have exactly the same
properties.

Table 3.8 The agreements/disagreements between an M-sequence and a shifted copy of

itself giving the autocorrelation value C(3) = (7- 8)/p - -1/15
Given M-sequence Shifted 3 posr (t = 3) Agreements (A) or disagreements (D)
1 A
1
1 ^ ^ -^ °\ D
A
1 - ^ 0 D
0 1 D
i i
I I A
0 0 A
1 0 D
1 1
1 1 A
0 0 A
0 0 A
1 0 D
0 1 D
0 1 D
0 1 D
Total: A = 7, D = 8

The maximum length of pseudorandom sequence is therefore seen to have

many interesting properties. The autocorrelation value has no specific
application in digital testing, but it is an indicator of the randomness of the
sequence. This is not a truly random sequence, however, since what the
sequence will be with a given circuit configuration is fully deterministic, and
it has a specific periodicity, but as we have seen it is more random in nature
than any normal binary or BCD counter. The designation pseudorandom
therefore is justified, and its ease of generation leads to its use in many
applications.
However, we have not yet considered how the taps on a shift register are
chosen so as to generate a maximum length sequence. Are only two taps as in
Figure 3.18 always sufficient, and where should they be connected? Is there
more than one possible choice for anyrc-stageLFSR? It may easily be shown
that a random choice of taps on a shift register will not always generate a
maximum length sequence—if we take a three-stage shift register and
exclusive-OR all three flip-flop outputs back to the serial input, four distinct
sequences can result, namely:
 Digital test pattern generation 81
• stuck, circulating all Os;
• stuck, circulating all Is;
• a sequence of 0 1 0, 1 0 1, repeat...;
• a sequence of 0 0 1, 1 0 0, 1 1 0, 0 1 1, repeat....
Clearly, a theory to determine the appropriate taps to give an M-sequence is
required.
The initial point to re-emphasise is that in the LFSR the serial input and
hence the next state of the register is fully deterministic, being a function of
the present state and of the exclusive-OR connections which are present. If
at time tj we know the 0 or 1 serial input signal, yif to the first flip-flop just
before the shift register is clocked, then at this time the output from the first
register will be the previous serial input y^j, the output from the second
flip-flop will be yt_2 and so on. This is shown in the general schematic of
Figure 3.19.
The value of the input bit, yj9 at any given time, ti9 is therefore the mod2
sum of the feedback taps, which may be expressed by the recurrence
relationship:

where yi9 ce{0, 1}.

Now from the theory originally developed for cyclic error detecting
codes44'45, any binary sequence of 0s and Is may be expressed by a
polynomial:
)= ... + amx

m
mx (3.18)
ro=0

where oP, x , x2 ... represent the positions in the bit sequence with increasing
l

time and ai are the binary coefficients, at-e{0, lj.For example, an

output sequence ... 1 1 1 0 0 1 with the first received bit on the right is given
by:
G(x} = lx° + Ox1 + Ox2 + I*3 + lx 4 + 5lx5

The algebraic manipulations of G(x) are all in the Galois field of GF(2), that
is mod2 addition, subtraction, multiplication and division of binary data.
Recall also that mod2 addition and subtraction are identical, being:
82 VLSI testing: digital and mixed analogue/digital techniques

i J L
= exclusive-OR = addition mod2
±
Figure 3.19 The general schematic of a LFSR with n stages, the taps cj, c2, c> ..., cn
being open (c{ = 0) if no connection is present, y^ is the input signal at
particular time fy

0 +0=0
0 + 1=1
1+0 = 1
1 + 1=0
0-1 =1
1-0 = 1
1-1=0
and hence polynomial multiplication and division follow as illustrated
below;*
(a? + x2 + x + 1) x (A? + x + 1) is given by:
x3 + x 2 + x + 1
x2 + x + 1
x3 + x 2 + x + 1
4 3 2
X + ^ + X +X
x5 + x4 + x3 + x2

* Note, as we are doing all the algebra here in GF(2), we use the conventional algebra
addition sign + rather than the logical exclusive-OR symbol ©. The latter symbol may
be found in some publications in this area, but not usually. Also, we will discontinue
the circle in the symbol I used in eqn. 3.17 from here on.
 Digital test pattern generation 83

since xl+ xl = 0. Similarly, (x5 + x? + x2 + I) + (x2 + x + 1 ) is given by:

x 3 + x2 + x + 1

* 4 + 0 + x2
4 3 2

* 3 +0 +0
x3 + x2 + x

x2 + x + 1
0

since x1' - x*' = 0. There is no remainder in this particular polynomial division,

and therefore x5 + x3 + x 2 + l i s said to be divisible by x2 + x + 1. Division of say
^ + x4 + x 2 + l b y x 3 + x +1 will be found to leave a remainder of x2.
Reverting to the autonomous LFSR circuit, each of the terms in the
polynomial expansion of eqn. 3.18 represents the value of the input bit yif
given by eqn. 3.17 at increasing time intervals (clock pulses). The first term
[
OQX° in eqn. 3.18 is the present value of yif the next term a1x is the next value
of yt and so on. The overall relationship is therefore as follows:
feedback taps

{0,1} aQx = y0 =
sequence = yx = cly0+c2y_l+c3y_2+.
G(x) with = y2 =
increasing
time

= clym_1+c2ym_2+c3ym_?i+...cnym_n

Hence the input signal, yit of eqn. 3.17 may now be replaced by ym, where m
denotes the increasing time of the sequence defined by eqn. 3.18.*
We may therefore rewrite eqn. 3.17 as:

-I'
n
(3.17a)

* Notice that the relationships shown above are in a matrix-like form. It is possible to
use matrix operations for this subject area, see Yarmolik21 for example, but we will not
do so in this text.
84 VLSI testing: digital and mixed analogue/digital techniques

Substituting for am in eqn. 3.18 now gives us:

This may be rearranged as follows:

^ | j ^ . * " ' +... + y_lX~l + G(X)J

This has rearranged the terms in the brackets { } into negative powers of x
(= past time), and positive powers of x (= present and future time), and has
eliminated the summation to infinity. Collecting together terms:

(3.20)

7=1

Because addition and subtraction are the same in GF(2), we may replace
the minus sign in the denominator of eqn. 3.20 with plus, giving the
denominator:

C
>*'' (3.21)

= l + cxx + c2x2+...+ cnxn (3.21a)

Hence the sequence G(x) is a function of:
(i) the initial conditions y_i, ^_ 2 ,..., y_n of the LFSR given by the numerator
in eqn. 3.20;
(ii) the feedback coefficients q, ^ , ..., cn in the denominator.
Notice that the denominator is independent of the initial conditions and only
involves the taps in the LFSR circuit, see Figure 3.19, Cj being 0 with the
feedback connection open (not present) and 1 with feedback connection
 Digital test pattern generation 85

closed (present). For the four-stage LFSR shown in Figure 3.18 the
denominator of G{x) would therefore be:
1 + xl + 0 + 0 + x4
= 1 + X1 + X4
This denominator which controls the sequence which the circuit generates
from a given initial condition is known as the characteristic polynomial P(x)
for the sequence; the powers of x in the characteristic polynomial are the
same as the stages in the shift register to which the feedback taps are
connected. Two further points may be noted, namely:
(i) if the initial conditions 31.1, y~2> • • •>y~n were all zero, then the numerator
of G(x) would be zero, and the sequence would be 0 0 0 ... irrespective
of the characteristic polynomial;
(ii) if the initial conditions were all zero except y__n which was 1, then the
numerator would become cn, which if cn = 1 gives:

G 3 2 2
() \ < )

Condition (i) above is a previously noted condition from a consideration of

the working of the LFSR. Condition (ii) is the example initialisation (seed)
signal used in Figure 3.186.
It is straightforward to perform the division in G(x) by hand, but in
practice it is rarely necessary to do so except as an academic exercise. The
simplest case to consider is eqn. 3.22. Taking the LFSR of Figure 3.18 with its
characteristic polynomial 1 + xl + x4, we have the never-ending division as
follows:
h*2 + x3 +x5 +x7+...

1 + tf + 0 + 0 + x4
[
+ 0 +• 0 + x 4
X
1 2
+ 0 + 0 + x5
x2 + 0 + x 4 + x 5
x2 (-0 + 0 + x6
, 4 ,
+ x6
3 7
x •0-t- 0 + x

x5 + x 6 + x 7
x 5 + x 6 + 0 + 0 + x9
x1 + 0 + x 9
86 VLSI testing: digital and mixed analogue/digital techniques

The generated sequence is therefore:

1 1 1 1 0 1 01...
which if continued will be found to be the sequence detailed in Figure 3.18b.
This pattern will start to repeat at xlb (the 16th bit) in the quotient, giving a
maximum length sequence of 2n- 1. If we had begun with a different set of
conditions for 3? then the same sequence would have been found but
displaced (cyclically shifted) from the above calculation. This GF(2) division
could of course equally be done by substituting 1 for each nonzero x*9
namely:
1 1 1 1 0 10 1...
1100 1)10000000...
See also and compare with the further development following, which involves
a similar GF(2) division with the same characteristic polynomial.
It has been shown that for the pseudorandom sequence to be the max-
imum length, the characteristic polynomial P(x) given by eqn. 3.21 must be a
primitive polynomial, that is it cannot be factorised into two (or more) parts.
For example (1 + xl + x3 + x5) may be factorised into (l + x1)(l + ^3 + x4),
remembering that we are operating in GF(2), but the polynomial (1 + ar2 + x?)
cannot be factorised. The latter but not the former, therefore, is a primitive
polynomial. Additionally, the primitive polynomial must divide without
remainder into the polynomial 1 + x2"'1, or putting it the other way around
the primitive polynomial must be a factor of 1 + 0? -1 , but not of 1 + x2"1
where t < n. For example, given the primitive polynomial 1 + xl + *?, which we
may write as 1 1 0 1, we have:

1110 1
1 1 0 ljl 0 0 0 0 0 0 1
110 1
10 10
110 1
1110
110 1
110 1
110 1
0
This may be further illustrated by evaluating the previous LFSR example of
Figure 3.18, dividing the primitive polynomial 1 + xl + x4 (1 1 0 0 1 ) into the
polynomial 1 + x15. The result of this division is the same as in the previous
worked example on page 85, except that we now have a 1 rather than a 0 in
the 16th position of the numerator, which causes the division to terminate
rather than continue onwards.
 Digital test pattern generation 87

All the primitive polynomials for any n are therefore prime factors of the
polynomial 1 + A2""1. Fortunately we do not have to calculate the primitive
polynomials for our own use, since they have been extensively calculated and
published. Appendix A at the end of this text gives the minimum primitive
polynomials for n< 100, together with further comments and references to
other published tabulations. The theory and developments of these poly-
nomial relationships may be found in MacWilliams and Sloane45, Brillhart
et a/.46, Bardell et a£47 and elsewhere, but some further comments may be
appropriate to include here.
First, as n increases the number of possible primitive polynomials increases
rapidly. The formula for this number may be found in the developments by
Golomb48 and listed in Bardell et al.Al, being for example 16 possibilities for
n = 8, 2048 possibilities for n = 16 and 276 480 possibilities for n = 24. Not all
are minimum, that is containing the fewest number of nonzero terms, but
even so there are alternative possibilities with the fewest number of terms for
n > 3. The listings given in Appendix A therefore are not the only
possibilities. A complete listing of all the possible primitive polynomials for
up to n =16 is given in Peterson and Weldon44.
Secondly, given any minimum primitive polynomial P(x) such as listed in
Appendix A, there is always the possibility of determining its reciprocal
polynomial P*(x), which is also a minimum primitive polynomial yielding a
maximum length sequence11'47'49. The reciprocal of the polynomial is
defined by:

| (3.23)

that is given, say,

which is the generating polynomial in Figure 3.18a, the reciprocal

polynomial is:

')-

This polynomial yields the maximum length sequence of

100110101111000
which may be confirmed by evaluating:
88 VLSI testing: digital and mixed analogue/digital techniques

and which will be seen to be the reverse of the sequence generated by

P(x) = 1 + x1 + x4. It is the property of every characteristic polynomial which
generates a maximum length sequence that its reciprocal will also generate a
maximum length sequence but in the reverse order with a cyclic shift. Hence,
there are always at least two characteristic polynomials with the fewest
number of terms for n = 3 upwards. (For n = 2, P(x) = 1 + xl + x2 = P*(x).) For
n- 15 there are six possible polynomials (including the reciprocals) which
have the minimum number of terms130, as listed in Table 3.9.

Table 3.9 The possible primitive polynomials for n = 15 with the least number of
nonzero terms (trinomials)
P(x) = 1 + x'+x 1 5 P|*(x) = 1 + X 1 4 H-x1
1
P2(x) = 1 4 - 4 4- 15 P2*(x) = 1 +X"H-x
8
P,(x) = 1 + X7 + X 15 P3*(x) = 1 +X +X 1 5

Finally, the LFSR circuit configuration that we have considered so far has the
feedback taps from the chosen LFSR stages all exclusive-ORed back to the
first stage. However, for any given circuit and characteristic polynomial, an
alternative circuit configuration with the same characteristic polynomial P(x)
and the same output sequence G(x), see eqn. 3.22, is possible by including the
exclusive-OR logic gates between appropriate LFSR stages. This is illustrated
in Figure 3.20. For each nonzero q in Figure 3.20a there is an effective
exclusive-OR gate between stages n - i and n-i+l in Figure 3.206; cn is
always nonzero, and therefore there is always a connection between Q^ and
the first stage as shown. For example, the equivalent of the LFSR circuit
shown in Figure 3.18 with the characteristic polynomial P(x)l + xl + x4 would
have one exclusive-OR gate between the third and final stages as shown in
Figure 3.20a
Notice that the same number of two-input exclusive-OR gates is necessary
in both possible circuit configurations, which we have termed type A and type
B in Figure 3.20. However, although the characteristic polynomial and hence
the output sequence of both type A and type B can be the same, the precise
n-bit data held in the n stages of the type A and type B LFSRs after each clock
pulse will not always be exactly the same. It is left as an exercise for the reader
to compile the state table for the type B LFSR with the characteristic poly-
nomial 1 + x1 + x4, and compare it with the state table given in Figure 3.186.
In general the type A LFSR of Figure 3.20 is preferable to the type B from
the manufacturing point of view, and most practical circuits show this
configuration. However, we will briefly come back to the type B in Section 4.5
of the following chapter, since it has a certain mathematical advantage when
the n-bit data in the LFSR rather than the 2 n - 1 pseudorandom output
sequence is of interest.
Further alternative circuit configurations have been investigated,
particularly the hybrid Wang-McCluskey circuits which seek to minimise the
number of exclusive-OR gates by a combination of the two circuit concepts
 Digital test pattern generation 89

D Q D Q D Q D Q

\ \

exclusive-OR feedback

Q. On

D Q OQ D Q
to— D Q

X"

D o D Q

Figure 3.20 Txvo alternative circuit configurations for the same maximum length
pseudorandom sequence generation
a type A LFSR, which is the circuit so far considered
b alternative type B circuit configuration
c type B realisation of the maximum length LFSR of Figure 3.18 with
the characteristic polynomial P(x) = 1 + xl + x4. Note, other
publications may refer to these two configurations as type 1 and type
2 LFSRs, but regretably there is a lack of consistancy whether a is type
1 and b is type 2, or vice versa

shown in Figure 3.2051. We will not pursue these and other alternatives such
as partitioning a LFSR into smaller autonomous LFSRs, particularly as the
cellular automata (CA) pseudorandom generators which we will introduce
below have theoretical advantages over LFSR generators. Further reading
may be found in References 11, 13, 44, 47 and 50.
90 VLSI testing: digital and mixed analogue/digital techniques

3.4.3.2 Cellular automata (CAs)

Turning from LFSRs to autonomous cellular automata, again the basic circuit
configuration is a shift register but now the connection between stages always
involves some linear (exclusive-OR) relationship. The regular shift of 0s and
Is along the register, as illustrated in Figure 3.18b therefore is not present.
The GA circuits which have been developed to produce a maximum length
pseudorandom sequence of 2 n - 1 states from an w-stage register have the D
input of each stage controlled by a linear relationship of the Q outputs of
adjacent (near-neighbour) states. For example, input Dk of stage Q^ may
involve the outputs Qk_x, Qk and Qk+li but no other global connection(s).
The two functions J{Dk) which are found to be relevant are as follows:

0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0

Reading these two exclusive-OR functions as eight-bit binary numbers

with the top entry as the least significant digit, the function Qk_i © Qk+i
is termed function 90, and the function Q/^\ © (^© Q&+iis termed function
150, a terminology first introduced by Wolfram52. This gives us the two basic
circuit blocks (cells) shown in Figure 3.21 from which autonomous maximum
length n-stage CAs may be constructed.*
Originally, research work, largely in Canada by Hortensius, McLeod, Card
and others53"56, demonstrated that appropriate strings of 90 and 150 cells
can produce maximum length pseudorandom sequences. The initial work of
the early 1980s involved extensive computer simulations of different strings
of 90 and 150 cells to determine the resulting sequences; it was found that
90 or 150 cells alone cannot produce an M-sequence. For small n a string of
90, 150, 90, 150, ..., 90, 150 was found to be successful, but in this early work
no theory was yet developed to determine the arrangements of 90/150
circuits for maximum length generation. Further research has solved this
problem (see later), and has also considered using the minimum number of

* Other functions of Q^\, Qk and Q^+1 have been investigated57'58, but it has now
been formally proved that only the 90 and 150 functions are appropriate to generate
maximum length sequences. We will, therefore, only consider the 90 and 150
functions in this text.
 Digital test pattern generation 91

Q,

clock clock

Figure 3.21 Two basic cells from which maximum length pseudorandom CA
generators may be built
a type 90 cell
b type 150 cell

150 cells, the more expensive cell of the two, and maximising the use of the
90 cell. It has been shown59 that for n<150 at most two 150 cells are
required, the remainder all being 90 cells. The list for n< 150 is given in
Appendix B.
The circuit and resulting M-sequence for a four-stage autonomous CA
generator with alternating 90 and 150 cells is given in Figure 3.22. As will be
seen, the resulting maximum length sequence does not have the simple shift
characteristic of the LFSR generator, but instead has a much more random-
like relationship between the successive output vectors Qj Q2 Q3 ^4- A
forbidden state of 0 0 0 0 is present as in an autonomous LFSR generator,
necessitating a seed of ...1... to be present to allow the M-sequence to
proceed. The circuit for n = 4 using the data tabulated in Appendix B would
be similar to Figure 3.22 but with the 90 and 150 cells interchanged—there is
always a choice of circuit configurations for n > 2.
The analysis of the sequence generated by a given CA may easily be found
by a matrix computation, where all multiplications and additions are in
GF(2). For example, consider the string of 90 and 150 cells shown in Figure
3.23; then the state transition matrix [T] is given by:

0 1 0 0 0 0 0 0
1 1 1 0 0 0 0 0
0 1 0 1 0 0 0 0
0 0 1 1 1 0 0 0
0 0 0 10 10 0
0 0 0 0 1 1 1 0
0 0 0 0 0 10 1
0 0 0 0 0 0 11
92 VLSI testing: digital and mixed analogue/digital techniques

Q3
*ir

D Q i! D Q D 0 D 0
i!
>ck i! >ck >ck >ck
i!
Q o ! Q o- ! 0
j
90 || 150 90 150 j

jl J Jl .J
Q2 Q^ Q3 Q4 Q3—' '—0

o2 QA

Q^ Q2 Q3 QA
initialisation
1 0 0 0 (seed) before first
clock pulse
clock pulse 1 0 1 0 0
2 1 1 1 0
3 1 1 1 1
4 1 1 0 0
5 1 0 1 0
6 0 0 0 1
7 0 0 1 1
8 0 1 1 0
9 1 0 1 1
10 0 0 1 0
11 0 1 0 1
12 1 1 0 1
13 1 0 0 1
14 0 1 1 1
15 1 0 0 0
sequence
0 1 0 0 \ repeats

Figure 3.22 An autonomous four-stage maximum length CA generator

a circuit
b the resulting sequence, cf. Figure 3.186

This is a tridiagonal matrix, that is all zeros except on three diagonals, the
diagonal row entries being 1 1 1 for internal 150 cells and 1 0 1 for internal
90 cells. For any present-state output vector Q), the next-state output vector
(£"] of the CA is given by:
[T]Q]=Q + ] (3.24)
 Digital test pattern generation 93

90 150 90 150 90 150 90 150

• i

Figure 3.23 Schematic of a string of 90/150 CA cells

For example, taking the eighth vector in Figure 3.226, namely 0 110, the
next-state vector for this CA is given by:
0 1 0 0 0 0+1+0+0 1
1 1 1 0 1 0+1+1+0 0
0 1 0 1 1 0+1+0+0 " l
0 0 1 1 0 0+0+1+0 1
[T] Q]
The following vector may be obtained by the transformation of 1 0 1 1, or by
transforming the previous vector 0 1 1 0 by [T]2, that is:
0 10 0 0 100 1110
1110 1 1 10 1111
0 10 1 0 10 1 110 1
00 11 00 11 0 110
[T] [T] [T] 2
In general, the kth vector Q+fi] after any given vector may be obtained by:
Q+*] (3.25)
where [T] is the given state transition matrix.
There is, therefore, relatively little difficulty in the analysis of a given
cellular automaton.* The theory for the synthesis of a maximum length CA,
however, is much more difficult; unlike the LFSR where polynomial division
over GF(2) is involved, for the CA no polynomial operations are directly
applicable and generally unfamiliar matrix operations are deeply involved.
It has been shown by Serra et a/.61"63 that autonomous LFSRs and CAs are
isomorphic to each other, so that given any maximum length LFSR a
corresponding maximum length CA may be determined; more precisely,
given any characteristic polynomial for a LFSR a corresponding CA may be

* We could of course have performed a similar matrix operation to determine the

next state of a LSFR; the state transition matrix of Figure 3.20a would be a tridiagonal
of 1 0 0 except for the first row which must represent the generating polynomial13.
However, the polynomial division that we have covered is generally quicker and gives
the full sequence of each LFSR output.
94 VLSI testing: digital and mixed analogue/digital techniques

found. In this context corresponding does not imply the same output
sequence, but a reordered output sequence of the same length. The
procedure involves three principal steps namely:
(i) compile the state transition matrix of the chosen LFSR generator;
(ii) determine the companion matrix64 of this state transition matrix using
similarity transformations, the former being a matrix which is
isomorphic to the transition matrix;
(iii) tridiagonalise the companion matrix into a tridiagonal form, this being
undertaken by a development of the Lanczos tridiagonalisation
algorithm64.
The last step generates the state transition matrix for the corresponding
cellular automaton, which as we have seen must be in tridiagonal form
because all interconnections involve only Q^lt Q^ and Q^+1 signals. Further
details may be found in Serra et al, particularly in References 61-63. Note,
the type 1 and type 2 LFSRs in Serra is what we have termed type B and type
A LFSRs, respectively.
However, this method of developing a maximum length autonomous
pseudorandom CA generator is found to produce far from minimum GA
assemblies, that is with the fewest number of the more expensive 150 cells,
even when developed from minimum length primitive polynomials. No
relationship exists between minimal LFSRs and minimal CAs, and hence the
search for minimal cost CA realisations has been undertaken by a search
procedure based upon the tridiagonal characteristics of the CA state
transition matrix.
Looking back at the example state transition matrix of Figure 3.23 it will be
seen that the main diagonal has the value 0 for a type 90 cell, and 1 for a type
150 cell; the two adjacent side diagonals are always all Is. Also, if the
transition matrix for any n produces the maximum length sequence of 2n - 1
states, then [T] k will yield the identity matrix [I] for k = 2", but will not yield
[I] for any k < 2n. This is so because the maximum length sequence repeats
after 2n - 1 different states to its starting state. The search procedure to
identify the smallest number of type 150 cells for a maximum length
sequence is therefore to set all the main diagonal entries initially to zero, and
then progressive insert one 1, two Is, ... in the main diagonal. The search is
stopped for any given n when [T]2"= [I]. Further details may be found in
Reference 59. This procedure has, as previously noted, shown that only two
type 150 cells are necessary for n < 150, see details in Appendix B.
Looking at the autonomous LFSR circuits and the CA circuits which we
have now examined, it will be appreciated that either could be used as a
standalone hardware generator for supplying pseudorandom test vectors50'57.
The total circuit requirements of a CA generator are more complex than that
of a LFSR generator, since more exclusive-OR gates are required, but no
interconnections running the full length of the shift register are ever
required in the CA case as is always necessary in a LFSR generator. This may
 Digital test pattern generation 95

be advantageous in an integrated circuit layout. Also the test vector sequence

produced by a CA generator has been shown to be more random in nature
than that produced by a LFSR, having preferable testing properties. Indeed,
as will be seen in the following section covering CMOS testing, the
pseudorandom sequence produced by a LFSR generator fails to provide a test
for certain CMOS conditions, whereas the CA generator will provide such a
test.
However, the main present and future use of both LFSR and CA generators
is not generally as standalone autonomous sources of pseudorandom test
vectors. Instead both are intimately involved in built-in test methods for
digital circuits. In particular the LFSR circuit will be encountered in the built-
in logic block observation (BILBO) methodology for the self test of VLSI
circuits, and the CA circuit will be found in the corresponding cellular
automata logic block observation (CALBO) test methodology (see Chapter
5). The LFSR circuit will also be encountered when considering signature
analysis in the following chapter. Having, therefore, now covered both means
of pseudorandom generation, we will be able to appreciate their action when
considering their utilisation in later pages.

3.5 IDDQ and CMOS testing

The problem of CMOS testing with its dual p-channel and n-channel FET
configurations was introduced in the preceding chapter. Functional testing
and IDDQ current tests were seen to be the most appropriate rather than test
pattern generation based upon, say, the stuck-at fault model.
To cover open-circuit and short-circuit faults in a CMOS circuit we have
seen that:
(i) for any open-circuit fault it is necessary to apply a specific pair of test
vectors, the first being an initialisation vector to establish a logic 0(1) at
the gate output, the second being the test vector which checks that the
output will then switch to 1 (0);
(ii) for any short-circuit fault then on some test vectors there will be a
conducting path from VDD to ground through the gate, which may be
detected by monitoring the supply current IDD under quiescent (non-
transitory) conductions, this being the //w> measurement.
The latter feature is illustrated by Figure 3.24.
Let us consider first the functional tests for open-circuit faults. Table 2.3
in Chapter 2 illustrated the exhaustive test set for a simple two-input
CMOS NAND gate; the pair of input test vectors 0 1,11 checked for
transistor T3 or T4 open circuit, the pair 11,10 checked for T2 open circuit
and the pair 1 1 , 0 1 checked for Tl open circuit. The mathematics for
determining an appropriate test vector sequence was not, however,
considered.
VLSI
The importance of testing
integrated circuits (ICs) has
escalated with the increasing
complexity of circuits fabricated
TESTING on a single IC chip. No longer
is it possible to design a new IC
digital and mixed and then think about testing:
such considerations must be
analogue/digital part of the initial design activity,
techniques and testing strategies should be
part of every circuit and system
designer’s education. This book is a comprehensive
introduction and reference for all aspects of IC testing.
It includes all of the basic concepts and theories
necessary for advanced students, from practical test
strategies and industrial practice, to the economic and
managerial aspects of testing. In addition to detailed
coverage of digital network testing, VLSI testing also
considers in depth the growing area of testing analogue
and mixed analogue/digital ICs, used particularly in
signal processing.

Stanley L Hurst began his industrial career with

Westing house Brake and Signal Company before
leaving for academia in the 1960s. Initially with the Bristol
College of Science and Technology and subsequently
with the University of Bath, he specialised in digital
electronic teaching and research, particularly in custom
microelectronics and testing. In 1985 he was recruited
by the Open University to produce educational material
on these subjects for industry and continuing education
courses. He is currently Academic Editor, Circuits and
Systems, of the Microelectronics Journal. He holds the
MSc(Eng) and PhD from the University of London, the
DSc from the University of Bath, and is the author of
some 50 papers and eight books in his subject area.

The Institution of Electrical Engineers

Cover illustration courtesy of VLSI Technology, Inc.

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ISBN 0 85296 901 5
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ISBN 978-0-852-96901-5