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 20CS301 DIGITAL
PRINCIPLES AND
SYSTEM DESIGN
Department: COMPUTER SCIENCE AND ENGINEERING
Batch/Year: BATCH 2020-24/II
Created by:
Dr. S Selvi , Professor, CSE, RMKEC
Ms. K Elavarasi , AP, CSE, RMKEC

Date: 28th October 2021

Syllabus
20CS301 DIGITAL PRINCIPLES AND SYSTEM DESIGN

UNIT V MEMORY AND PROGRAMMABLE LOGIC 15

RAM – Memory Decoding – Error Detection and Correction - ROM - Programmable
Logic Array – Programmable Array Logic – Sequential Programmable Devices.
Lecture Plan
Unit V
Lecture Plan – Unit 5 – MEMORY AND
PROGRAMMABLE LOGIC
Sl. Topic Numbe Proposed Actual CO Taxo Mode
No r of Date Lecture nomy of
. Period Date Level Deliver
s y
1 RAM – CO5 K4 PPT /
Memory Online
Decoding Lecture

2 Error CO5 K4 PPT /

Detection Online
and Lecture
Correction
3 ROM - CO5 K4 PPT /
Programma Online
ble Logic Lecture
Array –
Programma
ble Array
Logic
4 Sequential CO5 K4 PPT /
Programma Online
ble Devices Lecture
Activity Based Learning
Unit V
Activity Based Learning
Sl. No. Contents Page No.

1 Online Quiz 50
Lecture Notes – Unit V
UNIT V
MEMORY AND PROGRAMMABLE LOGIC
Sl. No. Contents Page No.
Introduction to Memory
1 12
Read / Write Operations
2 16
Classification of Memory – Types of Memory
3 18
Memory Decoding
Internal construction of RAM
4 33
Coincident Decoding
Address Multiplexing
Error Detection and Correction
5 Parity Bit 41
Hamming Code
ROM
Combinational PLD’s
6 - Programmable ROM (PROM) 50
- Programmable Logic Array (PLA)
- Programmable Array Logic (PAL)
Sequential Programmable Devices.
7 59
Introduction to Memory

• A memory unit is a collection of storage cells with associated circuits needed to

transfer information in and out of the device.

• The binary information is transferred for storage and from which information is
available when needed for processing.

• When data processing takes place, information from the memory is transferred to
selected registers in the processing unit. Intermediate and final results obtained
in the processing unit are transferred back to be stored in memory.

Units of Binary Data: Bits, Bytes, Nibbles and Words

• As a rule, memories store data in units that have from one to eight bits. The
smallest unit of binary data is the bit. In many applications, data are handled in
an 8- bit unit called a byte or in multiples of 8-bit units.

• The byte can be split into two 4-bit units that are called nibbles. A complete unit
of information is called a word and generally consists of one or more bytes.
Some memories store data in 9-bit groups; a 9-bit group consists of a byte plus a
parity bit.

Basic Semiconductor Memory Array

• Each storage element in a memory can retain either a 1 or a 0 and is called a

cell. Memories are made up of arrays of cells, as illustrated in Figure below using
64 cells as an example. Each block in the memory array represents one storage
cell, and its location can be identified by specifying a row and a column.
Introduction to Memory

A 64-cell memory array organized in three different ways

Memory Address and Capacity

• The location of a unit of data in a memory array is called its address. For
example, in Figure (a), the address of a bit in the 3-dimensional array is specified
by the row and column.

• In Figure (b), the address of a byte is specified only by the row in the 2-
dimensional array. So, as you can see, the address depends on how the memory
is organized into units of data. Personal computers have random-access memories
organized in bytes. This means that the smallest group of bits that can be
addressed is eight.
Introduction to Memory

Examples of memory address

• The capacity of a memory is the total number of data units that can be stored.
For example, in the bit-organized memory array in Figure (a), the capacity is 64
bits. In the byte-organized memory array in Figure (b), the capacity is 8 bytes,
which is also 64 bits. Computer memories typically have 256 MB (megabyte) or
more of internal memory.

Basic Memory Operations

• Since a memory stores binary data, data must be put into the memory and data
must be copied from the memory when needed.

• The write operation puts data into a specified address in the memory, and the
read operation copies data out of a specified address in the memory.

• The addressing operation, which is part of both the write and the read operations,
selects the specified memory address.
Introduction to Memory

• Data units go into the memory during a write operation and come out of the
memory during a read operation on a set of lines called the data bus. As indicated
in Figure, the data bus is bidirectional, which means that data can go in either
directional (into the memory or out of the memory).

Block diagram of memory operation

• For a write or a read operation, an address is selected by placing a

binary code representing the desired address on a set of lines called the
address bus.

• The address code is decoded internally and the appropriate address is

selected. The number of lines in the address bus depends on the
capacity of the memory.

• For example, a 15- bit address code can select 32,768 locations (215)
in the memory; a 16-bit address code can select 65,536 locations (216)
in the memory and so on.

• In personal computers a 32-bit address bus can select 4,294,967,296

locations (232), expressed as 4GB.
Introduction to Memory

Write Operation

• To store a byte of data in the memory, a code held in the address register is
placed on the address bus. Once the address code is on the bus, the address
decoder decodes the address and selects the specified location in the memory.

• The memory then gets a write command, and the data byte held in the data
register is placed on the data bus and stored in the selected memory address,
thus completing the write operation.

• When a new data byte is written into a memory address, the current data byte
stored at that address is overwritten (replaced with a new data byte).

Illustration of the Write operation

Introduction to Memory

Read Operation

• A code held in the address register is placed on the address bus. Once the
address code is on the bus, the address decoder decodes the address and
selects the specified location in the memory.

• The memory then gets a read command, and a "copy" of the data byte that
is stored in the selected memory address is placed on the data bus and
loaded into the data register, thus completing the read operation.

• When a data byte is read from a memory address, it also remains stored at

that address. This is called nondestructive read.

Illustration of the Read operation

Introduction to Memory

Classification of Memories

There are two types of memories that are used in digital systems:

• Random-Access Memory (RAM),

• Read-Only Memory (ROM).

• RAM (random-access memory) is a type of memory in which all addresses

are accessible in an equal amount of time and can be selected in any order
for a read or write operation.

• All RAMs have both read and write capability. Because RAMs lose stored data
when the power is turned off, they are volatile memories.

• ROM (read-only memory) is a type of memory in which data are stored

permanently or semi permanently. Data can be read from a ROM, but there is no
write operation as in the RAM.

• The ROM, like the RAM, is a random-access memory but the term RAM
traditionally means a random-access read/write memory. Because ROMs retain
stored data even if power is turned off, they are nonvolatile memories.

Classification of memories
Introduction to Memory

RANDOM-ACCESS MEMORIES (RAMS)

• RAMs are read/write memories in which data can be written into or read from
any selected address in any sequence.

• When a data unit is written into a given address in the RAM, the data unit
previously stored at that address is replaced by the new data unit.

• When a data unit is read from a given address in the RAM, the data unit
remains stored and is not erased by the read operation.

• This nondestructive read operation can be viewed as copying the content of

an address while leaving the content intact.

• A RAM is typically used for short-term data storage because it cannot retain
stored data when power is turned off.

• The two categories of RAM are the static RAM (SRAM) and the dynamic RAM
(DRAM).

• Static RAMs generally use flip-flops as storage elements and can therefore store
data indefinitely as long as dc power is applied. Dynamic RAMs use capacitors as
storage elements and cannot retain data very long without the capacitors being
recharged by a process called refreshing.

• Both SRAMs and DRAMs will lose stored data when dc power is removed and,
therefore, are classified as volatile memories.

• Data can be read much faster from SRAMs than from DRAMs. However, DRAMs
can store much more data than SRAMs for a given physical size and cost because
the DRAM cell is much simpler, and more cells can be crammed into a given chip
area than in the SRAM.
Introduction to Memory

Static RAM (SRAM)

Storage Cell:
• All static RAMs are characterized by flip-flop memory cells. As long as dc power is
applied to a static memory cell, it can retain a 1 or 0 state indefinitely. If power is
removed, the stored data bit is lost.

• The cell is selected by an active level on the Select line and a data bit (l or 0) is
written into the cell by placing it on the Data in line. A data bit is read by taking it
off the Data out line.

Basic SRAM Organization:

• The memory cells in a SRAM are organized in rows and columns. All the cells
in a row share the same Row Select line.

• Each set of Data in and Data out lines go to each cell in a given column and
are connected to a single data line that serves as both an input and output
(Data I/O) through the data input and data output buffers.

• SRAM chips can be organized in single bits, nibbles (4 bits), bytes (8 bits), or
multiple bytes (16, 24, 32 bits, etc.).

• The memory cell array is arranged in 256 rows and 128 columns, each with 8 bits
as shown below. There are actually 215 = 32,768 addresses and each address
contains 8 bits. The capacity of this example memory is 32,768 bytes (typically
expressed as 32 kbytes).
Introduction to Memory

Memory array configuration

Operation:

• The SRAM works as follows. First, the chip select, CS, must be LOW for the
memory to operate. Eight of the fifteen address lines are decoded by the row
decoder to select one of the 256 rows. Seven of the fifteen address lines are
decoded by the column decoder to select one of the 128 8-bit columns.

Memory block diagram

Introduction to Memory

Read:

• In the READ mode, the write enable input, WE‘ is HIGH and the output
enable, OE‗ is LOW.

• The input tristate buffers are disabled by gate G1, and the column output
tristate buffers are enabled by gate G2. Therefore, the eight data bits from
the selected address are routed through the column I/O to the data lines
(I/O1 through I/O7), which are acting as data output lines.

Write:

• In the WRITE mode, WE‘ is LOW and OE‘ is HIGH. The input buffers are
enabled by gate G1, and the output buffers are disabled by gate G2.

• Therefore the eight input data bits on the data lines are routed through the
input data control and the column I/O to the selected address and stored.

Read and Write Cycles

• For the read cycle shown in part (a), a valid address code is applied to the
address lines for a specified time interval called the read cycle time, tWC.

• Next, the chip select (CS) and the output enable (DE) inputs go LOW. One-
time interval after the DE input goes LOW; a valid data byte from the
selected address appears on the data lines. This time interval is called the
output enable access time, tGQ.

• Two other access times for the read cycle are the address access time,
tAQ, measured from the beginning of a valid address to the appearance of
valid data on the data lines and the chip enable access time, tEQ,
measured from the HIGH-to-LOW transition of CS to the appearance of valid
data on the data lines.
Introduction to Memory

• During each read cycle, one unit of data, a byte in this case is read from the

memory.

• For the write cycle shown in Figure (b), a valid address code is applied to the

address lines for a specified time interval called the write cycle time, tWE .

Next, the chip select (CS) and the write enable (WE) in puts go LOW.

• The required time interval from the beginning of a valid address until the WE

input goes LOW is called the address setup time, t s(A).

• The time that the WE input must be LOW is the write pulse width. The time

that the input WE must remain LOW after valid data are applied to the data

inputs is designated t WD; the time that the valid input data must remain on

the data lines after the WE input goes HIGH is the data hold time, t h(D).

• During each write cycle, one unit of data is written into the memory.
Introduction to Memory

Dynamic RAM (DRAM)

• Dynamic memory cells store a data bit in the form of electric charges on
capacitors. The basic storage device in DRAM is not a flip-flop but a simple
MOSFET and a capacitor.

• The advantage of this type of cell is that it is very simple, thus allowing very large
memory arrays to be constructed on a chip at a lower cost per bit.

• The advantage of this type of cell is that it is very simple, thus allowing very large
memory arrays to be constructed on a chip at a lower cost per bit.

• The disadvantage is that the storage capacitor cannot hold its charge over an
extended period of time and will lose the stored data bit unless its charge is
refreshed periodically.

• To refresh requires additional memory circuitry and complicates the operation of

the DRAM.

• In DRAM memory cell, a bit of data is stored as charge on storage capacitor,

where the presence or absence of charge determines the value of the stored bit 1
or 0.

• The DRAM cell includes a single MOS transistor (MOSFET) and a capacitor. When
column line and row line go high, the MOSFET conducts and charges the
capacitor. When the column and row lines go low, the MOSFET opens and the
capacitor retains its charge. In this way it stores 1 bit.

DRAM memory cell

Introduction to Memory

READ- ONLY MEMORIES (ROMS)

• A ROM contains permanently or semi-permanently stored data, which can be read

from the memory but either cannot be changed at all or cannot be changed without
specialization equipment.

• A ROM stores data that are used repeatedly in system applications, such as tables,
conversions, or programmed instructions for system initialization and operation.
ROMs retain stored data when the power is OFF and are therefore nonvolatile
memories.

• The ROMs are classified as follows:

i. Masked ROM (ROM)

ii. Programmed ROM (PROM)
iii. Erasable PROM (EPROM)
iv. Electrically Erasable PROM (EEPROM)

Masked ROM

• The mask ROM is usually referred to simply as a ROM. It is permanently

programmed during the manufacturing process to provide widely used
standard functions, such as popular conversions, or to provide user-specified
functions. Once the memory is programmed, it cannot be changed.

• Most IC ROMs utilize the presence or absence of a transistor connection at a

row/column junction to represent a 1 or a 0. The presence of a connection
from a row line to the gate of a transistor represents a 1 at that location
because when the row line is taken HIGH; all transistors with a gate
connection to that row line turn on and connect the HIGH (1) to the
associated column lines.

• At row/column junctions where there are no gate connections, the column

lines remain LOW (0) when the row is addressed.
Introduction to Memory

PROM (Programmable Read-Only Memory)

• The PROM (Programmable Read-only memory), comes from the

manufacturer unprogrammed and are custom programmed in the field to
meet the user‘s needs.

• A PROM uses some type of fusing process to store bits, in which a memory
link is burned open or left intact to represent a 0 or a 1.

• The fusing process is irreversible; once a PROM is programmed, it cannot be

changed.

EPROM (Erasable Programmable ROM)

• An EPROM is an erasable PROM. Unlike an ordinary PROM, an EPROM can be

reprogrammed if an existing program in the memory array is erased first.

• An EPROM uses an NMOSFET array with an isolated-gate structure. The

isolated transistor gate has no electrical connections and can store an
electrical charge for indefinite periods of time. The data bits in this type of
array are represented by the presence or absence of a stored gate charge.
Erasure of a data bit is a process that removes the gate charge.

• Two basic types of erasable PROMs are the ultraviolet erasable PROM (UV
EPROM) and the electrically erasable PROM (EEPROM).
EEPROM (Electrically Erasable PROM)

• The EEPROM (Electrically Erasable PROM), also uses MOS circuitry.

Data is stored as charge or no charge on an insulating layer, which is
made very thin (< 200Å). Therefore a voltage as low as 20- 25V can be
used to move charges across the thin barrier in either direction for
programming or erasing ROM.
Introduction to Memory

PROM (Programmable Read-Only Memory)

• The PROM (Programmable Read-only memory), comes from the

manufacturer unprogrammed and are custom programmed in the field to
meet the user‘s needs.

• A PROM uses some type of fusing process to store bits, in which a memory
link is burned open or left intact to represent a 0 or a 1.

• The fusing process is irreversible; once a PROM is programmed, it cannot be

changed.

EPROM (Erasable Programmable ROM)

• An EPROM is an erasable PROM. Unlike an ordinary PROM, an EPROM can be

reprogrammed if an existing program in the memory array is erased first.

• An EPROM uses an NMOSFET array with an isolated-gate structure. The

isolated transistor gate has no electrical connections and can store an
electrical charge for indefinite periods of time. The data bits in this type of
array are represented by the presence or absence of a stored gate charge.
Erasure of a data bit is a process that removes the gate charge.

• Two basic types of erasable PROMs are the ultraviolet erasable PROM (UV
EPROM) and the electrically erasable PROM (EEPROM).
EEPROM (Electrically Erasable PROM)

• The EEPROM (Electrically Erasable PROM), also uses MOS circuitry. Data is
stored as charge or no charge on an insulating layer, which is made very thin
(< 200Å). Therefore a voltage as low as 20- 25V can be used to move
charges across the thin barrier in either direction for programming or erasing
ROM.
Introduction to Memory

• An electrically erasable PROM can be both erased and programmed with

electrical pulses. Since it can be both electrically written into and electrically
erased, the EEPROM can be rapidly programmed and erased in-circuit for
reprogramming.

• It allows selective erasing at the register level rather than erasing all the
information, since the information can be changed by using electrical signals.

• It has chip erase mode by which the entire chip can be erased in 10 msec.
Hence EEPROM‘s are most expensive.
• Advantages of RAM:
1. Fast operating speed (< 150 nsec),
2. Low power dissipation (< 1mW),
3. Economy,
4. Compatibility,
5. Non-destructive read-out.
• Advantages of ROM:
1. Ease and speed of design,
2. Faster than MSI devices (PLD and FPGA)

3. The program that generates the ROM contents can easily be

structured to handle unusual or undefined cases,
4. A ROM‘s function is easily modified just by changing the stored
pattern, usually without changing any external connections,
5. More economical.

• Disadvantages of ROM:

• For functions more than 20 inputs, a ROM based circuit is impractical because of
the limit on ROM sizes that are available.

• For simple to moderately complex functions, ROM based circuit may be costly:
consume more power; run slower.
Introduction to Memory

Comparison between RAM and ROM

S.No RAM ROM
1 RAMs have both read and write ROMs have only read operation.

capability.
2 RAMs are volatile memories. ROMs are non-volatile memories.
3 They lose stored data when the They retain stored data even if power is
power is turned OFF. turned off.
4 RAMs are available in both RAMs are available in both bipolar and
bipolar and MOS technologies. MOS technologies.
5 Types: SRAM, DRAM, EEPROM Types: PROM, EPROM.

Comparison of SRAM and DRAM

S.No Static RAM Dynamic RAM

1 It contains less memory cells It contains more memory cells per unit area.
per unit area.
2 Its access time is less, hence Its access time is greater than static RAM
faster memories.
3 It consists of number of flip- It stores the data as a charge on the capacitor.
flops. Each It consists of MOSFET and capacitor for each
flip-flop cell.

stores
one bit.
4 Refreshing circuitry is Refreshing circuitry is required to maintain
not required. the charge on the capacitors every time after
every few milliseconds. Extra hardware is
required to control refreshing.

5 Cost is more Cost is less.

Introduction to Memory

Comparison of Types of Memories

Memory Non- Volatile High Density One- Transistor In-system

type cell writability

SRAM No No No Yes
DRAM No Yes Yes Yes
ROM Yes Yes Yes No
EPROM Yes Yes Yes No
EEPROM Yes No No Yes

Memory Decoding

• In addition to requiring storage components in a memory unit, there is a need for

decoding circuits to select the memory word specified by the input address.

• In this section, we present the internal construction of a RAM and demonstrate

the operation of the decoder.

• To be able to include the entire memory in one diagram, the memory unit
presented here has a small capacity of 16 bits, arranged in four words of 4 bits
each.

• An example of a two‐dimensional coincident decoding arrangement is presented

to show a more efficient decoding scheme that is used in large memories.

Internal Construction

• The internal construction of a RAM of m words and n bits per word consists of
m * n binary storage cells and associated decoding circuits for selecting individual
words.
Introduction to Memory

• The binary storage cell is the basic building block of a memory unit. The
equivalent logic of a binary cell that stores one bit of information is shown in the
following Figure.

• The storage part of the cell is modelled by an SR latch with associated gates to
form a D latch. Actually, the cell is an electronic circuit with four to six transistors.
Nevertheless, it is possible and convenient to model it in terms of logic symbols.

• A binary storage cell must be very small in order to be able to pack as many cells
as possible in the small area available in the integrated circuit chip.

• The binary cell stores one bit in its internal latch. The select input enables the cell
for reading or writing, and the read/write input determines the operation of the
cell when it is selected. A ‘1’ in the read/write input provides the read operation
by forming a path from the latch to the output terminal. A ‘0’ in the read/write
input provides the write operation by forming a path from the input terminal to
the latch.

Memory cell
Introduction to Memory

• The logical construction of a small RAM is shown in the following figure . This
RAM consists of four words of four bits each and has a total of 16 binary cells.
The small blocks labelled BC represent the binary cell with its three inputs and
one output.

• A memory with four words needs two address lines. The two address inputs go
through a 2 * 4 decoder to select one of the four words.

• The decoder is enabled with the memory‐enable input. When the memory enable
is 0, all outputs of the decoder are 0 and none of the memory words are selected.
With the memory select at 1, one of the four words is selected, dictated by the
value in the two address lines.

• Once a word has been selected, the read/write input determines the operation.
During the read operation, the four bits of the selected word go through OR gates
to the output terminals.

• During the write operation, the data available in the input lines are transferred
into the four binary cells of the selected word. The binary cells that are not
selected are disabled, and their previous binary values remain unchanged.

• When the memory select input that goes into the decoder is equal to 0, none of
the words are selected and the contents of all cells remain unchanged regardless
of the value of the read/write input.

• Commercial RAMs may have a capacity of thousands of words, and each word
may range from 1 to 64 bits. The logical construction of a large‐capacity memory
would be a direct extension of the configuration shown here.
Introduction to Memory

• A memory with 2k words of n bits per word requires k address lines that go into a
k * 2k decoder. Each one of the decoder outputs selects one word of n bits for
reading or writing.

• A memory with four words needs two address lines. The two address inputs go
through a 2 * 4 decoder to select one of the four words.

Diagram of a 4 * 4 RAM

Coincident Decoding

• A decoder with k inputs and 2k outputs requires 2k AND gates with k inputs per
gate. The total number of gates and the number of inputs per gate can be
reduced by employing two decoders in a two‐dimensional selection scheme.

• The basic idea in two‐dimensional decoding is to arrange the memory cells in an

array that is close as possible to square.
Introduction to Memory

• In this configuration, two k /2‐input decoders are used instead of one k ‐input
decoder. One decoder performs the row selection and the other the column
selection in a two‐dimensional matrix configuration.

• The two‐dimensional selection pattern is demonstrated in the following figure for

a 1K‐word memory. Instead of using a single 10 * 1,024 decoder, we use two 5 *
32 decoders.

• The five most significant bits of the address go to input X and the five least
significant bits go to input Y. Each word within the memory array is selected by
the coincidence of one X line and one Y line.

• Thus, each word in memory is selected by the coincidence between 1 of 32 rows

and 1 of 32 columns, for a total of 1,024 words. Note that each intersection
represents a word that may have any number of bits.

• As an example, consider the word whose address is 404. The 10‐bit binary
equivalent of 404 is 01100 10100. This makes X = 01100 (binary 12) and Y =
10100 (binary 20).

• The n ‐bit word that is selected lies in the X decoder output number 12 and the Y
decoder output number 20. All the bits of the word are selected for reading or
writing.
Introduction to Memory

Two‐dimensional decoding structure for a 1K‐word memory

Address Multiplexing

• The SRAM memory cell typically contains six transistors. In order to build
memories with higher density, it is necessary to reduce the number of transistors
in a cell.

• The DRAM cell contains a single MOS transistor and a capacitor. The charge
stored on the capacitor discharges with time, and the memory cells must be
periodically recharged by refreshing the memory.

• Because of their simple cell structure, DRAMs typically have four times the density
of SRAMs. This allows four times as much memory capacity to be placed on a
given size of chip.
Introduction to Memory

• The cost per bit of DRAM storage is three to four times less than that of SRAM
storage. A further cost savings is realized because of the lower power
requirement of DRAM cells.

• These advantages make DRAM the preferred technology for large memories in
personal digital computers. DRAM chips are available in capacities from 64K to
256M bits.

• Most DRAMs have a 1‐bit word size, so several chips have to be combined to
produce a larger word size.

• Because of their large capacity, the address decoding of DRAMs is arranged in a

two‐dimensional array, and larger memories often have multiple arrays.

• To reduce the number of pins in the IC package, designers utilize address

multiplexing whereby one set of address input pins accommodates the address
components.

• In a two‐dimensional array, the address is applied in two parts at different times,

with the row address first and the column address second. Since the same set of
pins is used for both parts of the address, the size of the package is decreased
significantly.

• We will use a 64K‐word memory to illustrate the address‐multiplexing idea. The

following diagram shows the decoding configuration. The memory consists of a
two‐dimensional array of cells arranged into 256 rows by 256 columns, for a total
of 28 * 28 = 216 = 64K words.
Introduction to Memory

• There is a single data input line, a single data output line, and a read/write
control, as well as an eight‐bit address input and two address strobes, the latter
included for enabling the row and column address into their respective registers.

• The row address strobe (RAS) enables the eight‐bit row register, and the column
address strobe (CAS) enables the eight‐bit column register.

• The bar on top of the name of the strobe symbol indicates that the registers are
enabled on the zero level of the signal.

• The 16‐bit address is applied to the DRAM in two steps using RAS and CAS.
Initially, both strobes are in the 1 state. The 8‐bit row address is applied to the
address inputs and RAS is changed to 0.

• This loads the row address into the row address register. RAS also enables the
row decoder so that it can decode the row address and select one row of the
array. After a time, equivalent to the settling time of the row selection, RAS goes
back to the 1 level.

• The 8‐bit column address is then applied to the address inputs, and CAS is driven
to the 0 state.

• This transfers the column address into the column register and enables the
column decoder. Now the two parts of the address are in their respective
registers, the decoders have decoded them to select the one cell corresponding to
the row and column address, and a read or write operation can be performed on
that cell. CAS must go back to the 1 level before initiating another memory
operation.
Introduction to Memory

Address multiplexing for a 64K DRAM

Solved Problems in RAM

1. Construct a 4K * 8 RAM with four 1K * 8 RAM Chips

Solution:

• The 8 input data lines go to all the chips. The outputs must be ORed together, to
form the common 8 output data lines. The 4k word memory requires a 12-bit
address. The 10 least significant bits of the address are applied to the address
inputs of all four chips.

• The other two most significant bits are applied to a 2*4 decoder. The four outputs
of the decoder are applied to the CS inputs of each chip. The memory is disabled
when the memory enable input of the decoder is equal to 0. This causes all the
four outputs of the decoder to be in the 0 state and none of the chips are
selected.
Introduction to Memory

Block Diagram of 1k * 8 RAM

Block Diagram of 4k * 8 RAM

Introduction to Memory

2. Construct two 1k * 8 chips to form a 1k * 16 memory

Solution:

• The 16 input and output data lines are split between the two chips. Both receive
the same 10-bit address and the common CS and RW control inputs.

Click Here for Quiz

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 2. ERROR CORRECTION SCHEME – HAMMING CODE

1. Obtain the 12‐bit Hamming code word for the 8‐bit data word
11000100.

Solution

•The given 8-bit data word is 11000100.

•We include 4 parity bits with the 8‐bit word and arrange the 12 bits as follows:

•The 4 parity bits, P1, P2, P4, and P8, are in positions 1, 2, 4, and 8, respectively.
•The 8 bits of the data word are in the remaining positions. Each parity bit is
calculated as follows:

•The exclusive‐OR (XOR) operation performs the odd function: It is equal to 1 for an
odd number of 1’s in the variables and to 0 for an even number of 1’s. Thus, each
parity bit is set so that the total number of 1’s in the checked positions, including the
parity bit, is always even.
 2. ERROR CORRECTION SCHEME – HAMMING CODE

1. Obtain the 12‐bit Hamming code word for the 8‐bit data word 11000100.

•The 8‐bit data word is stored in memory together with the 4 parity bits as a 12‐bit composite
word. Substituting the 4 P bits in their proper positions, we obtain the 12‐bit composite word
stored in memory:

•Therefore, the 12‐bit Hamming code word for the 8‐bit data word 11000100, calculated is,
001110010100
 2. ERROR CORRECTION SCHEME – HAMMING CODE

2. Obtain the 15‐bit Hamming code word for the 11‐bit data word 11001001010.

Solution

Solution

The given 11-bit data word is 11001001010.

We include 4 parity bits P1, P2 , P4 , P8 with the 11‐bit word and arrange the 15 bits as follows:

• The 4-parity bits, P1, P2 , P4 , and P8, are in positions 1, 2, 4, and 8, respectively.
• The 11-bits of the data word are in the remaining positions.
• Each parity bit is calculated as follows:

• The exclusive‐OR (XOR) operation performs the odd function: It is equal to 1 for an odd
number of 1’s in the variables and to 0 for an even number of 1’s. Thus, each parity bit is
set so that the total number of 1’s in the checked positions, including the parity bit, is
always even.
 2. ERROR CORRECTION SCHEME – HAMMING CODE

2. Obtain the 15‐bit Hamming code word for the 11‐bit data word 11001001010.

•The 11‐bit data word is stored in memory together with the 4 parity bits as a 15‐bit composite
word. Substituting the 4 P bits in their proper positions, we obtain the 15‐bit composite word
stored in memory:

•Therefore, the 15‐bit Hamming code word for the 11‐bit data word 11001001010, calculated
is,
101 110 011 001 010
 2. ERROR CORRECTION SCHEME – HAMMING CODE

3. A 12‐bit Hamming code word containing 8 bits of data and 4 parity bits
is read from memory. What was the original 8‐bit data word that was
written into memory if the 12‐bit word read out is as follows:

(a) 001110010100 (b) 101110010100 (c) 001100010100

Solution

•The 12‐bit Hamming code word containing 8 bits of data and 4 parity bits given is,
(a) 001110010100
(b) 101110010100
(c) 001100010100

• When the 12 bits are read from memory, they are checked again for errors. The
parity is checked over the same combination of bits, including the parity bit.
•The original 8-bit data word can be retrieved after the 4 check bits are evaluated as
follows:

•Now for every data word, the C = C8C4C2C1, will be evaluated.

•If C produces 0 check bit, then it indicates that no error has
occurred.
•That is, a 0 check bit designates even parity over the checked bits
and a 1 designates odd parity.
•Since the bits were stored with even parity, the result, C =
C8C4C2C1 = 0000, indicates that no error has occurred.
•However, if C 0, then the 4‐bit binary number formed by the check
bits gives the position of the erroneous bit.
 2. ERROR CORRECTION SCHEME – HAMMING CODE

3. A 12‐bit Hamming code word containing 8 bits of data and 4 parity bits is
read from memory. What was the original 8‐bit data word that was written into
memory if the 12‐bit word read out is as follows:

(a) 001110010100 (b) 101110010100 (c) 001100010100

•Then, consider the 3 12‐bit Hamming code word,

(a) 001110010100
(b) 101110010100
(c) 001100010100

• In a) C = C8C4C2C1 = 0000, indicates no error in the data word. Therefore the

original data word is, 11000100 (Except P1, P2, P4, and P8)

•In b) C = C8C4C2C1 = 0001, indicates error in bit 1. But the given 12-bit Hamming
word is 101110010100. Since there is an error in bit 1 (as computed C = 0001, is bit 1),
it has to be inverted. Therefore the correct 12-bit Hamming code is, 001110010100.
Therefore, the original data word is, 11000100.

•In c) C = C8C4C2C1 = 0101, indicates error in bit 5. But the given 12-bit Hamming
word is 001100010100. Since there is an error in bit 5 (as computed C = 0101, is bit 5), it
has to be inverted. Therefore the correct 12-bit Hamming code is, 001110010100.
Therefore, the original data word is, 11000100.
 2. ERROR CORRECTION SCHEME – HAMMING CODE

4. A 12‐bit Hamming code word containing 8 bits of data and 4 parity bits
is read from memory. What was the original 8‐bit data word that was
written into memory if the 12‐bit word read out is as follows:

(a)000011101010 (b) 101110000110 (c) 101111110100

Solution

(a)The 12‐bit Hamming code word containing 8 bits of data and 4 parity bits given
is,

(b) 000011101010

(c) 101110000110

(d) 101111110100

• When the 12 bits are read from memory, they are checked again for errors. The
parity is checked over the same combination of bits, including the parity bit.
•The original 8-bit data word can be retrieved after the 4 check bits are evaluated as
follows:

•Now for every data word, the C = C8C4C2C1, will be evaluated.

• If C produces 0 check bit, then it indicates that no error has
occurred.
•That is, a 0 check bit designates even parity over the checked bits
and a 1 designates odd parity.
•Since the bits were stored with even parity, the result, C =
C8C4C2C1 = 0000, indicates that no error has occurred.
•However, if C 0, then the 4‐bit binary number formed by the check
 2. ERROR CORRECTION SCHEME – HAMMING CODE

4. A 12‐bit Hamming code word containing 8 bits of data and 4 parity bits is
read from memory. What was the original 8‐bit data word that was written into
memory if the 12‐bit word read out is as follows:

(a) 000011101010 (b) 101110000110 (c) 101111110100

•Then, consider the 3 12‐bit Hamming code word,

(a) 000011101010

(b) 101110000110

(c) 101111110100

•In a) C = C8C4C2C1 = 0110, indicates that there is an error in the 6th bit of the
Hamming code. Therefore the correct 12-bit Hamming code is, 000010101010. Therefore
the original data word is, 0101 1010 (Except P1, P2, P4, and P8).

•In b) C = C8C4C2C1 = 0010, indicates error in bit 2. Therefore the correct 12-bit
Hamming code is, 111110000110. Therefore, the original data word is, 1100 0110.

•In c) C = C8C4C2C1 = 0000, indicates no error in the data word. Therefore, the
original data word is, 1111 0100 .
2. SINGLE‐ERROR CORRECTION, DOUBLE‐ERROR DETECTION

•The Hamming code can detect and correct only a single error.
•By adding another parity bit to the coded word, the Hamming code can be used to correct a
single error and detect double errors.
• If we include this additional parity bit, then the previous 12‐bit coded word becomes
001110010100P13, where P13 is evaluated from the exclusive‐OR of the other 12 bits.
• This produces the 13‐bit word 0011100101001 (even parity).
•When the 13‐bit word is read from memory, the check bits are evaluated, as is the parity P
over the entire 13 bits.
•If P = 0, the parity is correct (even parity), but if P = 1, then the parity over the 13 bits is
incorrect (odd parity).
The following four cases can arise:
• If C = 0 and P = 0, no error occurred.
• If C ≠ 0 and P = 1, a single error occurred that can be corrected.
• If C ≠ 0 and P = 0, a double error occurred that is detected, but that cannot be corrected.
• If C = 0 and P = 1, an error occurred in the P13 bit.

This scheme may detect more than two errors, but is not guaranteed to detect all such errors.
 READ ONLY MEMORY (ROM)

ROM
In Read Only Memory (ROM) permanent binary image is stored, once the pattern is
established, it stays within the unit even when the power is turned off and on again.

No. of words in ROM = 2k

No. of address lines needed = k
Size of each word = n bits

Ex: 32 x 8 ROM
No. of words in ROM = 32(25)
Size of each word = 8 bits
No. of address lines needed = 5 bits
The output of the decoder represents the memory address.
The 32 outputs of the decoder are connected to each of the eight OR gates.
Each OR gate must be connected to 32 input.
ROM has 32 x 8 = 256 internal connections.
READ ONLY MEMORY (ROM)
COMBINATIONAL CIRCUIT IMPLEMENTATION
• By inserting OR gates to sum of minterms of Boolean functions, able to generate
any desired combinational circuit.
• The ROM is essentially a device that includes both the decoder and the OR gates
within a single device. By choosing connections for those minterms that are
included in the function, the ROM outputs can be programmed to represent the
Boolean functions.
• The internal operation of a ROM can be interpreted in two ways:
• i) It is a memory unit that contains a fixed pattern of stored words.
• ii) It is a unit that implements a combinational circuit.

1. Implement the Boolean function using ROM/PROM.

F1(A1,A0) = ∑m(1,2)
F2(A1,A0) = ∑m(0,1,3)

Solution: F1,F2 are two outputs, so size of the word is 2

Minterms (0 to 3), so the number of address lines = 2
Number of words = 4 (22)
Decoder needed is 2 to 4 decoder
2. Design a combinational circuit using a PROM. The circuit accepts a 3 bit binary
number and generates an output binary number equal to the square of the input
number.
Solution:
Number of address lines (input) = 3 bits
Number of words = 23 = 8 words (minterms)
Size of each word = 6 bits
Decoder needed = 3 to 8 decoder
PROGRAMMABLE LOGIC DEVICES
(PLD)
COMBINATIONAL PLD’S:
• The PROM is a combinational programmable logic device (PLD).
• It is an IC with programmable gates divided into an AND array and an OR array to
provide an AND-OR SOP implementation.
• Three major types of combinational PLD’s :
i. Programmable ROM (PROM)
ii. Programmable Array Logic (PAL)
iii. Programmable Logic Array (PLA)
i) Programmable Read Only Memory: (PROM)
• Fixed AND array constructed as a decoder and a Programmable OR array.
• The programmable OR gates implement the Boolean functions in the sum of
minterms.

ii) Programmable Array Logic (PAL)

• Programmable AND array and a fixed OR array.
• They implement the Boolean function in SOP.
• AND gates are programmed to give the product terms, which are logically
summed in each OR gate.

iii) Programmable Logic Array (PLA)

• Most flexible PLD
• Both the AND and OR gates/arrays can be programmed
• The product terms in the AND array may be shared by any OR gate to provide
the required SOP implementation.
PROGRAMMABLE LOGIC ARRAY
(PLA)

PROGRAMMABLE LOGIC ARRAY (PLA)

• Similar to PROM in concept.

• Does not provide full decoding of the variables and does not generate all the
minterms.
• Decoder is replaced by an array of AND gates that can be programmed to
generate any product term of the input variables.
• The product terms are then connected to OR gates to provide the sum of
products for the required Boolean function.
n x p x m PLA
m -> variable
p -> product terms
n -> output lines
Implementing Combinational Circuit with a PLA
• Reduce the number of distinct product terms, since PLA has a finite number of
AND gates.
• The number of literals in a term is not importance, since all the input variables are
available any way.
• Each function should be simplified to find out product terms which are common to
other functions.
PLA Types:
(i) Mask Programmable: Programmable by the manufacturer.
(ii) Field Programmable Logic Array (FPLA): Can be programmed by the user by
means of a commercial hardware programmer unit.
1) Implement the following Boolean functions in a PLA:
F1 = AB’ + AC + A’BC’
F2 = (AC+BC)’

PLA Programming Table

PLA with 3 inputs, 4 products terms and 2 outputs

PROGRAMMABLE LOGIC ARRAY
(PLA)
• A dash specifies a blown fuse.
• An open terminal in the input of an AND gate behaves like a 1.
• An open terminal in the input of an OR gate behaves like a 0

2) Implement the following Boolean functions with a PLA:

F1(A,B,C) = ∑ (0,1,2,4)
F2(A,B,C) = ∑ (0,5,6,7)
Solution:
Simplify using K-Maps
PLA Programming Table

F1 = (AB+AC+BC)’
F2 = AB+AC+A’B’C’
PROGRAMMABLE ARRAY LOGIC
(PAL)
PROGRAMMABLE ARRAY LOGIC (PAL)
• PAL is a programmable logic device with a fixed OR array and a programmable
AND array.
• Easier to program, but is not as flexible as the PLA
• Each input has a buffer-inverter gate and each output has a fixed OR gate.
• Each sections in the unit is composed of a three-wide AND-OR array.
• Unlike the PLA, a product term cannot be shared among two or more OR gates.
Therefore, each function can be simplified by itself without regard to common
product terms.
• The number of product terms in each section is fixed and if the number of terms
in the function is too large, it may be necessary to use two sections.
• If AND gate is not used, all its input fuses are left intact. Since the corresponding
input receives both the true and complement of each input variable, we have AA’
= 0, and the output of the AND gate is always 0.

• Implementing Boolean functions with PAL:

• Boolean functions must be simplified to fit into each section.
• A product term cannot be shared among two or more OR gates. So, each function
can be simplified by itself without regard to common product terms.

1) Implement the Boolean function using a PAL:

W(A,B,C,D) = ∑(2,12,13)
X(A.B.C.D) = ∑(7,8,9,10,11,12,13,14,15)
Y(A.B.C.D) = ∑(0,2,3,4,5,6,7,8,10,11,15)
z(A,B,C,D) = ∑(1,2,8,12,13)
Simplify using K-Map
PROGRAMMABLE ARRAY LOGIC
(PAL)

PAL Programming Table

 7. SEQUENTIAL PROGRAMMABLE DEVICES

• Digital systems are designed with flip‐flops and gates.

• Since the Combinational PLDs consists of only gates, it is necessary to include

external flip‐flops when they are used in the design.

• Sequential programmable devices include both gates and flip‐flops. In this way,
the device can be programmed to perform a variety of sequential‐circuit
functions.

• There are several types of sequential programmable devices available

commercially, and each device has vendor‐specific variants within each type.

• The internal logic of these devices is too complex. Therefore, a brief description
of three major types of Sequential Programmable devices is given.

1. Sequential (or simple) programmable logic device (SPLD)

2. Complex programmable logic device (CPLD)

3. Field‐programmable gate array (FPGA)

7.1 SEQUENTIAL (OR SIMPLE) PROGRAMMABLE LOGIC DEVICE

(SPLD)

• The sequential PLD is sometimes referred to as a simple PLD to differentiate it

from the complex PLD.

• The SPLD includes flip‐flops, in addition to the AND–OR array, within the
integrated circuit chip.

• The block diagram of a Sequential/Simple Programmable Logic Device is given as

follows

Fig 7.1 Sequential Programmable Logic Device

 7. SEQUENTIAL PROGRAMMABLE DEVICES

• A PAL or PLA is modified by including a number of flip‐flops connected to form a

register.
• The circuit outputs can be taken from the OR gates or from the outputs of the
flip‐flops.

• Additional programmable connections are available to include the flip‐flop outputs

in the product terms formed with the AND array.

• The flip‐flops may be of the D or the JK type .

Configuration of a SPLD

• The configuration mostly used in an SPLD is the combinational PAL together with
D flip‐flops.

• A PAL that includes flip‐flops is referred to as a registered PAL, to signify that the
device contains flip‐flops in addition to the AND–OR array.

Macrocell

• Each section of an SPLD is called a macrocell, which is a circuit that contains a

sum‐of‐products combinational logic function and an optional flip‐flop.

Fig 7.2 Basic Macrocell Logic

 7. SEQUENTIAL PROGRAMMABLE DEVICES

• The AND–OR array is the same as in the combinational PAL.

• The output is driven by an edge‐triggered D flip‐flop connected to a common

clock input and changes state on a clock edge.

• The output of the flip‐flop is connected to a three‐state buffer (or inverter)

controlled by an output‐enable signal marked in the diagram as OE.

• The output of the flip‐flop is fed back into one of the inputs of the programmable
AND gates to provide the present‐state condition for the sequential circuit.

• A typical SPLD has from 8 to 10 macrocells within one IC package.

• All the flip‐flops are connected to the common CLK input, and all three‐state
buffers are controlled by the OE input.

• In addition to programming the AND array, a macrocell may have other

programming features.

• Typical programming options include the ability to either use or bypass the
flip‐flop, the selection of clock edge polarity, the selection of preset and clear for
the register, and the selection of the true value or complement of an output. An
XOR gate is used to program a true/complement condition. Multiplexers select
between two or four distinct paths by programming the selection inputs.

7.2 COMPLEX PROGRAMMABLE LOGIC DEVICE (CPLD)

• A complex programmable logic device (CPLD) is a collection of individual PLDs on

a single integrated circuit.

• A programmable interconnection structure allows the PLDs to be connected to

each other in the same way that can be done with individual PLDs.
 7. SEQUENTIAL PROGRAMMABLE DEVICES

General CPLD Configuration

A complex programmable logic device (CPLD) is a logic device with

completely programmable AND/OR arrays and macrocells. Macrocells are the
main building blocks of a CPLD.

Fig.7.3 General CPLD Configuration

• The device consists of multiple PLDs interconnected through a programmable

switch matrix.

• The input–output (I/O) blocks provide the connections to the IC pins.

• Each I/O pin is driven by a three‐ state buffer and can be programmed to act as
input or output.

• The switch matrix receives inputs from the I/O block and directs them to the
individual macrocells.

• Similarly, selected outputs from macrocells are sent to the outputs as needed.
Each PLD typically contains from 8 to 16 macrocells, usually fully connected.

• If a macrocell has unused product terms, they can be used by other nearby
macrocells. In some cases the macrocell flip‐flop is programmed to act as a D, JK,
or T flip‐flop.
 47 SEQUENTIAL PROGRAMMABLE DEVICES

7.3 FIELD PROGRAMMABLE GATE ARRAY (FPGA)

• The basic component used in VLSI design is the gate array, which consists of a
pattern of gates, fabricated in an area of silicon, that is repeated thousands of
times until the entire chip is covered with gates.

• A Field‐Programmable Gate Array (FPGA) is a VLSI circuit that can be

programmed at the user’s location.

• A typical FPGA consists of an array of millions of configurable logic blocks,

surrounded by programmable input and output blocks and connected together via
programmable interconnections.

• Each Configurable Logic Block can generate logic functions of many inputs.

• There is a wide variety of internal configurations within this group of devices.

• The performance of each type of device depends on the circuit contained in its
logic blocks and the efficiency of its programmed interconnections.

FPGA Logic Block

• A typical FPGA logic block consists of

i. Lookup tables
ii. Multiplexers
iii. Gates
iv. Flip‐flops

• Logic blocks uses a lookup table, which is a truth table stored in an SRAM and
provides the combinational circuit functions for the logic block.

• These functions are realized from the lookup table, in the same way that
combinational circuit functions are implemented with ROM.

• For example, a 16 * 2 SRAM can store the truth table of a combinational circuit
that has four inputs and two outputs. The combinational logic section, along
with a number of programmable multiplexers, is used to configure the input
equations for the flip‐flop and the output of the logic block.
 7. SEQUENTIAL PROGRAMMABLE DEVICES

• The advantage of using RAM instead of ROM to store the truth table is that the
table can be programmed by writing into memory.

• The disadvantage is that the memory is volatile and presents the need for the
lookup table’s content to be reloaded in the event that power is disrupted.

• The device must be reprogrammed every time power is turned on.

• SRAM based FPGA comes with EPROM which loads during power on.

Xilinx FPGAs
• Xilinx launched the world’s first commercial FPGA in 1985.

• The basic architecture consists of

• an array of configurable logic blocks (CLBs)
• a variety of local and global routing resources
• input–output (I/O) blocks (IOBs)
• programmable I/O buffers
• an SRAM‐based configuration memory

Fig 7.4. Basic Architecture of Xilinx FPGA

 7. SEQUENTIAL PROGRAMMABLE DEVICES

• Each CLB consists of a programmable lookup table, multiplexers, registers, and

paths for control signals.

• The programmable interconnect resources of the device connect Configurable

Logic Blocks (CLBs) and Input/output Blocks (IOBs), either directly or through
switch boxes.

• A grid of switch matrices overlays the architecture of CLBs to provide

general‐purpose interconnect for branching and routing throughout the device.

• A grid of horizontal and vertical single‐length lines connects an array of switch

boxes that provide a reduced number of connections between signal paths within
each box.

• Direct (dedicated) interconnect lines provide routing between adjacent vertical

and horizontal CLBs in the same column or row.
Video Links
UNIT V
Video Links
Sl. Topic Video Link
No.
Primary Memory : Types and https://www.youtube.com/watch?
1 differences from Secondary v=c3m9r62jMS8
Storage Memory
https://www.youtube.com/watch?
2 Basic Implementation of RAM
v=hDxq0qlChTs
Hamming Code | Error https://www.youtube.com/watch?
3 v=1A_NcXxdoCc
detection
https://www.youtube.com/watch?
4 ROM and PLA Implementation v=zaLPKUVffjY
https://www.youtube.com/watch?
5 PAL, PLA, CPLD, FPGA v=gCAYY0fHPq4

Sequential Programmable https://www.youtube.com/watch?

6
Devices v=gCAYY0fHPq4
Assignments
UNIT V
Assignment Questions
1) We have found a minimum sum of products expression for each of two
function F and G, minimizing them individually (no sharing) ( CO4, K6)

F = WY’ + XY’Z
G = WX’Y’ + X’ Y + W’Y’Z
Implement them with a ROM.
Implement them in the PLA using no more than four terms.

2) Design a combinational circuit defined by the following Boolean

functions using a PAL: ( CO4, K6)
W (A, ,B, C, D) =∑ (2, 12, 13)
x (A, ,B, C, D) =∑ (7, 8, 9, 10, 11, 12, 13, 14, 15)
y (A, ,B, C, D) =∑ (0, 2, 3, 4, 5, 6, 7, 8, 10, 11, 15)
z (A, ,B, C, D) =∑ (1, 2, 8, 12, 13)

3) A combinational logic circuit is defined by the functions ( CO4, K6)

F =∑ (3, 4, 5, 7, 10, 14, 15)
G =∑ (1, 5, 7, 11, 15)
Implement the circuit using a programmable logic array with 4 inputs, 6 product
terms and 2 outputs.
Part A – Q & A
Unit - V
 Part A Q & A (with K level and CO)

1) What is the use of error detection scheme. (CO6, k1)

The dynamic physical interaction of the electrical signals affecting the data path of a
memory unit may cause occasional errors in storing and retrieving the binary information.
Therefore , the error detection schemes such as Parity Bit and Hamming Code is used to
detect and correct errors.

2) What is the use of Hamming Codes. (CO6, k1)

One of the most common error‐correcting codes used in RAMs was Hamming Codes. In the
Hamming code, k parity bits are added to an n ‐bit data word, forming a new word of n + k
bits.

3) List the basic types of programmable logic devices. ( CO4, K1)

PAL – Programmable Array Logic
PLA – Programmable Logic Array

4) What is PAL? How it differ from PROM and PLA? ( CO4, K1)
PAL is a programmable logic device with a fixed OR array and a programmable AND
array. Because only the AND gates are programmable, the PAL is easier to program than,
but is not flexible as, the PLA.

5) Distinguish between PAL and PLA ( CO4, K1)

PAL - AND array is programmable, OR array is fixed at fabrication
PLA - Both AND and OR arrays are programmable
• Of the two organizations the PLA is the most flexible
• One PLA can implement a huge range of logic functions
• BUT many pins; large package, higher cost
• PALs are more restricted / you trade number of OR terms vs number of outputs
• Many device variations needed
• Each device is cheaper than a PLA
Part A Q & A (with K level and CO)

6) Differentiate ROM & PLD’s ( CO4, K1)

ROM (Read Only Memory) PLD’s (Programmable

Logic Devices)
It is a device that includes It is a device that includes
both the decoder and the OR both AND
gates within a single IC and OR gates within a single
package IC package
ROM does not full decoding of PLD’s does not provide full
the variables and does decoding of the variable and
generate all the minterms does not generate all the
minterms

7) What are the terms that determine the size of a PAL? ( CO4, K1)
The size of a PLA is specified by the
Number of inputs, Number of products terms & Number of outputs
 Part A Q & A (with K level and CO)
8) What is a Sequential Programmable Device? (CO5, k1)

• Digital systems are designed with flip‐flops and gates.

• Since the Combinational PLDs consists of only gates, it is necessary to include

external flip‐flops when they are used in the design.

• Sequential programmable devices include both gates and flip‐flops. In this way,
the device can be programmed to perform a variety of sequential‐circuit
functions.

9) What are the types of Sequential Programmable Devices? (CO5, k1)

• The three major types of Sequential Programmable devices are:

1. Sequential (or simple) programmable logic device (SPLD)

2. Complex programmable logic device (CPLD)

3. Field‐programmable gate array (FPGA)

10) Define a Simple PLD (SPLD) (CO5, k1)

• The sequential PLD is sometimes referred to as a simple PLD to differentiate it

from the complex PLD.

• The SPLD includes flip‐flops, in addition to the AND–OR array, within the
integrated circuit chip.

• The block diagram of a Sequential/Simple Programmable Logic Device is given as

follows

The flip‐flops may be of the D or the JK type .

 Part A Q & A (with K level and CO)

11) Define a Complex PLD (CO5, k1)

• A complex programmable logic device (CPLD) is a collection of individual PLDs on

a single integrated circuit.

• A programmable interconnection structure allows the PLDs to be connected to

each other in the same way that can be done with individual PLDs.

• A complex programmable logic device (CPLD) is a logic device with

completely programmable AND/OR arrays and macrocells. Macrocells are the main
building blocks of a CPLD.

• The device consists of multiple PLDs interconnected through a programmable

switch matrix.

12) What is a FPGA? (CO5, k1)

• A Field‐Programmable Gate Array (FPGA) is a VLSI circuit that can be

programmed at the user’s location.

• A typical FPGA consists of an array of millions of logic blocks, surrounded by

programmable input and output blocks and connected together via programmable
interconnections.

• A typical FPGA logic block consists of

i. Lookup tables
ii. Multiplexers
iii. Gates
iv. Flip‐flops
Part B – Questions
 Part B Q (with K level and CO)

1. A 12‐bit Hamming code word containing 8 bits of data and 4 parity bits is
read from memory. What was the original 8‐bit data word that was
written into memory if the 12‐bit word read out is as follows: (a)
000011101010 (b) 101110000110 (c) 101111110100 .
(CO6,K2)

2. It is necessary to formulate the Hamming code for four data bits, D3, D5,
D6, and D7, together with three parity bits, P1, P2, and P4. (a) *
Evaluate the 7‐bit composite code word for the data word 0010. (b)
Evaluate three check bits, C4, C2, and C1, assuming no error. (c)
Assume an error in bit D5 during writing into memory. Show how the
error in the bit is detected and corrected. .
(CO6,K2)

3. Given the 8‐bit data word 01011011, generate the 13‐bit composite
word for the Hamming code that corrects single errors and detects
double errors. (CO6,K2)

4. Obtain the 15‐bit Hamming code word for the 11‐bit data word
11001001010. (CO6,K2)
5. Implement the two following Boolean functions using 8 x 2 PROM. (
CO4, K6)
F1 =∑ m (3, 5, 6, 7) and
F2 =∑ m (1, 2, 3, 4)

6. Implement the following two Boolean functions using PLA with 3 inputs,
4 product terms and 2 outputs ( CO4, K6)
F1 =∑ m (3, 5, 6, 7) and
F2 =∑ m (1, 2, 3, 4)

7. Implement the switching function: ( CO4, K6)

Z1 = ab’d’e + a’b’c’d’e’ + bc + de
Z2 = a’c’e
Z3 = bc + de + c’d’e’ + bd
Z4 = a’c’e + ce
Using 5 x 8 x 4 PLA.
 Part B Q (with K level and CO)

8. Implement the following function using PLA: ( CO4, K6)

A(x,y,z) =∑ m (1, 2, 4, 6)
B(x,y,z) =∑ m (0, 1, 6, 7)
C(x,y,z) =∑ m (2, 6)

9. A combinational circuit is defined by the functions ( CO4, K6)

F1 =∑ m (1, 3, 5) and
F2 =∑ m (5, 6, 7)
Implement the circuit with a PLA having 3 inputs, 3 product terms and two
outputs.
10. Explain the various Sequential Programmable Devices with neat
diagrams (CO5, K2)
Supportive online
Certification courses
(NPTEL, Swayam,
Coursera, Udemy, etc.,)
Supportive Online Certification
Courses
• Swayam:
• Digital Circuits By Prof. Santanu Chattopadhyay | IIT Kharagpur
• https://swayam.gov.in/nd1_noc19_ee51/preview
• Coursera:
• Digital Systems: From Logic Gates to Processors offered by Universitat
Autònoma de Barcelona
• https://www.coursera.org/learn/digital-systems
• Classcentral.com:
• Online Course - Digital Electronic Circuits by Indian Institute of
Technology, Kharagpur and NPTEL via Swayam
• https://www.classcentral.com/course/swayam-digital-electronic-circuits-
12953
• Udemy:
• Master The Digital Electronics- Minimisation And Basic Gates –
[Learn about the digital gates, boolean algebra, k-map| Update your digital
from base to pro]
• https://www.udemy.com/course/professional-digital-electronics/
Real time Applications
in day to day life and to
Industry
Real time Applications

Devices where ROM is used:

Devices where RAM is used:

Content Beyond
Syllabus
Application Specific Integrated Circuits
(ASIC)
What is An ASIC(Application Specific Integrated Circuit)?

ASIC full form is Application Specific Integrated Circuit. These circuits are
application specific .i.e. tailored made ICs for a particular application. These are
usually designed from root level based on the requirement of the particular
application. Some of the basic application-specific integrated circuit
examples are chips used in toys, the chip used for interfacing of memory and
microprocessor etc…These chips can be used only for that one application for which
these are designed. Presumably, these types of ICs are preferred only for those
products which have a large production run. As ASICs are designed from the root
level they have high cost and are recommended only for high volume productions.

The main advantage of ASIC is reduced chip size as a large number of functional
units of a circuit are constructed over a single chip. Modern ASIC generally includes
a 32-bit microprocessor, memory blocks, network circuits etc…Such type of ASICs is
known as System on Chip. With the development in manufacturing technology and
increased research in design methods, ASICs with different levels of customization
are developed.

Types of ASIC

ASICs are categorized based on the amount of customization a programmer is

allowed to do on a chip.
Application Specific Integrated Circuits
(ASIC)
Application Specific Integrated Circuit (ASIC) Design Flow
• Designing an ASIC is carried out in step by step manner. This order of steps is
known as ASIC Design Flow. Steps of design flow are given in below flow chart.

Design Entry: At this step, the microarchitecture of the design is implemented

using hardware description languages such as VHDL, Verilog and System Verilog.
Logic Synthesis: At this step a netlist of logic cells to be used, types of
interconnections and all other parts required for the application is prepared using
HDL.
System Partitioning: At this step, we divide the largely sized die into ASIC sized
pieces.
Pre-Layout Simulation: At this step, a simulation test is done to check whether
the design contains any errors.
Floor Planning: At this step blocks of netlist are arranged on the chip.
Placement: At this step location of cells inside the block is decided.
Routing: At this step, connections are drawn between blocks and
cells. Extraction: At this step, we determine the electrical properties like
resistance value and the capacitance value of interconnect.
Post-Layout Simulation: Before the submission of the model for manufacturing
this simulation is done to check whether the system functions properly along with
a load of interconnect.
Applications of ASIC
• The uniqueness of ASIC has revolutionized the way electronics are manufactured.
These reduced the die sizes while increasing the density of logic gates per chip.
ASICs are usually preferred for high-level applications. ASIC chip is used as IP
cores for satellites, ROM manufacturing, Microcontroller and various types of
applications in the medical and research sectors. One of the trending applications
of ASIC is BITCOIN MINER.
Assessment Schedule
(Proposed Date &
Actual Date)
Assessment Schedule (Proposed Date &
Actual Date)
Prescribed Text Books
& Reference
Prescribed Text Books & Reference
TEXT BOOK:
• M. Morris R. Mano, Michael D. Ciletti, “Digital Design: With an Introduction to the Verilog
HDL, VHDL, and System Verilog” , 6th Edition, Pearson Education, 2017.
REFERENCES:
1. G. K. Kharate, Digital Electronics, Oxford University Press, 2010
2. John F. Wakerly, Digital Design Principles and Practices, Fifth Edition, Pearson Education,
2017.
3. Charles H. Roth Jr, Larry L. Kinney, Fundamentals of Logic Design, Sixth Edition, CENGAGE
Learning, 2013
4. Donald D. Givone, Digital Principles and Design‖, Tata Mc Graw Hill, 2003.
Mini Project
Suggestions
Mini Projects

Security Alarm/Burglar Alarm Circuit

USB LED Lamp Circuit

Digital Bank Token Number Display

Smoke Detector Alarm Circuit

Digital Bank Token Number Display

Water Level Controller using 8051

ANALOG TO DIGITAL CONVERTER

Security Alarm/Burglar Alarm Circuit

A burglar alarm system is designed to detect an unauthorized entry into a house or

area. Burglar alarm systems can be used in residential buildings, commercial
buildings, offices, industries and even in military locations. All you need is just to
place this circuit in front of the locker or below the mat so when any unknown
person come and walk over the switch, the circuit will trigger and sound of alarm
comes. The main benefit of the circuit is that these can be implied in two places at a
time as two different switches produces two different sounds.

Circuit Components
● LM358 – 1
● IR Transmitter or IR LED – 1
● Photo Diode – 1
● 10 KΩ – 1
● 150Ω – 1
● 10 KΩ POT – 1
● Buzzer – 1

LM358: It is a dual Op Amp IC. It consists of two independent operational

amplifiers that can be used separately. It is commonly used in all op amp circuits,
transducer amplifiers, active filters, general signal conditioning and DC gain blocks.
IR Transmitter: Infrared or IR is a range of light frequencies that have longer
wavelength than visible light. Hence, they are not visible to human eye. An IR
transmitter or IR LED is a device that emits infrared light.
Photo Diode: A photo diode is a device that converts light to electrical current. It is
basically a PN junction that operates in reverse bias condition. When light falls on
the photo diode, a reverse bias current flows in the junction that is proportional to
the luminescence of the light.
Buzzer: It is an alarming device that makes a loud sound when current flows
through it.
Security Alarm Circuit

Circuit Design of Burglar Alarm System

The IR transmitter or IR LED is connected to a current limiting resistor of 150Ω and
connected to supply. It is placed at the maximum possible range from photo diode.
The cathode of the photo diode is connected to supply while anode is connected to
10KΩ resistor. Other end of the resistor is connected to ground. The anode terminal
of the photo diode is also connected to pin 5 of LM358 op amp, which is the non-
inverting terminal.
Wiper of the 10KΩ POT is connected to the inverting terminal i.e. pin 6 of LM358
while the other two terminals of the POT are connected to Vcc and ground.
Pins 8 and 4 of LM358 are supply pins. They are connected to Vcc and ground
respectively.
The output of the op amp is taken at pin 7. One terminal of the buzzer is connected
to pin 7 of LM358 while the other terminal is connected to Vcc.

Circuit Diagram of Security Alarm

Security Alarm Circuit

Working of Security Alarm Circuit

The aim of this project is to implement a simple Burglar Alarm System that can
detect an unauthorized entry by a burglar. All the connections are made as per
circuit diagram. The working of the circuit is as follows.
LM358 is configured to work as comparator in this project. When the system is
powered on, the IR transmitter or IR LED emits infrared light. This light falls on the
surface of the photo diode.
As it is connected in reverse bias fashion, when the light falls on it, it conducts and
current flows through it. Since it is connected to the non-inverting terminal (pin 5)
of the op amp, output of the op amp comparator will be high. As the buzzer is
connected between Vcc and output of op amp, no alarm is made.
When an intruder or a burglar enters the gap between the IR transmitter and photo
diode, the light falling on the photo diode is interrupted and it doesn’t conduct.
As a result, the input at non-inverting terminal (pin 5) is less than the input at
inverting terminal (pin 6). Hence, the output of the comparator is low. This will
trigger the buzzer and a loud alarm is made.

Video Link

https://youtu.be/P3jz1oo-TXk
USB LED Lamp Circuit

LED Light bulbs are becoming more common and are replacing the CFL Bulbs. With
the cost of LED light bulbs becoming lower, people are gradually shifting towards
LED Lamps in their homes and offices. In this project, a simple USB LED Lamp
circuit is designed. This is an easy to implement DIY circuit that can be used to
provide an extra lighting for your laptop or tablet.

Components Required
● USB Male Connector
● Light Emitting Diodes – 5 X 5mm White LEDs
● Resistors – 100Ω X 5
● Perf Board

Circuit Design of USB LED Lamp Circuit

The circuit mainly consists of a male USB Connector. USBs can be mainly divided
into two standard types – USB of ‘A’ type and USB of ‘B’ type. These different types
of USBs connectors differ in their shapes. Type ‘A’ USB can be used with the
upstream devices such as USB hub or host. Type ‘B’ USB can be used with
downstream devices such as printers.

The cables will have same number of pins but they differ mechanically. Many
versions in USB were released. The first version USB 1.0 and 1.1 had the data rate
of 12 Mbps.USB 2.0 has data rate of 480 Mbps.USB 3.0 is expected to have data rate
of 4.8 Gbps.

USB used here is of type ‘A’. It has 4 pins. These pins are VCC, GND, D+, D-. The
D+ and D- pins are the data pins. VCC pin outputs the voltage of 5V. The USB LED
Lamp with Type ‘A’ male USB connector can be simply connected to the USB port of
the computer.
USB LED Lamp Circuit

LED is a semiconductor device with two leads. Generally LEDs were used for
indicating but now-a-days, LEDs are becoming the main sources of lighting in
homes, offices, streets, automobiles, etc.
An LED is similar to a normal P-N junction diode. The energy emitted is in the form
of light when applied with the required voltage, while normal P-N junction diode
emits energy in the form of heat.
The color of light emitted depends on the band gap of the semiconductor. The LEDs
used here are normal white LEDs. They have voltage drop of 3.6V. The current
required by the LEDs is 40mA.
Initially these LEDs are limited to the red color, later high power LEDs and other
colored LEDs such as blue LEDs, white LEDs etc. were developed.
A resistor of 100Ω is connected between the Light Emitting Diode and the USB.
This acts as a current limiting resistor. As the LEDs require maximum current of
40mA to glow with full brightness, they are required to protect from current more
than this.
So, for that reason, a resistor is to be placed between the LED and the power supply
to limit the amount of current flowing through the LED. The supply voltage coming
from the USB is 5V and the current drop at the Light Emitting Diode is 40 milli
amperes.

The following formula can be used to calculate the resistor value.

R=V/I

where, the value of V is 5 volts and the value of I is 40 mA. So,

R= 5V/0.04A =125 ohms

But generally, 125 ohm resistor does not exist in real time. Therefore a resistor of
100Ω is used instead of 125Ω.
Though it gives an output current of 50 mA, this can be tolerated by the LED.
USB LED Lamp Circuit

DIY LED Light Bulb Circuit Diagram

How to Operate USB LED Lamp Circuit?

● Initially connect the circuit as shown in the circuit diagram.
● Now insert the USB to the port of the computer.
● You can observe the lamp glowing
● Now remove the USB from port.
● Now lamp is switched off.

USB LED Lights Circuit Advantages

● This is simple and inexpensive.

● This is a portable lamp.
● No extra source is required.

Video Link: https://youtu.be/2n_KU6wgmfM

Smoke Detector Alarm Circuit

A Smoke Detector is a smoke sensing device that indicates fire. Smoke Detectors are
very common in homes, offices, schools and industries. Smoke Detectors are very
useful devices as the damage caused by fire accidents is catastrophic.Now a days,
smoke detectors and smoke alarms are very cheap as its usage is increasing and
cost of manufacturing is decreasing. In this project, a simple Smoke Detector Circuit
using simple hardware is implemented.
Components Required

● MQ-2 Sensor
● LM358
● 10KΩ
● 330Ω
● LED
● 0.1µF
● 10KΩ POT
Circuit Diagram:
Smoke Detector Alarm Circuit

Working:
Smoke Detectors are amazing devices as they are small, cheap yet very useful. In
this project, a simple Smoke Detector Circuit with adjustable sensitivity is
implemented.
A Smoke Sensor MQ-2 as the main sensory device. LM358 acts as a comparator in
this circuit. The inverting terminal of LM358 is connected to POT so that the
sensitivity of the circuit can be adjusted.
The output of LM358 is given to an LED as an indicator although a buzzer can be
used as an alarm. The non-inverting terminal of LM358 is connected with output of
smoke sensor.
Initially, when the air is clean, the conductivity between the electrodes is less, as the
resistance is in the order of 50KΩ. The inverting terminal input of comparator is
higher than the non-inverting terminal input. The indicator LED is OFF.
In the event of fire, when the sensor is filled with smoke, the resistance of the
sensor falls to 5KΩ and the conductivity between the electrodes increases.
This provides a higher input at the non-inverting terminal of comparator than the
inverting terminal and the output of comparator is high. The alarming LED is turned
ON as an indication of presence of smoke.

Note:
● The heating element in the Smoke Sensor must be preheated before it can
sense any smoke or gas.
● The sensor gets hot because of the heating coil and it is advised not to touch
the sensor while it is switched on.
● The sensitivity of the circuit to different concentrations of smoke can be
adjusted by using the POT.
● The output LED can be replaced with a loud buzzer for effective alarm.

Video Link: https://circuitdigest.com/electronic-circuits/simple-smoke-detector-alarm-circuit-

diagram
Digital Bank Token Number Display

Token systems are used to manage queues of people in banks, hospitals and other
places. Visitors are allotted serial token numbers and have to wait till there number
is called. These no.’s can be updated by entering the complete no. or by pressing
the up/down key in case it's a serially organized count. Here a very simple token
system or an up down counter is designed.
Components required :
● 1 x Arduino Uno R3 Board
● 1 x 4 Digit Multiplexed Seven Segment Board
● 1 x 8 Push Button Board
● 1 x Mini Breadboard
Optional
● Power Source (Battery with Snapper/DC Adapter) : 9-12V DC
● Tools
● Jumper Wires
Circuit Diagram:

Video Link: https://www.youtube.com/watch?v=quuoFZp0kJs

Water Level Controller using 8051

This system mainly works on a principle that “water conducts electricity”. The four
wires which are dipped into the tank will indicate the different water levels. Based
on the outputs of these wires, microcontroller displays water level on LCD as well as
controls the motor.
Initially when the tank is empty, LCD will display the message LOW and motor runs
automatically. When water level reaches to half level, now LCD displays HALF and
still motor runs.
When the tank is full, LCD displays FULL and motor automatically stops. Again, the
motor runs when water level in the tank becomes LOW.
Components Required for Water Level Controller using 8051
Microcontroller

● AT89C51 Microcontroller (or any 8051 based Microcontroller)

● 8051 Programmer (Programming Board)
● 11.0592 MHz Quartz Crystal
● 2 x 33pF Capacitor
● 2 x 10KΩ Resistor (1/4 Watt), 10µF Capacitor
● Push Button
● 1KΩ x 8 Resistor Pack (for Pull – up)
● 16 x 2 LCD Display, 5V Relay
● 4 x 2N2222 (NPN) Transistors
● DC Motor (for demonstration)
● 10KΩ Potentiometer
● 1N4007 PN Junction Diode
● Programming cable,Connecting wires
● Power Supply
● Keil µVision IDE
● Willar Software (for burning code)
● Proteus (for circuit diagram)
Water Level Controller using 8051

Water Level Controller using 8051 Microcontroller Circuit

Diagram
Water Level Controller using 8051

How to Design Circuit for Water Level Controller using 8051

Microcontroller?
The heart of the Water Level Controller using 8051 Microcontroller project is the
AT89C51 Microcontroller. The water level probes are connected to the P0.0, P0.1
and P0.2 through the transistors (they are connected to the base of the transistors
through corresponding current limiting resistors). P0.0 for LOW level, P0.1 for HALF
Level and P0.2 for HIGH Level.
The Collector terminals of the Transistors are connected to VCC and the Emitter
terminals are connected to PORT0 terminals (P0.0, P0.1 and P0.2).
PORT1 of the microcontroller is connected to the data pins of LCD and the control
pins RS, RW and EN of the LCD Display are connected to the P3.6, GND and P3.7
respectively.
For demonstration purpose, a simple DC Motor Pump is used. It is connected to the
Relay and the input to the relay is fed from P0.7 through a transistor.

Algorithm for Water Level Controller Circuit

● First configure the controller pins P0.0, P0.1 and P0.2 as inputs and P0.7 as
output.
● Now, initialize the LCD.
● Continuously check the water level input pins P0.0, P0.1 and P0.2.
● If all the pins are low, then display tank as “EMPTY” on the LCD and make
P0.7 pin HIGH to run the motor automatically.
● If the level is low i.e. if P0.0 is HIGH, display the water level as “LOW” and
continue to run the motor.
● A HIGH pulse on the pin P0.1 indicates that water has reached half level. So,
display the same thing on LCD and run the motor normally.
● If P0.2 is HIGH, then the water level in the tank is FULL.
● Now, make the P0.7 pin as LOW to turn off the motor automatically.
Water Level Controller using 8051

How to Operate Water Level Controller Circuit using 8051

Microcontroller?
1. Initially, write the program for Water Level Controller in Keil µVision IDE and
generate the .hex file.
2. Burn the program (.hex file) to the microcontroller using external
programmer and Willar Software.
3. Now give the connections as per the circuit diagram.
4. While giving the connections, make sure that there is no common connection
between AC and DC supplies (if you are using an AC Motor)
5. Place the 4 water level indicating wires into the small tank (3 probes for three
different levels and fourth one for common supply)
6. Switch on the supply. Now, the motor will run automatically as there is no
water in the tank. (It will turn on even if the water level is LOW).
7. Now pour the water, when it reaches LOW level, then LCD displays LOW.
8. For middle level, it will display as HALF on the LCD.
9. Still if you pour the water, then the water level reaches full and the LCD
displays FULL and also the motor is turned OFF automatically.
10. Switch off the motor supply and board supply.

Video Link:
https://www.youtube.com/watch?time_continue=112&v=tYwQTTG-
GDg&feature=emb_logo
Analog To Digital Converter

A 2 bit parallel analog to digital converter using comparators and

priority encoder
• An analog-to-digital converter (A/D or ADC) produces a digital number
corresponding to an analog input voltage sample.
• Flash ADC Consists of a series of comparators, each one comparing the input
signal to a unique reference voltage.
• The comparator outputs connect to the inputs of a priority encoder circuit,
which produces a binary output
Design and Working
Input voltage 0-5v. Output -2 bit binary. Any input voltage between 0-5v will be
converted into corresponding binary output.

The circuit shown in figure takes the given analog signal as input (varying from 0-5v)
and produces a digital output corresponding to the input given. In this circuit ,we
used three comparators and a 4*2 priority encoder. There are four resistors of equal
value of 1kohm each. And the reference voltage is taken as 5volts.

1. According to voltage division rule, the reference voltage given is divided into
3Vr/4 ,2Vr/4, Vr/4 at posituve terminal of the comparators respectively. Here, 'Vr' is
the reference voltage. Span is defined as the difference between maximum and
minimum analog input voltages and here, it is 5v. step size is given by span/2^n
where n is number of bits in the binary output(here, n=2). Hence, stepsize is
5/4=1.25 (here).

2. Now, the negative terminals of the comparators are given the input
voltage as analog signal and by comaparing the positive and negative terminals, as
the analog input voltage exceeds the reference voltage at each comparator, the
comparator outputs will go to a high state. By considering first comparator, the
negative terminal has input voltage 'Va' and the positive terminal has input as '3Vr/4' .
if Va is greater than 3Vr/4, the output will be logic 1; else the output will be logic 0.
Similarly, the same procedure is repeated for the remaining comparators with their
respective reference voltages.
Analog To Digital Converter

3. The outputs of comparators are given as inputs to the priority encoder and the
corresponding binary outputs are generated. The priority encoder generates a
binary number based on the highest-order active input, ignoring all other active
inputs. The output of the first comparator will be higher priority input compared
to other bits.

INPUT & OUTPUT

Input Outut
0-1.25 00

1.25-2.5 01

2.5-3.75 10

3.75-5 11

CIRCUIT DIAGRAM
 Thank you

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