AUP-ZU3 Reference Manual RealDigital

Revision: A1 www.realdigital.org

Overview PROG PWR

To power
The AUP-ZU3 is a high-performance PD network
embedded computing platform built USBC port for power
FTDI
around AMD’s Zynq UltraScale+
MPSoC “ZU3EG” device. This
USB2
advanced system-on-chip combines (JTAG &
4Gbyte or
a powerful multicore Arm® 8Gbyte DDR
UART)
USB3 2 USB3 Dual
processing system (PS) with a rich Ports Role ports
set of peripherals and high-speed
Micro SD
interfaces, all tightly integrated with Socket Reset button
ASIC-class programmable logic (PL) System
Done LED
fabric. Mini DP
DisplayPort
The ZU3’s programmable logic fabric Pushbutton
enables high-speed, low-latency, and 33.33MHz PS_Clk User
2 User LEDs
fully customizable hardware
acceleration for compute-intensive
Grove PS Mic in
Expansion
tasks such as graphics rendering, Connectors I2S I2S Line Out
Cocec
video processing, and AI workloads. Line In
Developers can implement custom IP
Pi Camera Pi-cam 8 switches
blocks to create specialized compute (15-pin) 8 LEDs
engines like Deep Learning GPIO 4 RGB LEDs
Processing Units (DPUs), hardware 4 buttons
Pmod+ Expansion
co-processors, or custom memory
Analog/
hierarchies, unlocking capabilities Joystick
and enabling powerful new designs
that are simply not possible with Raspberry Pi Expansion Servo
Connector
fixed-function processor
architectures. 100MHz PL_Clk XADC 10K Pot
With over 6,000 high-bandwidth PL
interconnects between the PS and XCZU3EG-2SFVC784E
PL, the ZU3’s architecture ensures
seamless, high-speed Figure 1: AUP-ZU3 Block Diagram
communication that far outperforms
traditional multichip solutions.

The AUP-ZU3 board features four or eight gigabytes of high-speed DDR memory, onboard ROM, audio and
video interfaces, general-purpose I/O, and multiple expansion connectors compatible with Raspberry Pi,
PMOD, Grove, and standard camera modules. This makes it a versatile solution for rapid prototyping and
embedded system development across a wide range of applications.
AUP-ZU3 Reference Manual Page 2 of 12

The board supports AMD-Xilinx’s Vitis and Vivado toolchains, along with the Python-based PYNQ framework,
offering flexibility for both software and hardware development. Programming can be done directly via USB
2.0 or through SD card boot, giving developers a convenient and adaptable workflow.

PYNQ

PYNQ (Python Productivity for Zynq) is an open-source framework that streamlines the development process
on AMD-Xilinx platforms by providing a high-level, Python-based interface for interacting with programmable
logic. Built on Jupyter notebooks, PYNQ allows developers to load hardware overlays and control custom logic
without the need for traditional, hardware-centric design tools.

By abstracting the complexity of hardware design, PYNQ makes it easier for software developers, data
scientists, and system engineers to leverage the power of hardware acceleration in their applications. This
greatly expands access to custom hardware capabilities, enabling rapid prototyping and development in a
more familiar software environment.

When combined with high-performance platforms like AMD’s MPSoC, PYNQ unlocks advanced visualization
and signal analysis capabilities - making it a powerful tool for many compute-intensive applications and real-
time data processing.

XCZU3 MPSoC and AUP-ZU3 board Major Features

The MPSoC board is centered around the ZYNQ UltraScale+ XCZU3EQ device in the SFVC784 package. The
XCZU3EQ includes:

• A 64-bit quad-core ARM Cortex-A53 and a 32-bit dual-core ARM Cortex-R5F

• Large on-chip cache memories for each core
• A tightly coupled and large programmable logic array with 154K logic cells and 360 DSP slices
• An ARM Mali-400 based GPU and NEON advanced SIMD media processing engine
• A single and/or double precision floating point unit
• 256Kbytes of PS RAM, and a combined 9.4Mb of UltraRAM and distributed RAM
• Support for 32-bit, 3200MHz DDR4 with an 8-channel DMA controller
• Support for PCI Express, SATA, DisplayPort, Gbit Ethernet, USB3 and other common ports
• System Memory Management Unit

The ZU3 board surrounds the ZYNQ device with everything needed to build complex digital systems, including
high-speed memories, highly stable power supplies, clean and fast clocks, and high-speed data offload. Major
board features include:
• Multiple USB ports, including a USB2 port for UART/JTAG and two USB3 dual-role ports
• Up to 8GBtyes of 32-bit, 3200MTPS DDR4 connected to the Processing System (PS)
• Mini DisplayPort and I2S audio codec
• MicroSD card reader
• Raspberry PI, Grove, and Pmod+ expansion connectors
• GPIO devices including pushbuttons, slide switches, LEDs, RGB LEDs.

The figure below shows theZU3 board with callouts for major features and interfaces.
 AUP-ZU3 Reference Manual Page 3 of 12

Mini User USB3 JTAG programming SD card Main power

Displayport ports port socket input

Boot Power
MIPI camera Switch switch
connector

Reset button
& DONE LED Joystick
input

Audio Servo
Jacks ZYNQ DDR4 connectors
Ultrascale+
Fan MPSoC 10K pot
XC ZU3EG DDR4 Connected to ADC

Pmod+ Raspberry Pi
expansion expansion
connector connector

PL GPIO: 8 switches, 8 LEDs, 4 Grove PS GPIO:

buttons, 4 RGB LEDs connectors 2 LEDs, 1 button

Figure 2: ZU3 Board Major Components

Programming
The ZU3 board features a USB2-based JTAG port for programming and debugging. This interface supports
direct hardware configuration from within the Vivado design suite, and enables software development,
execution, and debugging through the Vitis environment. An independent UART/COM port is also always
available over this same USB2 connection.
Alternatively, the board can boot from a MicroSD card loaded with hardware and software configuration files
produced by Vivado and Vitis. A BOOT mode switch located near the SD card slot selects between USB-JTAG
and SD card boot modes. On power-up, if a properly formatted SD card is inserted, the ZU3 device will
automatically load its configuration and programming files from the SD card. These files can be generated
using AMD-Xilinx tools such as Vivado and Vitis, and written to an SD card using any of several freely available
SD card writing programs.
The ZU3 board also supports the PYNQ framework. To use PYNQ, the board must be booted from a MicroSD
card preloaded with a PYNQ image specific to the ZU3. Any branded 16GB or larger MicroSD card (with a
minimum write speed of 10MB/s) can be used, and a compatible SD card is included with the optional ZU3 kit.
AUP-ZU3 Reference Manual Page 4 of 12

The latest PYNQ image from AMD can be downloaded from www.pynq.io and written to an SD card using any
of several freely available SD card writing programs.
A system Reset button is available to restart the board and trigger a new configuration cycle. A status LED
labeled “Done” will illuminate once configuration is complete.

Clocks
The ZU3 uses two primary clock sources: a 33.3333MHz oscillator that provides the primary clock source for
the PS, and a 25MHz crystal that drives a TI CDCE6214 Clock Generator. The TI clock generator is factory
programmed to produce five clock signals: two single-ended 24MHz clocks that drive the two on-board
Microchip USB2 transceivers; a dual-ended 100MHz clock that provides the main PL clock source; and two
dual-ended 100MHz clocks that drive the Gigabit transceiver (GTR) blocks that interface with the USB3 and DP
blocks.

While the clock generator is in-system programmable, reconfiguration is not recommended for most users.
However, it can be controlled via three GPIO pins (GPIO1, GPIO4, and HW_SW_CNTL) and an I²C interface, all
routed from the PS. For detailed guidance on modifying clock settings, please refer to the CDCE6214 datasheet
available on the Texas Instruments website.

100MHz LVDS
OUT3 PL SYS_CLK (D6, D7)
PL
SCL
MIO36
SECREF_P SDA
MIO37
25MHz CLK_GPIO1 Clock
Xtal J19
SECREF_N CLK_GPIO4 Control
J20
CLK_HW_SW_CTRL
L21
100MHz LVDS
OUT2 GTR_REK_CLK_DP (F23, F24)
100MHz LVDS
OUT4 GTR_REK_CLK_USB3 (E21, E22)

33.3333MHz PS_REF_CLK (R16)

Oscillator
PS
24MHz LVCMOS AMD XCZU3EG
OUT1_P
24MHz LVCMOS
OUT1_N
USB 3.0 DRP 1
TI CDCE6214 USB3320C
USB2
PHYs
USB 3.0 DRP 2
USB3320C

Figure 3: AUP-ZU3 Clocking Scheme

AUP-ZU3 Reference Manual Page 5 of 12

Power Supplies
The AUP-ZU3 board is powered via a USB-C adapter connected to the onboard USB-C port labeled “EXT PWR.”
A TPS25730 USB Power Delivery (PD) controller negotiates with the power source to request 9V at up to 3A.
Once negotiated, the input power is routed to three downstream switching regulators, which generate all
required system voltages.

The board supports any USB-C power source that complies with the USB PD standard and that can deliver 9V
at 3A. A compatible USB-C power adapter is included in the board kit.

Under typical operating conditions, the ZU3EG MPSoC may dissipate up to about 12W. To manage this thermal
load, a passive heatsink is pre-installed. However, during sustained high-performance workloads, heat
dissipation may exceed the capacity of passive cooling. In such cases, an active fansink can be added for
improved thermal management. The board includes a built-in fan controller and a 2-pin fan connector,
allowing easy integration of a standard off-the-shelf, clip-on 23mm x 23mm fansink. As examples, the Radian
“FJ23/1.3+Y+T725” fansink is available from radianheatsinks.com, and the HF23 with an added fan is available
from Malico.

If the fan controller detects an over-temperature condition, it will automatically reset the ZU3 MPSoC device
to prevent thermal damage. During this condition, the controller will hold the ZU3 in reset and illuminate a red
LED located near the fan connector to indicate the fault. The board will remain in this state until the
temperature drops below a safe threshold. Once normal thermal conditions are restored, the board will
automatically attempt to reboot from the selected configuration source. To address persistent over-
temperature issues, consider using a modified design that reduces the processing load on the MPSoC, or install
an active fansink to improve cooling performance.

All required board voltages are generated by a series of onboard switching regulators, as illustrated in the
figure below. Two power status LEDs, located in the upper-right corner of the board, indicate the operational
state of the PD controller and the main regulator.

USBC
CC1
EXT CC2 5V/3A Power supply enables,
PWR VBUS
TPSM863257 RGB LEDs, Raspberry PI,
Regulator Servo, USB, fan
TVS2200
Clamp
0.85V/5A
VccINT
100K

100K
100K

100K

ADCIN1 TPS65256
ADCIN2 3.3V/3A LEDs, Pmods, PI & Grove
ADCIN3 Regulator
ADCIN4 Strap connectors, audio, DP,
115K

5.1K

5.1K

5.1K

For ON
USB, SD Card, clock
9V/3A
RSRV26 1.8V/2A Audio codec, FTDI,
10K
10K

10K

RSRV27
RSRV36 VCC_IO, VCC_AUX
2.5V/1A
10K

10K

10K

TPS65295
TPS25730 Regulator DDR
1.2V/8A
USBPD controller USB
PWR

Figure 4: AUP-ZU3 power supplies

AUP-ZU3 Reference Manual Page 6 of 12

Memories
The AUP-ZU3 board is available with either 4GB or 8GB of 3200
MT/s DDR4 memory. The 4GB configuration uses two Micron

Or MT40A2G8T (16Gb)
Timing & 23

MT40A2G16 (32Gb)
MT40A2G8T devices, while the 8GB version uses two dual-die Control
MT40A2G8T devices. Both configurations implement a 32-bit data Addr
14

Micron
bus, with address, control, and timing signals routed in parallel to 16
both DDR devices. Data lines and data strobes are routed Data 16
separately to ensure signal integrity and performance. PS
Pin assignments for the memory interface can be found in the AMD XCZU3EG
schematic.
Figure 5: ZU3 DD4 Memory
In addition to the external DDR4 memory, the ZU3EG MPSoC
integrates several internal memory resources, including 7.6 Mb of
UltraRAM, 1.8 Mb of distributed RAM within the programmable
logic, and a 256 KB SRAM memory block within the processing system.

These internal memory blocks provide fast, low-latency storage for real-time tasks and can be used to optimize
memory hierarchies in performance-critical applications.

Data Ports
The AUP-ZU3 board features multiple high-speed data interfaces for flexible connectivity and development.
It includes two dual-role USB 3.0 user ports, a USB 2.0 port for JTAG programming and UART communication,
and a MicroSD card socket for booting and storage.

All data interfaces are fully supported by drivers included in the Linux distribution provided with the PYNQ
boot image. This image is available for download from both the Real Digital and PYNQ websites, enabling out-
of-the-box support for USB peripherals, serial communication, and SD-based file systems.

USB2/UART port
The AUP-ZU3 board includes a USB-C connector labeled “PROG UART” along the top edge, providing both JTAG
and UART (COM) functionality over a single cable. This interface is powered by an FTDI2232 USB 2.0 controller,
which appears to the host computer as two separate devices: a JTAG programming interface recognized by
AMD-Xilinx development tools, and a standard COM port accessible from Windows and Linux systems.

The JTAG and COM functions operate independently and are always available when the board is connected to
a host via the PROG UART port.

The COM port uses a two-wire UART interface, with signals connected to the ZU3EG processing system on pins
J16 (RXD) and L16 (TXD). Two onboard LEDs labeled RX and TX, located near the USB-C connector, indicate
UART activity for easy monitoring during development and debugging.

USB3 Ports
The AUP-ZU3 board's two USB 3.0 user ports support SuperSpeed (5.0 Gb/s), High-Speed, Full-Speed, and Low-
Speed modes in all configurations. USB 2.0 signaling is handled by USB3320C transceivers, while Multi-Gigabit
Transceivers (MGTs) on the ZU3EG MPSoC handle the USB 3.0 SuperSpeed signals. Both USB host ports can
supply up to 2A of current to connected devices.
AUP-ZU3 Reference Manual Page 7 of 12

To protect against overcurrent conditions, each port includes a Texas Instruments TPS25200 electronic fuse (e-
fuse). If the current draw exceeds approximately 2.5A, the e-fuse will disconnect power from the USB port. In
such an event, a red LED labeled “USB FLT” near the corresponding port will illuminate, indicating that current
flow has been interrupted.

The USB device (slave) port supports up to 12 endpoints and can operate at speeds of up to 5.0 Gb/s, making it
suitable for high-speed data transfer and peripheral emulation.

SD Card
AF18 SD_DQ3
A MicroSD card socket located along the top edge of the AE18 SD_DQ2 SD Card
AUP-ZU3 board supports standard MicroSD cards for boot AG18 SD_DQ1 Socket
MIO Pins AH18 SD_DQ0
images, file systems, and general-purpose data storage. Bank 500
P18
AB20 SD_CLK
This provides a convenient and flexible option for AC21 SD_CMD
embedded Linux systems and custom applications AB19 SD_CD_IN
PS
requiring removable storage.
AMD XCZU3EG

Figure 6. SD Card interface

GPIO
The ZU3 board offers several general-purpose I/O
devices, including pushbuttons, slide switches and LEDs PS_PB_3
User
Button User
that can be used for customized control inputs and status LEDs
PS_LED0
POR System 2 LEDs
indicators. All GPIO inputs and outputs are active high. Reset
PS
Processing System: One pushbutton and two green LEDs, LDn
BTNn
labelled on the board as shown in the diagram, are 8 white LEDs
4 pushbuttons
connected to MIO pins and are directly accessible by the
PS. All three devices are located at the bottom of the SWn RGBn
board between the Grove and Raspberry PI connectors. PL 4 RGB LEDs
8 slide switches
Programmable Logic: Eight pushbuttons, eight white XCZU3EG
LEDs and four RGB LEDs, labelled on the board as shown
in the diagram, are connected to FPGA pins. All devices Figure 7: GPIO (pinouts in Appendix A)
are located along the bottom edge of the board.

Pin numbers for all GPIO devices can be found in Appendix A.

Mini DisplayPort
The AUP-ZU3 board includes a Mini DisplayPort interface capable of driving high-resolution external displays.
This interface is driven directly by the Zynq UltraScale+ MPSoC, which includes an integrated DisplayPort
controller capable of operating high-speed serial transceivers at up to 6 Gb/s. No additional interface
components are required.

The DisplayPort implementation conforms to the VESA DisplayPort Standard Version 1, Revision 2a, and
supports multiple data paths for streaming or memory-based audio/video feeds from both the Processing
System (PS) and the Programmable Logic (PL). It supports dual audio/video pipelines, enabling simultaneous
rendering with features such as alpha blending, chroma resampling, color space conversion, and audio mixing.
AUP-ZU3 Reference Manual Page 8 of 12

MGT D23 DPO_TX_P

D24 DPO_TX_N LANE0 MINI
E25 DP1_TX_P DP
E26 DP1_TX_N LANE1

CONFIG
G16 OE

HPD
Differential DP_TX_AUX_P
J15 DOUT Transceiver DP_TX_AUX_N AUX
F16 DIN FIN1019

PS K15 DP_HPD

AMD XCZU3EG
Figure 8. DP Interface

The DisplayPort interface can derive its pixel clock either from one of the PS PLLs or from a clock provided by
the PL, giving developers flexible clocking options for custom display applications.

To protect the 3.3V power rail on the DisplayPort connector, a Texas Instruments TPS25200 e-fuse is used. If
more than approximately 2.5A of current is drawn, the e-fuse will cut power to the connector. In this case, an
LED labeled “DP FLT” will illuminate, indicating a fault condition.

Audio Codec
The ZU3 board features a TLV320 stereo audio codec, capable of recording and playback at sample rates
ranging from 8 kHz to 96 kHz. Audio input can be sourced from either a microphone connected to the MIC_IN
jack or a line-level signal via the LINE_IN jack. The codec includes advanced signal processing features such as
programmable filters, programmable gain amplifiers (PGAs) with automatic gain control (AGC), and noise gate
functionality, enabling flexible input conditioning for a variety of audio applications.

AF18 AIC_SCL AIC_LO_L

AE18 AIC_SDA AIC_LO_R
AG18 AIC_MCLK
MIO Pins AH18 AIC_WCLK AIC_LI_L
Bank 500 AIC_BCLK AIC_LI_R
P18 AB20
AC21 AIC_DIN
AIC_MICINP_L
AB19 AIC_DOUT
PS TI TLV320 I2C AIC_MICINP_R
AB19 AIC_RST Audio Codec
AMD XCZU3EG

Figure 9. Audio Codec

Audio output is provided through the LINE_OUT jack, which can drive resistive loads ranging from 600 ohms to
10 kΩ, making it suitable for use with amplified headphones or external powered speakers.

The TLV320 codec communicates with the system over the I²C bus using 7-bit addressing, and supports both
standard-mode (100 kbps) and fast-mode (400 kbps) I²C operation for configuration and control.
AUP-ZU3 Reference Manual Page 9 of 12

Pmod+ Port
The AUP-ZU3 board includes a single 30-pin

GND
GND

3V3
3V3
JB1_P (E12)
Pmod+ connector, providing a versatile JA1_P (J12)

interface for custom peripherals and

standard Pmod modules. This connector
routes 24 high-speed, differentially-paired PmodB PmodA
signals from the PL to a compact, low-cost
100-mil DIP header. It supports signal speeds
up to approximately 50 MHz, making it
suitable for a wide range of user-defined I/O Pin 12 Pin 6 3V3

functions. GND

A11 A10 A11 JB4_N

A10 JB2_N
Of the 30 available pins, 4 are connected to A12 B11
PmodB A12 JB4_P
B11 JB2_P
ground, 4 to VDD, and 22 to FPGA I/O B10 D11 B10 JB3_N
D11 JB1_N
signals, arranged as 11 differential pairs. The Pin 7 C11 E12 Pin 1 C11 JB3_P
E12 JB1_P
connector is organized so that it can accept D10 E10 D10 JAB_3
E10 JAB_2
either two standard 12-pin Pmod modules, F10 G11 JAB F10
G11
JAB_4
JAB_1
(Pmod+ Pins)
inserted into designated subsets of the 30- F11 F12 F11 JAB_5
F12 JAB_0
pin footprint, or a single 30-pin double-Pmod Pin 12 Pin 6 3V3

module, using the full connector width. GND

J10 JA4_N
J10 G10 G10 JA2_N
This flexible arrangement allows developers PmodA J11 JA4_P
J11 H11 H11 JA2_P
to easily prototype with off-the-shelf K12 JA3_N
K12 H12 H12 JA1_N
modules or design custom daughterboards. K13 JA3_P
Pin 7 K13 J12 Pin 1 J12 JA1_P
Pmod signal assignments can be found in
Appendix A of the documentation. FPGA
PCB

Figure 10: Pmod+ Connector

Joystick and Analog Ports

The ZU3 board includes an unpopulated 5- PL
0V85
W12
pin header designed for compatibility with AD9_P
VERT W11
analog joysticks. The joystick’s X and Y axis AD9_N
HORZ
signals are routed to channels 8 and 9 of SEL Y12 AD8_P
the Xilinx XADC (Analog-to-Digital GND AA12 AD8_N
Converter), enabling direct analog input JSTICK
AC13
capture. Additionally, the board features a
10K potentiometer connected to the
primary XADC input channels, providing a 10K R13 VP
Pot
convenient analog input source for testing T12
VN
or user interaction.
AMD XCZU3EG

Figure 11. Joystick/Analog ports

AUP-ZU3 Reference Manual Page 10 of 12

Servo Ports
The ZU3 board includes four Jump to use Cable to use
OR
board power external supply
3-pin headers designed for
compatibility with standard GND GND Servo SIG
hobby servo motors. These VS VS Cable PWR (VS)
5V0 5V0 GND
connectors provide signal,
power, and ground lines,
supporting direct

SPWR
connection to commonly

SEL
used servos. Because servo SERVOS SERVO0 W14
motors can draw several GND GND SERVO1 Y14
VS VS SERVO2
hundred milliamps each, SIG
W13
5V0 SERVO3
power availability must be Y13

S3

S1
S0
S2
considered carefully. FPGA

The board's main power Figure 12. Servo ports

supply may be sufficient to
drive one or two servos,
depending on the total current draw. Servo motor power is routed through the jumper labelled
“SPWR SEL”. To power servos using the main supply, install a jumper across the VS and 5V pins on
this jumper.
If additional current is required, a two-pin MTE cable can be used to connect an external bench
power supply directly to the VS and GND pins on the “SPWR SEL” jumper, providing a higher-capacity
power source for more demanding servo configurations.

Grove connectors GROVE

AMD XCZU3EG
Grove connectors offer a standardized,
PS
Pin1

modular interface for connecting a PS

L17 SCL0
3V3
broad range of peripherals such as H17 SDA0
sensors, motors and actuators, displays,
PL

and other modules to system boards PL

AE14 GRV0_GPIO0
like the ZU3. Each Grove connector
AE13 GRV0_GPIO1
features a 4-pin interface comprising
3.3V and GND power rails, along with
PL

two signal lines that support multiple AD15 GRV1_GPIO0

protocols, including I²C, UART, or AD14 GRV1_GPIO1
general-purpose digital I/O.
The ZU3 includes three Grove Figure 13. Grove connectors
connectors to support rapid hardware
AUP-ZU3 Reference Manual Page 11 of 12

expansion. One connector is routed to the Processing System (PS), making it ideal for I²C-based
modules that can be managed entirely through software. The remaining two connectors are
connected to the Programmable Logic (PL), allowing for more flexible use. These can interface with
EMIO-connected I²C or UART buses, or be controlled through custom logic blocks implemented in the
FPGA fabric.
A wide variety of low-cost Grove modules—ranging from sensors and relays to displays and wireless
communication modules—are readily available from Seeed Studio and other vendors. These modules
provide a simple and efficient way to extend the functionality of the ZU3 platform with minimal
development overhead.

Raspberry Pi Hat port and MIPI Camera connector

The ZU3 is equipped with a full Raspberry Pi expansion connector and a MIPI CSI-2 camera interface.
The Raspberry Pi connector supports a wide range of standard “HAT” add-on boards, enabling
extensive expansion and customization using components readily available from various
manufacturers.
The MIPI CSI-2 camera connector supports cameras compliant with the MIPI standard, offering
compatibility with a broad selection of camera modules available from multiple vendors.

CAMERA 5V0 3V3

POT
3V3
Pin1
PL
DO_N(2) AG3
DO_P(3) AH4
Flex D1_N(5) AH3
cable D1_P(6) AG4

CLK_N(8) AD4
CLK_P(9) AD5

PWUP(11) J14
LED(12)
X
SCL(13) K14
MIPI Camera SDA(14_ L14
module
AMD XCZU3EG RPI

Raspberry Pi
Hat connector
(Pinout in Appendix A)
MIPI Connector Interface
Figure 14. Raspberry Pi and MIPI Interfaces
AUP-ZU3 Reference Manual Page 12 of 12

Appendix A. PL Pinout Table

White LEDs (LVCMOS12) Audio (LVCMOS18) PMods (LVCMOS33) Raspberry Pi (LVCMOS3)
PL_USER_LED0 AF5 I2C_AIC_SCL F5 JA_[0] J12 RBP_GPIO[0] AF10
PL_USER_LED1 AE7 I2C_AIC_SDA G5 JA_[1] H12 RBP_GPIO[1] AG10
PL_USER_LED2 AH2 AIC_nRST[0] E2 JA_[2] H11 RBP_GPIO[2] AC12
PL_USER_LED3 AE5 AIC_SDATA_O G3 JA_[3] G10 RBP_GPIO[3] AD12
PL_USER_LED4 AH1 AIC_SDATA_I G4 JA_[4] K13 RBP_GPIO[4] AE12
PL_USER_LED5 AE4 AIC_SCLK G1 JA_[5] K12 RBP_GPIO[5] AE10
PL_USER_LED6 AG1 AIC_LRCLK F2 JA_[6] J11 RBP_GPIO[6] AB11
PL_USER_LED7 AF2 AIC_MCLK F3 JA_[7] J10 RBP_GPIO[7] AD11
JB_[0] E12 RBP_GPIO[8] AG11
RGBs (LVCMOS12) Joystick (LVCMOS33) JB_[1] D11 RBP_GPIO[9] AH11
PL_LEDRGB0_R AD7 SEL_JOYSTICK AC13 JB_[2] B11 RBP_GPIO[10] AH12
PL_LEDRGB0_G AD9 VERT_AD9_P W12 JB_[3] A10 RBP_GPIO[11] AH10
PL_LEDRGB0_B AE9 VERT_AD9_N W11 JB_[4] C11 RBP_GPIO[12] AD10
PL_LEDRGB1_R AG9 HORIZ_AD8_P Y12 JB_[5] B10 RBP_GPIO[13] AA11
PL_LEDRGB1_G AE8 HORIZ_AD8_N AA12 JB_[6] A12 RBP_GPIO[14] AE15
PL_LEDRGB1_B AF8 JB_[7] A11 RBP_GPIO[15] AF13
PL_LEDRGB2_R AF7 Servo (LVCMOS33) JAB_[0] F12 RBP_GPIO[16] AB10
PL_LEDRGB2_G AG8 SERVO[0] W14 JAB_[1] G11 RBP_GPIO[17] AG14
PL_LEDRGB2_B AG6 SERVO[1] Y14 JAB_[2] E10 RBP_GPIO[18] AC11
PL_LEDRGB3_R AF6 SERVO[2] W13 JAB_[3] D10 RBP_GPIO[19] AB9
PL_LEDRGB3_G AH6 SERVO[3] Y13 JAB_[4] F10 RBP_GPIO[20] AA10
PL_LEDRGB3_B AG5 JAB_[5] F11 RBP_GPIO[21] Y9
Grove PL (LVCMOS33) RBP_GPIO[22] AH13
Switches (LVCMOS12) PL_GRV_[0] AE14 RBP_GPIO[23] AG13
PL_USER_SW0 AB1 PL_GRV_[1] AE13 RBP_GPIO[24] AF12
PL_USER_SW1 AF1 PL_GRV_[2] AD15 RBP_GPIO[25] AF11
PL_USER_SW2 AE3 PL_GRV_[3] AD14 RBP_GPIO[26] AA8
PL_USER_SW3 AC2 RBP_GPIO[27] AH14
PL_USER_SW4 AC1 Camera (LVCMOS12)
PL_USER_SW5 AD6 CAM0_LN0_P AG3
PL_USER_SW6 AD1 CAM0_LN0_N AH3
PL_USER_SW7 AD2 CAM0_LN1_P AG4
CAM0_LN1_N AH4
Pushbuttons (LVCMOS33) CAM0_CLK_P AD5
PL_USER_PB0 AB6 CAM0_CLK_N AD4
PL_USER_PB1 AB7 CAM0_SCL K14
PL_USER_PB2 AB2 CAM0_SDA L14
PL_USER_PB3 AC6 CAM0_PWUP J14