ECE-2002

Computer Organization and Architecture

Dr. Debanjali Sarkar

School of Electronics Engineering, VIT-AP
 Micro-Operation

➢Execution of a program consists of a sequence of instruction cycles.

➢Each instruction executed during an instruction cycle made up of
shorter sub-cycles (fetch, indirect, execute, interrupt).
➢The performance of each sub-cycle involves one or more shorter
operations, that is, micro-operations.
 Instruction Cycle

➢Registers involved in each Instruction Cycle:

• Memory Address Register (MAR): It holds the address of the
location to be accessed from memory.
• Memory Buffer Register (MBR): It contains data to be written
into or to be read out from the addressed location.
• Program Counter (PC): It contains the memory address of the
next instruction to be fetched.
• Instruction Register (IR): It holds the current instruction fetched.
Instruction Cycle
 Fetch Cycle
➢At the beginning of the fetch cycle, the address of the next instruction to
be executed is in the Program Counter(PC).

➢Step 1: The address in the program counter is moved to the MAR

 Fetch Cycle
➢Step 2:
• The address in MAR is placed on the address bus, now the control unit
issues a READ command on the control bus, and the result appears
on the data bus and is then copied into the MBR.
• PC is incremented by one, to get ready for the next instruction.
(These two action can be performed simultaneously to save time)
 Fetch Cycle
➢Step 3: The content of the MBR is moved to the IR.
 Fetch Cycle
➢A simple Fetch Cycle consist of four micro-operations. Symbolically,
we can write these sequence of events as follows:-

➢Here ‘I’ is the instruction length. The notations (t1, t2, t3) represents
successive time units.
• First time unit: Move the contents of the PC to MAR.
• Second time unit: Move contents of memory location specified by
MAR to MBR. Increment content of PC by I.
• Third time unit: Move contents of MBR to IR.
 Indirect Cycle

➢Once an instruction is fetched, the next step is to fetch source

operands (for indirect addressing).

➢Step 1: The address field of the instruction is transferred to the MAR.

This is used to fetch the address of the operand.
➢Step 2: The data is fetched and stored in MBR.
➢Step 3: The address field of the IR is updated from the MBR.
 Execute Cycle
➢Consider an add instruction:
➢Here, this instruction adds the content of location X to register R.
Corresponding micro-operation will be:-

➢We begin with the IR containing the ADD instruction.

➢Step 1: The address portion of IR is loaded into the MAR.
➢Step 2: The data is fetched and stored in MBR.
➢Step 3: Now, the contents of R and MBR are added by the ALU.
 Interrupt Cycle
➢At the completion of the Execute Cycle, if an enabled interrupt has
occurred then Interrupt Cycle occurs.

➢Step 1: Contents of the PC is transferred to the MBR (so that they can
be saved for return).
➢Step 2: MAR is loaded with the address at which the contents of the PC
are to be saved.
➢PC is loaded with the address of the start of the interrupt-routine.
➢Step 3: MBR, containing the old value of PC, is stored in memory.
 Instruction Cycle

➢Till now we have seen each phase (fetch, indirect, and interrupt
cycles) decomposed into sequence of elementary micro-operations
➢Complete instruction cycle: Need to tie sequences together
➢Assume new 2-bit register called Instruction cycle code (ICC) which
designates the state of the processor
• 00: Fetch
• 01: Indirect
• 10: Execute
• 11: Interrupt
 Instruction Cycle

01

00: Fetch
01: Indirect
10: Execute
11: Interrupt
 Write the Micro-operations for each instruction

MOV R1, 25H ADD R1, 25H

MAR <- PC MAR <- PC

MBR <- MEMORY MBR <- MEMORY
PC <- PC + 1 PC <- PC + 1
IR <- MBR IR <- MBR
R1 <- 25H R1 <- R1+ 25H
 Write the Micro-operations for each instruction

LOAD 25H ADD 25H

MAR <- PC MAR <- PC

MBR <- MEMORY MBR <- MEMORY
PC <- PC + 1 PC <- PC + 1
IR <- MBR IR <- MBR
AC <- 25H AC <- AC+ 25H
Write the Micro-operations for each instruction

MOV R1, R2 ADD R1, R2

MAR <- PC MAR <- PC

MBR <- MEMORY MBR <- MEMORY
PC <- PC + 1 PC <- PC + 1
IR <- MBR IR <- MBR
R1 <- R2 R1 <- R1 + R2
 Write the Micro-operations for each instruction

MOV R1, [2000H] ADD R1, [2000H]

MAR <- PC MAR <- PC

MBR <- MEMORY MBR <- MEMORY
PC <- PC + 1 PC <- PC + 1
IR <- MBR IR <- MBR
MAR <- IR(2000H) MAR <- IR(2000H)
MBR <- MEMORY ([2000H]) MBR <- MEMORY ([2000H])
R1 <- MBR R1 <- R1 + MBR
 Write the Micro-operations for each instruction

LOAD [2000H] ADD [2000H]

MAR <- PC MAR <- PC

MBR <- MEMORY MBR <- MEMORY
PC <- PC + 1 PC <- PC + 1
IR <- MBR IR <- MBR
MAR <- IR(2000H) MAR <- IR(2000H)
MBR <- MEMORY ([2000H]) MBR <- MEMORY ([2000H])
AC <- MBR AC <- AC + MBR
 Write the Micro-operations for each instruction

MOV R1, [R2] ADD R1, [R2]

MAR <- PC MAR <- PC

MBR <- MEMORY MBR <- MEMORY
PC <- PC + 1 PC <- PC + 1
IR <- MBR IR <- MBR
MAR <- R2 MAR <- R2
MBR <- MEMORY ([R2]) MBR <- MEMORY ([R2])
R1 <- MBR R1 <- R1 + MBR
 Write the Micro-operations for each instruction

STC CLC

MAR <- PC MAR <- PC

MBR <- MEMORY MBR <- MEMORY
PC <- PC + 1 PC <- PC + 1
IR <- MBR IR <- MBR
CF <- 1 CF <- 0
 Control Unit
➢The control unit performs two basic tasks:
• Sequencing: The control unit causes the processor to step
through a series of micro-operations in the proper sequence,
based on the program being executed.
• Execution: The control unit causes each micro-operation to be
performed.
➢ Implementation of Control unit is broadly of two types
• Hardwired implementation
• Microprogrammed implementation
Hardwired Control Unit
 Control Unit

➢The inputs are:

Clock: The control unit causes one micro-operation (or a set of simultaneous
micro-operations) to be performed for each clock pulse.
 Control Unit

Instruction register: The opcode and addressing mode of the current instruction
are used to determine which micro-operations to perform during the execute
cycle.
Flags: These are needed by the control unit to determine the status of the
processor and the outcome of previous ALU operations.
Control signals from control bus: The control bus portion of the system bus
provides signals to the control unit.
 Control Unit

➢ The outputs are :

Control signals within the processor: These are two types:
1. Data Movement Control Signals- These signals control the transfer of data
between different parts of the processor, like registers, and memory.
2. ALU Control Signals- These signals control the operations performed by the
ALU
 Control Unit

Control signals to control bus: These are also of two types: control signals to
memory, and control signals to the I/O modules.
 Example- Fetch Cycle

How control signal is used for fetch cycle

• MAR <- PC
• Control unit activates signal to open gates between PC and MAR
• MBR <- memory
• Control unit activates signal to open gates between MAR and address
bus
• Control unit activates Memory read control signal
• Control unit activates signal to open gates between data bus and MBR
• PC <- PC+1
• Control unit activates signal to logic that add 1 to the contents of PC
• IR <- MBR
• Control unit activates signal to open gates between MBR and IR
Data Paths, Micro-operations and Control Signals
 Control Unit with Decoded Inputs
➢Different control signals for different instructions
➢To simplify, unique logic input for each opcode

Decoder: n binary inputs

and 2^n binary outputs
 Example
• For each control signal, to derive a Boolean expression of that signal as a
function of the inputs
• Let us consider a single control signal, C5, which causes data to be read from
the external data bus into the MBR
• Let us define two new control signals,
P and Q, that have the
following interpretation:
PQ = 00 Fetch Cycle
PQ = 01 Indirect Cycle
PQ = 10 Execute Cycle
PQ = 11 Interrupt Cycle
 Example
• Then C5 can be defined using the
Boolean expression as:

• That is, the control signal C5 will

be asserted during the second
time unit of both the fetch and
indirect cycles.

PQ = 00 Fetch Cycle
PQ = 01 Indirect Cycle
PQ = 10 Execute Cycle
PQ = 11 Interrupt Cycle
 Example

Identify the control

signals for Load
[2000H]. Write the
corresponding Boolean
Expressions for each
control signal and
realise the Boolean
expressions using
Logic Gates.
 Example

LOAD [2000H]

T1-MAR <- PC
T2-MBR <- MEMORY
PC <- PC + 1
T3-IR <- MBR

T1-MAR <- IR(2000H)

T2-MBR <- MEMORY ([2000H])

T1-AC <- MBR

Example
 Micro Program

➢A program is a set of instructions. An instruction requires a set of micro-

operations.
➢Micro-operations are performed using control signals.
➢Instead of generating the control signals by hardware, here, these control
signals are generated using micro-instructions.
➢This means every instruction requires a set of micro-instructions
➢A set of micro-instructions are called micro-program.
➢Microprograms for all instructions are stored in a small memory called
control memory.
➢The control memory is present inside the processor.
 Micro-Instructions
➢A microinstruction format includes 20 bits in total.

➢F1, F2, F3 are the micro-operation fields. They determine micro-operations

for the computer.
➢CD is the condition for branching. They choose the status bit conditions
(e.g., Zero, Carry, Overflow flags)
➢BR is the branch field. It determines the type of branch (Unconditional,
Conditional, etc.)
➢AD is the address of the next microinstruction to be executed
*Each microinstruction can have only three micro-operations, one from each
field.
 Wilkes’ Design for Micro programmed Control Unit

➢Consider an instruction fetched

from the main memory into the
Instruction Register (IR).
➢The processor uses opcode to
identify the address of the first
micro-instruction.
➢That address is loaded into
CMAR (Control Memory Address
Register).
➢CMAR passes the address to
decoder.
 Wilkes’ Design for Micro programmed Control Unit
➢The decoder identifies the
corresponding microinstruction
from the control memory.
➢A microinstruction has two fields:
Control field and Address field.
➢Control field: indicates the control
signal to be generated.
➢Address field: indicates the
address of the next
microinstruction
➢This address is further loaded
into CMAR to fetch the next
instruction.
 Wilkes’ Design for Micro programmed Control Unit
➢For a conditional microinstruction,
there are two address fields, as
the address of the next
microinstruction depends on the
condition (true or false).
 Wilkes’ Design for Micro programmed Control Unit

Address of Address of
current Control signal next
instruction instruction
000 C0, C1, C4, C7 001
001 C0, C3, C5, C6 101
000 010 C2, C4 001
001
011 C1, C2, C4, C6 010/101
010

011
100 C0, C3, C7 101
100 101 C0, C4, C5 100
101
110 C2, C5, C6 001
110

111
111 C1, C3, C4, C6 011
 Wilkes’ Design for Micro programmed Control Unit

Address of Control Address of

current signal next
instruction instruction

000
001
000
001 010
010 011
011
100
100

101 101
110 110
111
111
Actual Microprogrammed control unit
➢Instruction fetched from the
main memory into IR.
➢The processor uses opcode to
identify the address of the first
micro-instruction.
➢That address is loaded into
Micro PC.
➢Corresponding microinstruction
is fetched from control memory.
➢Micro PC- holds address of
next microinstruction
➢Incrementor- Increment PC
after every microinstruction
Actual Microprogrammed control unit
➢Once microinstruction is
fetched from the control
memory, it generates control
signals.
➢Branch Address- in case of
jump microinstructions
➢Branch Condition- in case of
jump with conditions
microinstructions
➢Conditions are selected
based on status flags
through Mux.
➢If condition is true, load
branch address to Micro PC.
Micro-Instruction Format
Micro-Instruction Format
 Nano-Programming

➢Horizontal micro-instructions can produce multiple control signals

simultaneously but are very wide. This makes the control memory very
large.
➢Vertical micro-instructions are narrow, but after decoding, only produce
one control signal. This makes the control memory small, but the
execution is slow since decoding is needed.
➢Hence, a combination of both techniques is needed to be called nano
programming.
 Nano-Programming

➢Instruction fetched from the main memory into IR.

➢The processor uses opcode to identify the address of the micro-instruction.
➢That address is loaded into Micro PC.
➢Corresponding microinstruction is fetched from control memory and given to
micro IR.
 Nano-Programming

➢Since the microinstruction is in vertical form it has to be decoded.

➢The decoded output loads a new address in nPC (nano PC).
➢ Using this address, nano-instruction is fetched from the nCM into nIR.
➢Since the instruction is in horizontal form, it can directly generate control
signals.