Quick Guide supportnet.mentor.com Questa SIM 10.

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Questa SIM 10.4 SUPPORT Quick Guide

Key Commands do vcd dumpports

executes commands contained in a macro file creates a VCD file that captures port driver data
add memory drivers vcd2wlf
opens the specified memory in the MDI frame of the Main window displays in the Main window the current value and scheduled future values translates VCD files into WLF files
add testbrowser for all the drivers of a specified VHDL signal or Verilog net vcom
adds .ucdb files to the Test Management Browser dumplog64 compiles VHDL design units
add watch dumps the contents of the vsim.wlf file in a readable format vcover attribute
adds signals or variables to the Watch window
Quick Guide
echo displays attributes in the currently loaded database
add wave displays a specified message in the Main window vcover merge
adds VHDL signals and variables, and Verilog nets and registers to the edit merges multiple code or functional coverage data files offline
Wave window invokes the editor specified by the EDITOR environment variable vcover ranktest
alias environment ranks the specified input files according to their contribution to cumulative
creates a new Tcl procedure that evaluates the specified commands displays or changes the current dataset and region environment coverage
examine vcover report
examines one or more objects, and displays current values (or the values at reports on multiple code or functional coverage data files offline
SVA & PSL ------
Questa SV/AFV 6.3
a specified previous time) in the Main window vcover stats
assertion active find produces summary statistics from multiple coverage data files
instructs the simulator to report on any active assertion directives at the displays the full pathnames of all objects in the design whose names match vcover testnames
end of simulation (EOS) the name specification you provide displays test names in the current UCDB file loaded
atv log force vdel
enables or disables assertion thread viewing (ATV) for the specified applies stimulus to VHDL signals and Verilog nets deletes a design unit from a specified library
assertion(s) history vdir
assertion count lists the commands executed during the current session lists the contents of a design library
returns the sum of the assertion failure counts for the specified set of next verror
assertion directive instances continues a search; see the search command prints a detailed description of a message number
assertion fail noforce vgencomp
configures fail tracking for SystemVerilog and PSL assertions removes the effect of any active force commands on the selected object writes a Verilog module’s equivalent VHDL component declaration to
assertion pass notepad standard output
configures pass tracking for SystemVerilog and PSL assertions opens a simple text editor view
assertion report printenv opens a QuestaSim window and brings it to the front of the display
produces a textual summary of SystemVerilog and PSL assertion results echoes to the Main window the current names and values of all environment vlib
variables creates a design library
------ profile on vlog
enables runtime profiling of where your simulation is spending its time and compiles Verilog design units and SystemVerilog extensions
change where memory is allocated vmake
modifies the value of a VHDL variable or Verilog register variable property list creates a makefile that can be used to reconstruct the specified library
checkpoint changes one or more properties of the specified signal, net, or register in the vmap
saves the state of your simulation List Window defines a mapping between a logical library name and a directory
compare add property wave vopt
compares signals in a reference design against signals in a test design changes one or more properties of the specified signal, net, or register in the produces an optimized version of your design
configure Wave Window vsim
invokes the List or Wave widget configure command for the current pwd loads a new design into the simulator
default List or Wave window displays the current directory path in the Main window when
qverilog instructs QuestaSim to perform actions when the specified conditions are
COVERAGE ------ compiles, optimizes, and simulates a Verilog or SystemVerilog design in met
one step where
coverage attribute radix displays information about the system environment
displays attributes in the currently loaded database specifies the default radix to be used wlf2log
coverage clear report translates a QuestaSim WLF file to a QuickSim II logfile
clears all coverage data obtained during previous run commands displays the value of all simulator control variables, or the value of any wlf2vcd
vcover diff simulator state variables relevant to the current simulation translates a QuestaSim WLF file to a VCD file
reports the coverage differences between two test runs restart wlfman
coverage file reloads the design elements and resets the simulation time to zero outputs information about or a new WLF file from an existing WLF file
sets the name of the coverage data file to be automatically saved at the restore xml2ucdb
end of simulation restores the state of a simulation that was saved with a checkpoint creates an HTML report of code coverage from a .ucdb file
coverage goal command during the current invocation of vsim
Sets the value of UCDB-wide goals resume RED text = ModelSim SE only.
coverage ranktest resumes execution of a macro file after a pause command or a breakpoint
ranks coverage data according to user-specified tests right
coverage report searches right (next) for signal transitions or values in the specified Wave
produces a textual output of the coverage statistics that have been window
gathered up to this point run
coverage summaryinfo advances the simulation by the specified number of timesteps
prints coverage numbers of the specified coverage types without loading sccom
the entire database compiles SystemC design units
coverage tag sdfcom
adds or removes tags from specified objects compiles SDF files
coverage testnames search
displays test names in the current UCDB file loaded searches the specified window for one or more objects matching
the specified pattern(s)
------ seetime
scrolls the List or Wave window to make the specified time visible
delete ucdb2html
removes objects from either the List or Wave window converts a .ucdb file into HTML
 www.mentor.com/training_and_services www.mentor.com/products/fv/abv Questa SIM 10.4
TRAINING PRODUCTS Quick Guide

Key Command Arguments VOPT Code Coverage

Use <command> -help for a full list. Design optimization options Key Arguments to vcom/vlog
1. Optimized designs simulate faster, while non-optimized designs provide +cover=bcefsx Specifies coverage type(s)
QVERILOG object visibility for debugging.
2. Use +acc with vopt or vsim -voptargs with +acc for selective design object Key Arguments to vopt
The qverilog command compiles, optimizes, and simulates Verilog and Quick Guide
visibility during debugging. +cover=bcefsx Specifies coverage type(s)
SystemVerilog designs in a single step. 3. Read “Optimizing Designs with vopt” in the User’s Manual for additional -nocover Disable coverage on all source files
1. automatic work library creation information. Key Arguments to vsim
2. support for all standard vlog arguments
-coverage Enables statistics collection
3. support for C/C++ files via the SystemVerilog DPI Key arguments to vopt
4. implicit “run -all; quit” unless using -i, -gui, -do (see -R below) -o <name> Optimized design name
5. vopt performance invoked (see the vopt section of this guide) <design> Top-level design unit SVA & PSL
[+acc=[<spec>]+[<module>]] Enable design object visibility
Key arguments to qverilog
<filename> Verilog source code file to compile, one is
Questa SV/AFV 6.3
+cover=bcefsx Specifies coverage type(s) Key arguments to vcom and vlog
-nocover Disable coverage on all source files [-pslfile <file>] External PSL file
required -g Assigns a value to generics and parameters with no value [-nopsl] Ignore embedded PSL assertions
[-R <sim_options>] vsim command options applied to simulation -G Forces value assignment for generics and parameters Key arguments to vsim
Key arguments to vsim [-nopsl] Ignore embedded PSL assertions
SCCOM
[-vopt] Run vopt if not automatically invoked [-nosva] Ignore SystemVerilog concurrent assertions
-link Links source code, required [-voptargs=”<args>”] Arguments passed to vopt, use +acc args for
[CPP option] C++ compiler option Key modelsim.ini variables
design visibility AssertionFail* Control assertion failure behavior
[-g] Compile with debugging info
-vv Echo subprocess invocations on stdout AssertionFormat* Define messages for VHDL assertion types
VSIM AssertionPass* Control assertion pass behavior
[-scv] Includes SystemC verification library
[-assertdebug] Keep data for debugging assertion failures BreakOnAssertion Stop the simulator after assertion message
<filename(s)> SystemC files to be compiled
[-assertfile <filename>] Alternative file for recording assert messages Cover* Control cover directive behavior
[-assume] Simulate PSL and Verilog assume directives same as IgnoreSVA* Control SVA message logging
VCOM Sv_Seed Seed random number generator
assert directives
[-2008 | -2002 | -93 |-87] Choose VHDL 2008, 2002,1993, or 1987 [-c ] Run in cmd line mode
[-check_synthesis] Turn on synthesis checker [-coverage] Invoke Code Coverage
[-debugVA] Print VITAL opt status
Wave Window
[-do “cmd” | <file>] Run cmd or file at startup
[-explicit] Resolve ambiguous overloads [-elab] Create elaboration file add wave <item> Wave specific signals/nets
[-help] Display vcom syntax help [-f <filename>] Pass in args from file add wave * Wave signals/nets in scope
[-f <filename>] Pass in arguments from file [-g|G<name=value>] Set VHDL Generic values add wave -r /* Wave all signals/nets in design
[-norangecheck] Disable run time range checks [-hazards] Enable hazard checking add wave abus(31:15) Wave a slice of a bus
[-nodebug] Hide internal variables & structure [-help] Display vsim syntax help view wave Display wave window
[-novitalcheck] Disable VITAL95 checking [-l <logfile>] Save transcript to log file view wave -new Display additional wave window
[-nowarn <#>] Disable individual warning msg [-load_elab] Simulate an elaboration file write wave Print wave window to file
[-quiet] Disable loading messages [-noassume] Do not simulate PSL and Verilog assume directives <left mouse button> Select signal / Place cursor
[-refresh] Regenerate library image [-nopsl] Disable PSL assertions <middle mouse button> Zoom options
[-version] Returns vcom version [-nosva] Disable System Verilog concurrent assertions <right mouse button> Context Menu
[-work <libname>] Specify work library [+notimingchecks] Disable timing checks <ctrl-f> Find next item
<filename(s)> VHDL file(s) to be compiled [-quiet] Disable loading messages <tab> (go right) Search forward for next edge
[-restore <filename>] Restore a simulation <shift-tab> (go left) Search backward for next edge
VLOG [-sdf{min|typ|max} <region>=<sdffile>] Apply SDF timing data e.g., i or + | o or - Zoom in | Zoom out
[-vlog95compat] Disable Verilog 2001 keywords sdfmin /top=MySDF.txt f | l Zoom full | Zoom Last
[-compat] Disable event order optimizations [-sdfnowarn] Disable SDF warnings Key modelsim.ini variables
[-f <filename>] Pass in arguments from file [-sv_seed <seed>] Specify a seed for the Random Number WLF* Waveform management variables
[-hazards] Enable run-time hazard checking Generator of the root thread WLFCacheSize Change default or disable WLF file cache
[-help] Display vlog syntax help [-t [<mult>]<unit>] Time resolution
[-nodebug] Hide internal variables & structure [-vcdstim [<instance>=]<filename>] Stimulate the top-level design or RED text = ModelSim SE only.
[-quiet] Disable loading messages instances from an Extended VCD file
[-R <simargs>] Invoke VSIM after compile [-version] Returns vsim version
[-refresh] Regenerate lib to current version [-vopt] Run vopt automatically
[-sv] Enables SystemVerilog keywords [-voptargs=”<args>”] Arguments to pass to vopt
[-version] Returns vlog version [-view <filename>] Log file for VSIM to view
[-v <library_file>] Specify Verilog source library [-wlf <filename>] Log file to create
[-work <libname>] Specify work library [<libname>.<design_unit> Configuration, Module, Entity/Arch, or
<filename(s)> Verilog file(s) to be compiled optimized design to simulate
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[-wlfcachesize] Specify WLF reader cache size (per WLF file.)
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[-wlfslim <size>] Specify the number of Megabytes to be saved in
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event log file
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[-wlftlim <duration>] Specify the duration of time to be saved in
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event log file
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