Teaching Top-down Design Using VHDL and CPLD

Morris Chang
Computer Engineering Program
Department of Computer Science
st
Illinois Institute of Technology, 10 west 31 street
Chicago, IL 60616
Internet: [email protected]

designers. Today, system-level logic design is most likely

Abstract a team work, forcing modular and hierarchical design
approach. Moreover, exploiting many technology
This paper presents a teaching experience in using (implementation) options without translation of the
VHDL and CPLD in the senior digital design course. The source design description is an increasingly important
course focus on teaching the top-down design requirement. The IEEE-standard (i.e. IEEE-1076) VHDL
methodology through hands-on experiments. The language addresses these needs.
industrial available tools — Maxplus2, made possible
through Altera’s University Program, provide our
VHDL can be used to describe hardware from the
students a smooth transition from academic concepts to
abstract to the concrete level. Many of the EDA
industrial practice. VHDL, the industrial standard
(Electronic Design Automation) vendors are
language (IEEE-1076), is used as the design entry. Thus,
standardizing on VHDL as input and output from their
the students are forced to learn the practical aspect of
tools. These tools include simulation tools, synthesis
writing a synthesizable VHDL code. The hands-on weekly
tools, layout tools, testing tools, etc. Due to the recent
projects are exercised on the integrated CPLD design
advances in high-level synthesis tools, the text-based
tool which has VHDL compiler, logic synthesizer,
design entry has gained increasing popularity in the
functional and timing simulator, floor plan editor and
ASIC design. In our senior design course, we introduce
programmer. With the help of programmable devices,
VHDL as the design entry in the CPLD design
students can bypass the waiting period for IC fabrication
environment. This course focuses on how to write VHDL
and obtain ASIC designs after the devices have been
code that can be processed by synthesis tools [2].
programmed.

The course begins with a brief summary of the

The VHDL design entry in Maxplus2 is ideal for
syntax of VHDL and is followed by several examples of
teaching top-down design methodology. Translating from
a given Algorithmic State Machine (ASM) chart to a hardware modelling. The examples include simple
synthesizable and efficient VHDL code is presented. combinational logic, sequential models and finite state
Exploiting the VHDL constructs to make a design machines. Applications of VHDL to top down design
reusable is demonstrated through examples. In this methodology are presented. Specific design trade-offs in
course, students learn how to partition a complex design CPLD for performance and efficiency are also discussed.
into small components and focus on higher level of
abstraction and hierarchy in design description which We employ the industry standard language,
have become desirable to digital systems designers. VHDL, and a commercially available CAD tool
(Maxplus2[1] from Altera) in a set of hands-on weekly
Introduction laboratory experiments. These labs, in concert with a
semester design project, provide our students with a
In recent years, CPLDs (Complex Programmable smooth transition from the abstractions of academe to the
Logic Devices) have increased dramatically in capacity realities of engineering practice.
and complexity. CPLDs with 100K gates are available in
today’s technology. To cope with the complex design,
higher level of abstraction and hierarchy in design
description have become desirable to digital systems
Course Description

Following topics are addressed in this senior

design course.
1. Introduction to the syntax and basic structure of J
VHDL— data types, operators; signal assignments;
components instantiation; modeling styles:
behavioral, dataflow and structural; subprograms; K
packaging parts and utilities. X, Y
2. The synthesizable issues under current technology— F
register (latches) inference; state machines. F
A B
3. The VHDL portability issues in the synthesis tools. T L T
4. Introduction to the architecture ofCPLDs.
5. Design trade-offs in CPLD. X
6. Labs on: design, verification, synthesis, timing
F
simulation and program CPLDs. B JW
7. Lab assignments: multiplexor, adder, decoder/encoder, T M N
round-up circuit, multiplier, counter/shift registers,
W Y
Finite State Machine, digital comparator, Arithmetic
and Logic Unit, and a simple microprocessor. 1, - 0, 0
B, C
The top-down designs that exploiting the 0, 1
VHDL
The VHDL design entry in Maxplus2 is ideal for
teaching top-down design methodology. Instead of
emphasizes the microscopic gate aspects of the digital conditional state with its name conditional
branch enclosed in a circle output
design, we emphasize a macroscopic view of digital
systems by starting from the original problem. This result
in a top-down approach to design. Once the problem is This ASM can be implemented as following VHDL
analyzed and partitioned to a further design, students can code.
focus on the design aspect and exploit the logic synthesis
-- This example shows how to translate a given ASM chart to VHDL
tool for the minimization and implementation details. In -- The filename: asm2.vhd
this section, we will show two type of top-down design -- Note: the a, b and c are asynchronous inputs.
examples that would fit well into the VHDL design. -- Author: M. Chang (Illinois Institute of Technology)

entity asm2 is -- Specify the inputs and outputs

port( clock, reset, a, b, c :IN bit;
ASM chart to VHDL x_out, y_out, w_out :OUT bit ;
state :OUT bit_vector(4downto 0)
-- output the state variables for testing
Algorithmic State Machine (ASM) chart [4] has );
been used to describe the finite state machine for more end asm2;
than two decades. The ASM chart can be used to describe architecturestatemach of asm2 is
either Mealy machine or Moore machine of traditional type state_type is (j,k,l,m,n);
sequential circuit theory. An ASM with only signal mstate, next_state :state_type;
-- initial state is j
unconditional outputs is equivalent the traditional Moore begin
machine; the traditional mealy machine has conditional state_register: process( clock,reset)
outputs. begin
if reset = ‘1’ then
mstate <= j;
Translating a given ASM chart into a synthesizable elsif clock’event and clock = ‘1’ then
VHDL code can be done in a systematic fashion. The mstate <= next_state;
end if;
next figure presents a simple ASM chart. In this ASM, end process;
there are five states, namely J, K, L, M and N; three
inputs: A, B, and C; three outputs: W, X, and Y. state_logic: process(mstate,a,b,c)
begin bit adder. Such approach also results in a reusable
x_out<= ‘0’;
y_out <= ‘0’; design.
w_out <= ‘0’;
CASE mstate IS
WHEN j =>
However, some of the cases can be less intuitive
next_state<= k; than the adder. The digital comparator which can be
WHEN k => found in [3] is one of such cases. The students need to
x_out <= ‘1’; know the detail algorithm that employs N 1-bit
y_out <= ‘1’;
IF a = ‘1’ THEN comparators in a “message passing” fashion.
next_state<= l;
ELSIF (a = ‘0’ and b = ‘1’) THEN
next_state<= n; One of our favorite examples is a round-up system.
w_out <= ‘1’; This system should round up a given n-bit binary data (as
ELSIF (a = ‘0’ and b = ‘0’) THEN input) to its next higher binary data (as output) which is
next_state<= n;
END IF;
2N. Example (in decimal):
WHEN l => input output
x_out <= ‘1’; _____________________________
IF b = ‘0’ THEN w_out <= ‘1’; 0 0 (a special case)
else w_out <= ‘0’; end if; 1 1
IF b = ‘1’ THEN 2 2
next_state<= m; 5 8
ELSE 31 32
next_state<= n; 58 64
END IF; … …
WHEN m =>
w_out <= ‘1’; It is worth noting that this system will need n+1 bits
IF b = ‘1’ THEN
next_state<= m; output for the input with n bits. Students are asked to
ELSIF ( b = ‘0’ and c = ‘1’) THEN come up an algorithm (a combinatorial one is preferred)
next_state<= k; and partition it into small components. Again, the design
ELSIF ( b = ‘0’ and c = ‘0’) THEN
next_state<= j; is asked to be a reusable one that can be customized
END IF; easily for any length of the data. With an approach that
WHEN n => similar to the comparator, students can quickly see the
next_state<= m;
y_out <= ‘1’; advantages of using VHDL in digital design (verse the
END CASE; Boolean expression.)
END process;

with mstate select A simple VHDL design (not optimized one) for the
state <= “00001” when j, 4-bit round-up system is described in the next figure.
“00010” when k, This design takes similar approach as the digital
“00100” when l,
“01000” when m, comparator described earlier. A one-bit round-up system
“10000” when n; (i.e. the roundup entity) is designed first. Then, a
END statemach; structural architecture, which takes advantage of VHDL
construct — generate and constant, is implemented (i.e.
This VHDL code has two processes; one for the
rndup_n entity). A 4-bit design using a Boolean
registers and one for the combinatorial logic. The state
expression is also included for comparison. Apparently, it
encoding is decoded and connected to output ports for
would be much difficult and error prone to design a 32-
testing purpose.
bit case by using the Boolean expression approach.
System level partition Leading0_in
Bit_in leading0_in : all the leading bits
Any1_out are “0s”
Leading0_out
Partition a complex design into small components Set1_out One-bit Any1_in any1_in: at least one of the
allows students to focus on higher level of abstraction round-up trailing bits is “1”
Set1_in
set1_out: the current bit is
and hierarchy in design description which have become requesting the next
bit_out
desirable to digital systems designers. For instance, an 8- higher order bit to set its
bit ripple adder can be implemented by a cascade of 8 b_in(3) b_in(2) b_in(1)b_in(0)
bit_out to “1”
full-adder stages. The VHDL generate statement can
instantiate small components (e.g. 1-bit full adder) in an
iterative fashion. In addition, using the VHDL constant
declaration this 8-bit adder can be modified easily to a n-
b_out(3) b_out(1)
b_out(2) b_out(0)
b_out(4)
 b_out(3) = b_in(3)•b_in(2)’•b_in(1)’•b_in(0)’
+ b_in(3)’•b_in(2)•( b_in(1) + b_in(0))
b_out(4) = b_in(3)•(b_in(2) + b_in(1) + b_in(0))

-- Author: MorrisChang (Illinois Institute of Technology) Conclusions

-- Basic cell for round-up circuit

entity roundup is Using commercially available VHDL tool to design

port( bit_in, set1_in, any1_in,leading0_in: in BIT; CPLD in a senior design course has following advantages
bit_out,set1_out, any1_out, leading0_out: out BIT); for our students:
end roundup;
• to have a quick turn around time for their design;
architecturedataflow of roundup is students can bypass the waiting period for IC
begin
bit_out <= leading0_in and ((set1_in and not
bit_in) or fabrication and obtain ASIC designs after the
(bit_in and not any1_in)); devices have been programmed.
set1_out <= bit_in and any1_in; • to focus on the top-down design methodology;
any1_out <= any1_in orbit_in;
leading0_out <= leading0_in and notbit_in; students can leave the minimization and detail
end dataflow; implementations to logic synthesizer.
• to gain an edge in the job marketplace; students
----------------------------------------------------------------
-- Round up system learn the practical aspect of writing a
entity rndup_n is synthesizable VHDL code through hands-on
port (b_in : in bit_vector(3downto 0); projects.
b_out : out bit_vector(4downto 0);
any1_in : in bit :=’0’; -- need external stimulus
set1_in : in bit :=’0’; Maxplus2 supports only a subset (the synthesizable
leading0_in : inbit:= ‘1’; part) of VHDL to be used as CPLD design entry. We plan
leading0_out, any1_out, set1_out : out bit to cover the non-synthesizable part of the VHDL, which
);
end rndup_n; can be used for modelling and simulation, through other
architecture iterative ofrndup_n is VHDL tools.
component roundup portbit_in, ( set1_in, any1_in,leading0_in:in bit;
bit_out,set1_out, any1_out, leading0_ou t:out bit);
end component; Acknowledgments
for all : roundup use entity work roundup( dataflow);
constant n : integer := 4; The University Program at Altera Corporation
signal set1_im, any1_im, leading0_im:bit_vector(0 to n); provides us Maxplus2-VHDL and hardware at Rochester
begin Institute of Technology and Illinois Institute of
b0: roundup port map b( _in(0), set1_in, any1_in,leading0_im(0), Technology. Partial support for this work was provided
b_out(0), set1_im(0),any1_im(0),leading0_out); by the National Science Foundation’s Division of
bn_1: roundup port map b_in(n-1),
( set1_im(n-2), any1_im(n-2),
leading0_in,b_out(n-1), set1_im(n-1),any1_out, Undergraduate Education through grant DUE-9650347.
leading0_im(n-1-1));
b_out(n) <= set1_im(n-1); References
set1_out <= set1_im(n-1);
b_rest: fori in 1 to n-2 generate [1] Altera MAXPLUS II— VHDL manual, 1994,Altera.
rest: roundup port map b_in(i),
( set1_im(i-1), any1_im(i-1),
leading0_im(i), b_out(i), set1_im(i),any1_im(i), [2] M. Chang, “From VHDL to CPLD — a Synthesizable Journey,”
leading0_im(i-1)); one-day tutorial workshop, IEEE International ASIC Conference,
end generate; Austin, Texas, Sept. 21, 1995.
end iterative;
[3] Z. Navabi, “VHDL: Analysis and Modeling of Digital Systems”,
1993, McGraw-Hill.
The Boolean expression approach
:
[4] Franklin Prosser and David Winkel, “The Art of Digital Design —
b_out(0) = b_in(3)’•b_in(2)’•b_in(1)’•b_in(0) An Introduction to Top-Down Design,” second edition, Prentice-
b_out(1) = b_in(3)’•b_in(2)’•b_in(1)•b_in(0)’ Hall, 1987
b_out(2) = b_in(3)’•b_in(2)•b_in(1)’•b_in(0)’
+ b_in(3)’•b_in(2)’•b_in(1)•b_in(0)