MICROPROCESSOR ARCHITECTURE

Pin Diagram of INTEL 8085:-

BLOCK DIAGRAM OF INTEL 8085:-

Pin Description:-
X1, X2 (INPUTS):- X1 and X2 are connected to a crystal, LC or RC network to drive the internal clock
generator. X1 can also be an external clock input from a logic gate. The input frequency is divided by 2 to
give the processors internal operation frequency.

RESET OUT (OUTPUT):- It indicates CPU is being reset can be used as a system reset. The signal is
synchronized to the processor clock and lasts an integral number of clocks periods.

SOD (OUTPUT):- Serial output data line. The o/p SOD is set or reset as specified by the SIM
instruction.

SID (INPTU):- Serial input data line. The data on this line is loaded onto accumulator bit 7 whenever a
RIM instruction is executed.

TRAP (INPUT):- It is a non- mask able restart interrupt. It’s recognized at the same time as INTR or
RST 5.5, RST 6.5, RST 7.5. It is unaffected by any mask or interrupt enables. It has the highest priority
of any interrupt.

RST 5.5, 6.5, 7.5 (INPUTS):- Restart interrupts. These three inputs have the same timing as INTR. In
addition, they may be individually masked out using the SIM instruction.

INTR (INPUTS):- Its interrupt request signal. Among interrupts it has the lowest priority. When it goes
high the program counter doesn’t increments its content. The microprocessor suspends its normal
sequence of instructions. After completing the instruction at hand it goes to CALL instructions. The
INTR line is sampled in the last stage of the M/C cycle of an instruction. The microprocessor
acknowledges the interrupts signal and issue an INTA signal. The INTR is enabled or disabled by
software. An interrupts is used by I/O devices to transfer data to the microprocessor without wasting its
time.

INTA (OUTPUT):- Interrupts acknowledge is used instead of R͞ D during the instruction cycle after
an INTR is accepted. It can be used to activate the 8259 interrupts chip or some other interrupts parts.

AD0- AD7 (Inputs/Output)(3 stage):- Multiplexed address/data us: lower 8 bit of the memory address
(or I/O address) appear on the bus during the first clock cycle of the M/C cycle. It then becomes the data
bus during the second and third clock cycle.

Vcc: - Input +5V D.C

GND or Vss:- Grounding

A8 – A15 (Output, 3-stage):- Address bus: the most significant 8 bits of the memory address or I/O
address, 3 staged during HOLD and HALT modes and during RESET.

S0 (29), S1 (33) and IO/M͞͞ (34)(OUTPUTS):-

Machine cycle status table:-

 IO/M͞ S1 S0 STATUS
0 0 1 Memory write
0 1 0 Memory read
1 0 1 I/O write
1 1 0 I/O read
0 1 1 Opcode fetch
1 1 1 Interrupt acknowledge
. 0 0 Halt
. X X Hold
. X X Reset
Note: - . → 3 state (high impedance) & X→ Unspecified
S1 can be used as an advanced R/W͞ status. IO/M͞ , S0 & S1 becomes valid at the beginning of an m/c cycle
and remains unchanged (stable) throughout the cycle. The falling edge of ALE may be used to latch the
state of these lines.

ALE (Output):- Address latch enable: It occurs during the first clock state of a machine cycle and
enables the address to get latched into the on-chip latch of peripherals. The falling edge of the ALE is set
to guarantee setup and hold times for the address information. The falling edge of ALE can also be used
to stroke the status information. ALE is never tri-stated.

W͞ R (Output, 3-state):- A low level on W͞ R indicates the data on the data bus is to be written into the
selected memory or I/O location. Data is setup at the trailing edge of W͞ R. 3 stated during HOLD &
HALT modes and during RESET.

R͞ D (Output, 3-state):- A low level on R͞ D indicates the selected memory or I/O devices are to be read
and that the data bus is available for the data transfer. 3-stated during HOLD & HALT modes and during
RESET.

READY (Inputs):-If READY is high during a read or write cycle, it indicates that the memory or
peripheral is ready to send or receive data. If READY is low, the CPU will wait an integral number of
clocks cycle for READY to go high before completing the read or write cycle. READY must confirm to
specified setup and hold times.

R͞ E͞ S͞ E͞ T͞ I͞ N͞ (Input):- Sets the program counter to zero and resets the interrupt enable and HLDA flip-
flops. The data and address buses and the control lines are 3-stated during reset because of the
asynchronous nature of reset the processors internal register and flags may be altered by reset with
unpredictable results. R͞ E͞ S͞ E͞ T͞ I͞ N is a Schmitt-trigged inputs allowing connection to an RC n/w for
power-on reset delay. The CPU is held in the reset condition as long as R͞ E͞ S͞ E͞ T͞ I͞ N is applied.

CLK (Output):- Clock output for use as a system clock. The period of CLK is twice the X1, X2 inputs
period.

HLDA (Output):- Hold acknowledge indicates that the CPU has received the HOLD request and that it
will relinquish the bus in the next clock cycle. HLDA goes low after the HOLD request is removed. The
CPU takes the bus one half clock cycles after HLDA goes low.
HOLD (Input):- HOLD indicates that another master is requesting the use of the address and data
buses. The CPU upon receiving the hold request will relinquish the use of the bus as soon as the
completions of the current bus transfer. Internal processing can continue. The processor can regain the
bus only after the HOLD is removed. When the HOLD is acknowledged, the address, data, R͞ D, W͞ R &
IO/M͞ lines are tri-stated.

INSTRUCION CYCLE: - An instruction is a command given to the computer to perform a

specified operation on given data. The sequence of instruction written by the programmer to perform a
particular task is called program. Program and data are stored in the memory. The CPU fetches one
instruction from the memory at a time and executes it.

The necessary steps that a CPU carries out to fetch an instruction and necessary data from the memory
and to execute it constitute an instruction cycle

Instruction cycle (IC) =Fetch Cycle (FC) +Execution Cycle (EC)

In the fetch cycle a CPU fetches OPCODE from the memory. The necessary steps which are carried out
to fetch an OPCODE from the memory constitute a fetch cycle.

The necessary steps which are carried out to get if any form memory and to perform the specific
operation specified in an instruction, constitute an execute cycle.

The time required to fetch an OPCODE is a fixed slot of time while the time required to execute an
instruction is variable which depends on the type of the instruction to be executed. The total time required
to execute an instruction is given by:-

IC = FC + EC
FETCH OPERATION: - An instruction may be more than one byte long operand address. The
program counter (PC) keeps the memory address of the next instruction to be executed. In the beginning
of a fetch cycle, the content of the program counter which is the address of the memory location where
OPCODE is available is sent to the memory and the memory places the OPCODE on the data bus so as to
transfer it to the CPU. The entire operation of fetching an OPCODE takes three clock cycles. In case of
slow memory the CPU has to wait till the memory sent the OPCODE. The clock cycle for which the CPU
waits is called wait cycle.

EXEXUTE OPRATION: - The OPCODE fetched from the memory goes to the data register
(DR) and then to instruction register and then goes to decoder circuitry to which decodes the instruction.
The decoder circuitry is within the microprocessor. After the instruction is decoded, execution begins. If
the operand is in the general purpose register, execution is immediately performed. The time taken in
decoding and execution is one clock cycle. If an instruction contains data or operand and address which
are still in the memory, the CPU has to perform some read operation to get the desired data. After
receiving the data it performs executed operation. A red cycle is similar to a fetch cycle. In case of a read
cycle the quantity received from the memory are data or operand address instead of an OPCODE. In some
instruction write operation is performed. In write cycle data are sent from CPU to the memory or output
devices.
MACHINE CYCLE AND STATES: - The necessary steps carried out to perform fetch, a
read or a write operation constitute a machine cycle (M/C). In a M/C one basic operation such as
OPCODE fetch, memory read, memory write, I/O read or I/O write is performed. An instruction cycle
consists of several M/C cycle. The OPCODE is fetched in the first M/C off an instruction cycle. Most of
the single byte instruction requires only one M/C to fetch the OPCODE and execute the instruction. Two
or three bytes instructions require more than one M/C .additional M/C cycles are needed to read data from
or to write data into the memory or I/O devices.

One subdivision of operation performed in one clock cycle is called state or T-state.

INSTRUCTION AND DATA FLOW:-

Two kinds of words namely instruction word and data word are processed during an instruction cycle. At
the beginning of a fetch cycle the contents of the program counter is transferred to a special register
known as Memory address register (MAR) or (AR). The content of the MAR is transferred to the
memory through the address bus. By sending certain control signal to memory the microprocessor also
indicates that it want to read the content of the memory. The decoder circuitry in the memory is activated
and the memory understands what is to be done. Then the memory sends OPCODE to the microprocessor
through the data bus. The OPCODE first comes in memory data register (MDR) or simply (DR). In case
of INTEL 8085 there is a data buffer for this purpose. The operation code is then placed in the instruction
register (IR). The instruction is decoded by instruction decoder and it’s executed. Finally the contents of
the PC are incremented.
The executing of an instruction requires the flow of data words in the most of the instructions. A data
word is received either from the memory or input devices. The data words flows to the processors through
the data bus and is placed in the ACC or any other general purpose register depending on the instruction.
After the execution of and instruction the data is placed in a register or a memory location. After the
execution of a program the result (data) is placed in the memory or sent to output devices. When in MDR
(or DR or data buffer) until the write operation is complete.

ADDRESSING MODES OF 8085 microprocessor: -

Each instruction requires certain data or which it has to operate. The techniques to specify data for
instruction are called Addressing Modes. The INTEL 8085 has the following addressing modes:-

 Direct addressing
 Register addressing
 Register indirect addressing
 Immediate addressing

1. Direct Addressing:- In this mode the address of the operand(data) is given in the instruction
itself.
E.g. STA 2400H, IN 0FH.
2. Register addressing:- In this mode the operands are in the general purpose register.
E.g. MOV A, B, ADD B
3. Register indirect addressing:- In this mode the address of the operand is specified by a register-
pair.
E.g. LXI H, 2500H
 4. Immediate Addressing:- In this mode the operand is specified within the instruction itself.
E.g. MVI A, 05H , ADI 09H
MVI C, 06H , OR 01H
5. Implicit addressing:- There are certain instructions which operates on the content of ACC such
instructions don’t require the address of the operand.
E.g. RAL, RAR, RRC, RLC, CMA…..

Instruction Format

An instruction is a command to the microprocessor to perform a given task on a specified data. Each
instruction has two parts: one is task to be performed, called the operation code (op-code), and the
second is the data to be operated on, called the operand. The operand (or data) can be specified in various
ways. It may include 8-bit (or 16-bit) data, an internal register, a memory location, or 8-bit (or 16-bit)
address. In some instructions, the operand is implicit.

Instruction word size

The 8085 instruction set is classified into the following three groups according to word size:

1. One-word or 1-byte instructions

2. Two-word or 2-byte instructions
3. Three-word or 3-byte instructions

In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor. However,
instructions are commonly referred to in terms of bytes rather than words.

One-Byte Instructions
A 1-byte instruction includes the op-code and operand in the same byte. Operand(s) are internal register
and are coded into the instruction.
For example:

Task Op Operand Binary Hex

code Code Code
Copy the contents of the accumulator in the MOV C,A 0100 1111 4FH
register C.
Add the contents of register B to the contents ADD B 1000 0000 80H
of the accumulator.

Invert (compliment) each bit in the CMA 0010 1111 2FH

accumulator.

These instructions are 1-byte instructions performing three different tasks. In the first instruction, both
operand registers are specified. In the second instruction, the operand B is specified and the accumulator
is assumed. Similarly, in the third instruction, the accumulator is assumed to be the implicit operand.
These instructions are stored in 8bit binary format in memory; each requires one memory location.
Two-Byte Instructions

In a two-byte instruction, the first byte specifies the operation code and the second byte specifies the
operand. Source operand is a data byte immediately following the op-code. For example:

Task Op-code Operand Binary Code Hex Code

Load an 8-bit data MVI A , Data 0011 1110 3E Data First Byte
byte in the Second Byte
accumulator.
DATA

Assume that the data byte is 32H. The assembly language instruction is written as
Mnemonics Hex code
MVI A, 32H 3E 32H
The instruction would require two memory locations to store in memory.

Three-Byte Instructions

In a three-byte instruction, the first byte specifies the op-code, and the following two bytes specify the 16-
bit address. Note that the second byte is the low-order address and the third byte is the high-order address.
Op-code + data byte + data byte

For example:

Task Opcode Operand Binary code Hex Code

Transfer JMP 2085H C3 First byte
the
program 1100 0011
sequence 85 Second Byte
to the 1000 0101
memory
location 0010 0000 20 Third Byte
2085H.

This instruction would require three memory locations to store in memory.

Three byte instructions – op-code + data byte + data byte

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