Floorplan Implimentation:
what is floorplan ?
1. A floorplan is nothing but the arrangement of all the components (such as cells, macros, and
blocks) on a semiconductor chip.
2. It defines the relative positions of these elements to optimize Area, performance, and power while
considering constraints like wire length, congestion, and timing requirements.
3. Floorplanning is a key step in the physical design process.
Steps involved in Floor Planning:
1. Determine core height and breadth to estimate die size.
2. IO pad and port placement.
3. Macro placement
4. Creating voltage area.
5. Adding physical only cells
6. Pre-routing - power planning
All these steps are done at Floorplan by the following commands :
FLOORPLAN BY USING ICC2 SHELL COMMANDS:
Initializing floorplan by estimating die and core utilization :
################## FLOORPLAN ###################
1. initialize_floorplan -control_type die -core_utilization 0.80 -flip_first_row false -use_site_row -
keep_all -core_offset {5} -keep_placement {all macro block io physical_only}
PORT PLACEMENT:
In our design we have 3 different types of ports which will be used for power, clock and all other
signals
1. Input ports
2. Output ports
3. Clock ports
################## PORTS PLACEMENT ##################
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for port placement we can go through this command :
1. create_pin_guide -boundary {{344.8560 418.0910} {354.8560 586.0040}} -pin_spacing 2 -layers
M5 [get_ports -filter "direction == in"]
2. place_pins -ports [get_ports -filter "direction == in"]
3. create_pin_guide -boundary {{709.6880 435.5240} {719.6880 597.5270}} -pin_spacing 2 -layers
M5 [get_ports -filter "direction == out"]
4. place_pins -ports [get_ports -filter "direction == out"]
################# CHECK PORT PLACEMENT ################
we will check pins are alligned properly to the tracks or not !! else we got base drc's
1. check_pin_placement
MACRO PLACEMENT :
what is a macro ?
A macro is referred to a pre-designed, reusable block or module, such as memory, standard cells, or
complex IP (intellectual property) cores, that performs a specific function within a chip. Macros are
typically larger than individual standard cells and are placed and routed as a single unit during
physical design.
Types of macros :-
Hard macros : Hard macros are those in which the circuit is fixed. We are unable to view the macro
functionality details. we know the timing information.
Soft macros : We are able to observe the circuit's functionality and the kind of gates used inside it.
We are also aware of the timing details.
Macro placing guidelines :
⮚Place macros at the edges of the core
⮚Avoid criss-cross connections
⮚Macro pins should be faced toward the centre of the core
⮚Talking macros should be near to each other
⮚Avoid notches
⮚Maintain proper halo around the macros
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Types of macro placement:
⮚Manual macro placement : In this method we need to flylines in GUI and by the lines we
need place the macros in the design by dragging the each macro individually.
⮚Auto placemat : In this method we can use the auto placement command by disabling
standard cells by using app options
################# AUTO FLOORPLAN #############
To place macros acutomatically we should enable this app option .
1. set_app_options -name plan.macro.macro_place_only -value true
2. create_placement -floorplan
################# LIB CELL #########################
To finding lib cell, use this command :
1. get_lib_cells saed32_hvt|saed32_hvt_std/*
2. get_lib_cells saed32_hvt|saed32_hvt_std/DCAP*
################ BOUNDARY AND TAP CELLS ########
1. set cell saed32_hvt|saed32_hvt_std/DCAP_HVT
2. set_boundary_cell_rules -left_boundary_cell $cell -right_boundary_cell $cell -prefix BOUND -
at_va_boundary
3. compile_boundary_cells
4. create_tap_cells -lib_cell $cell -prefix TAP -skip_fixed_cells -at_distance_only -distance 30 -
pattern stagger
################ CHECKS AFTER FLOORPLAN ############
1. check_legality
2. save_block -as YOURNAME
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