Bulletin of Electrical Engineering and Informatics

Vol. 13, No. 2, April 2024, pp. 800~811

ISSN: 2302-9285, DOI: 10.11591/eei.v13i2.4249  800

Design and implementation of pulse width modulation gate

control signals for two-level three-phase inverters

Ezzidin Hassan Aboadla1,2, Kushsairy Kadir1, Sheroz Khan3

1
Electrical Engineering Section, University Kuala Lumpur British Malaysian Institute, Selangor, Malaysia
2
Department of Electrical and Electronic Engineering, Higher Institute of Science and Technology, Al-Zahra, Libya
3
Department of Electrical Engineering, Onaizah Private Colleges, Al-Qassim, Saudi Arabia

Article Info ABSTRACT

Article history: The switching control circuit in a DC to AC inverter is the critical part that is
applied to control the power transistors insulated-gate bipolar transistor
Received Jun 14, 2022 (IGBTs) and metal-oxide semiconductor field-effect transistor (MOSFETs).
Revised Sep 15, 2023 This paper proposes a high-performance and low-cost pulse width
Accepted Jan 9, 2024 modulation (PWM) control signal with a 120º phase shift circuit for a two-
level three-phase inverter. Typically, a PWM signal with a 120º phase shift
for three-phase inverters is generated with the help of analogue components
Keywords: with more complicated designs and power losses or by using a
microcontroller with necessary programming or coding. The proposed
Dead time control solution is to design a 120° three-phase shift circuit based on D flip-flops
Gate driver circuit and the 555-timer to generate the clock signal for the flip-flop input in
Phase shift circuit addition to the dead-time control circuit. The proposed circuit is controlled
Pulse width modulation by one square wave signal as an input signal to generate six output PWM
Three-phase inverter control signals at 50 Hz to operate six MOSFETs in the three-phase inverter.
Simulation results in power simulation software PSIM and PROTEUS
simulation tools are used to verify the proposed circuit. Hardware
implementation of the proposed circuit and three-phase inverter is carried
out to validate the performance of the proposed design.
This is an open access article under the CC BY-SA license.

Corresponding Author:
Ezzidin Hassan Aboadla
Electrical Engineering Section, University Kuala Lumpur British Malaysian Institute
Batu 8, Jalan Sungai Pusu, Selangor-53100, Malaysia
Email: [email protected]

1. INTRODUCTION
Recently, with the continuous revolution of using solar photovoltaic (PV) energy, power-generating
techniques are becoming increasingly relevant with the push toward environmentally friendly and naturally
occurring energy sources benevolent methods. Because of the rapid development in the production of
electronic semiconductors, the high-performance design of power inverters has faced several challenges
[1]–[3]. The conventional two-level, three-phase voltage source inverter (VSI), used in numerous
applications including electrical motors, electric vehicles (EVs), and wind turbine systems, is thought to be
the most widely used converter architecture [4]. Inverter is an electronic device which contains various power
switches. By applying proper control pulses to these switches, AC power can be generated from DC input
[5]–[8].
One of the major problems that the designers must deal with is how to adjust the voltage of the gate
driver for the power switches while maintaining high safety isolation. These challenges are to design reliable
PWM gate drivers that are suitable and ensure quick ON/OFF transitions for operations. Several forms of
control driver circuits are employed to generate control signals for power converters [9]. A high switching

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Bulletin of Electr Eng & Inf ISSN: 2302-9285  801

frequency is presented in [10] to operate the power switches of the three-phase inverter, which is used to
improve the performance of the total harmonic distortion (THD) according to the alternative switching
approach. Pulse width modulation (PWM) signals are often produced by digital control circuits, although
they can also be produced by analog control circuits and programmable microcontrollers. However, digital
control techniques can provide excellent flexibility with low-tech hardware components and a higher
switching frequency. The analog PWM method necessitates many passive components, increasing power
consumption and decreasing stability [11]. Active driver circuits using analogue circuits such as diodes and
transistors have been proposed [12], [13]. However, it is not able to realize high-speed control signals due to
component delay time. A programmable gate control circuit utilizes full digital control to solve the active
gate driver circuit drawback [14]–[16]. To drive the power switches, a bootstrap driver circuit is commonly
used; however, it is unreliable, with any faults occurring when the controller part is not isolated [17], [18].
Selecting a suitable modulation technique for the inverter design is the most important step toward realizing a
low THD in the output voltage waveform. Several types of PWM generation schemes can be applied for gate
controller circuit of the inverters, such as the standard PWM, Sinusoidal pulse width modulation (SPWM),
space vector pulse width modulation (SVPWM), and the selective harmonic elimination pulse width
modulation (SHEPWM) method [19]–[21]. A pulse width modulation has been generated using the
multicarrier sinusoidal pulse width modulation method to operate a 15-level multilevel inverter presented in
[22]. The enhanced digital space vector pulse width modulation could create clocks by employing a digital
clock manager and phase-locked loop (PLL). The modified digital space vector modulation is produced on a
low-cost field programmable gate array (FPGA) for three-phase inverters [23]. A single-phase full-bridge
inverter is designed based on the selective harmonic elimination method. An Arduino Mega has been used to
determine the switching angles of the control signal and produce the PWM [24]. A three-phase full-bridge
inverter is the main device utilized to derive induction motor and AC supplies. The output phase shift of the
three-phase inverters is mutually phase-shifted by a 120-degree angle [25]. Three-phase shift signals with a
120-degree have been generated using a programmable microcontroller [26]. An analogue circuit based on
operational amplifiers has been proposed to produce a three-stage phase shift with a 120-degree [27].
To implement a higher performance, low-cost gate controller circuit, this paper proposes a new
50 Hz single-input multi-output PWM gate controller circuit for three-phase inverters based on D flip-flops
and the 555-timer. A 555 timer is applied to generate square wave PWM with a 50% duty cycle as an input to
the control gate circuit. Three-phase shift signals based on digital flip-flops with a dead-time control and gate
driver circuit have been proposed to operate the six power switches of the two-level three-phase inverter.
Simulation results and prototype circuits have been utilized to validate the performance of the proposed
design.

2. THREE-PHASE INVERTER
In industrial applications, three-phase inverters are more widely applied to drive induction motors
and other three-phase AC equipment. The two-level three-phase inverter circuit consists of six power
switches as insulated-gate bipolar transistor (IGBTs) or metal-oxide semiconductor field-effect transistor
(MOSFETs) as shown in Figure 1. Each phase has two switches controlled by a PWM signal. To prevent a
short circuit, the switches in the same phase are not turned on at the same time. Two methods are used to
control the inverter switches: 120° conduction mode and 180° conduction mode. In this paper, the 180°
conduction mode has been used to design the proposed control circuit. The switch timing occurs every 60° as
shown in Figure 2. Where Figure 2(a) shows the switches timing occurs every 60° and Figure 2(b) shows the
phase voltage of the three-phase inverter in 180° conduction mode.

Figure 1. Two-level three-phase inverter circuit diagram

Design and implementation of pulse width modulation gate control signals for … (Ezzidin Hassan Aboadla)
802  ISSN: 2302-9285

(a)

(b)

Figure 2. Control signals for switches; (a) the switches timing occurs every 60° and (b) the phase voltage of
the three-phase inverter in 180o conduction mode

3. PROPOSED PWM CONTROL CIRCUIT

A high-performance, low-cost PWM gate control circuit for three-phase inverters to control six
power switches with 120º phase-shift and dead-time generation circuit is proposed in this study. The block
diagram of the proposed design is shown in Figure 3. The circuit is divided into four stages: square wave
generator with 50% duty cycle, three-phase PWM control circuit with 120º phase shift, dead-time control
circuit, and the driver circuit.

3.1. Square wave generator module

In this section, 50% duty cycle square wave PWM signal is produced by a 555-timer IC. As the
clock signal to the next stage, a multi-PWM control circuit with a 120º phase shift oscillator. An astable
multivibrator circuit based on the 555-timer is low cost and simple to implement using a few capacitors and
resistors [28]. The values of the resistors and capacitors affect the frequency and duty cycle of the generated
signal. The period time (T), frequency (f), and duty cycle (D) are determined by (1) to (3):

𝑇 = 0.693(𝑅1 + 𝑅2 )𝐶 (1)
1 1.44
𝑓= = (2)
𝑇 (𝑅1 +2𝑅2 )𝐶

𝑅1 +𝑅2
𝐷=( ) × 100 (3)
𝑅1 +2𝑅2

Bulletin of Electr Eng & Inf, Vol. 13, No. 2, April 2024: 800-811
Bulletin of Electr Eng & Inf ISSN: 2302-9285  803

Figure 3. The block diagram of the proposed PWM module

3.2. A 120-degree three-phase shift circuit

A PWM control circuit based on a D flip-flop is proposed to provide switching control signals with
120º phase shift for three-phase inverter power transistors. The D flip-flop is the main part that is used to
generate 50 Hz PWM signals with a 120º phase shift. The number of D flip-flops required to design the
circuit is based on the number of high-side transistors of the inverter. Therefore, three D flip-flops are used in
this design. The switching diagram of the two-level three-phase inverter in Figure 4 is used to design the
control circuit. Because of the complementary status of the two switches in the same inverter leg, only the
signal of the upper switches (S1, S3, and S5) in each phase is used for designing the circuit. The state
diagram of the inverter switching operation is determined from the switching diagram as presented in
Figure 5. Each state in the diagram represents the status of the switching in all phases of the inverter. At the
switching period, the initial state (000) occurs when all switches are OFF. When S1 is ON, S2 is OFF, and S3
is ON, the state is changed to the following example (101). When S1 is ON while S2 and S3 are OFF, the
next state (100) is reached. When S1 is ON, S2 is ON, and S3 is OFF, the subsequent transfer (110) takes
place. When S1 is OFF, S2 is ON, and S3 is OFF, the state (010) is reached. The switches S1 is OFF, S2 and
S3 are ON, and the state (011) occurs. However, the last transfer (001) occurred when S1 was turned off, S2
was turned off, and S3 was turned on. In the next switching period, all states will repeat themselves.

100
S1 000

101 110

S3 111

001 010
S5

011
0 60 120 180 240 300 360

Figure 4. Three phase inverter switching Figure 5. The state diagram of the inverter switching
diagram status

The following step is to determine the state table of the present switching states and the following
switching states based on the state diagram as shown in Table 1. Each state of the switches (S1, S3, and S5)
has a separate Boolean function. Karnaugh map is used to determine the Boolean functions for each switch
depending on the D flip-flop state.
a. Karnaugh map and Boolean function of the first phase D flip-flop

Design and implementation of pulse width modulation gate control signals for … (Ezzidin Hassan Aboadla)
804  ISSN: 2302-9285

Q1.Q2
00 01 11 10
Q3
0 1 0 0 1
1 1 0 1 1

̅̅̅̅
𝐷𝑆1 = 𝑄1. 𝑄3 + 𝑄2 (4)

b. Karnaugh map and Boolean function of the second phase D flip-flop

Q1.Q2
00 01 11 10
Q3
0 0 1 1 1
1 0 0 0 0

̅̅̅̅ + 𝑄2. 𝑄3
𝐷𝑆2 = 𝑄1. 𝑄3 ̅̅̅̅ (5)

c. Karnaugh map and Boolean function of the third phase D flip-flop

Q1.Q2
00 01 11 10
Q3
0 1 1 0 0
1 1 1 1 0

𝐷𝑆3 = 𝑄2. 𝑄3 + ̅̅̅̅

𝑄1 (6)

Table 1. The state table of the PWM control circuit

Current switching states (Q) Next switching states (Q+1) Output states
Q1 Q2 Q3 Q1 Q2 Q3 D1 D2 D3
0 0 0 1 0 1 1 0 1
0 0 1 1 0 1 1 0 1
0 1 0 0 1 1 0 1 1
0 1 1 0 0 1 0 0 1
1 0 0 1 1 0 1 1 0
1 0 1 1 0 0 1 0 0
1 1 0 0 1 0 0 1 0
1 1 1 1 0 1 1 0 1

The circuit diagram of the proposed 120º phase shift circuit for a two-level three-phase inverter is
presented in Figure 6.

Q2*

Q1
Q3 Q1
1D 1Q
2D ~1Q Q1*
Q1 3D 2Q
4D ~2Q Q2
Q3* 3Q
~CLR ~3Q Q2*
Q2 CLK 4Q
~4Q Q3
Q3* Q3*

Q1*

Q2
Q3

Figure 6. The proposed PWM control circuit for two-level three-phase inverters

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Bulletin of Electr Eng & Inf ISSN: 2302-9285  805

3.3. Dead time control generation

To prevent a short circuit in the leg and the DC supply as well, the dead time must be included
between the gate drive pulses for two IGBTs in one leg of the inverters [29]. A dead time circuit is a small
interval ∆t between the upper and lower switches in the same inverter leg used to reduce the switch losses
and avoid the short circuit of the voltage source as shown in Figure 7. In addition, to avoid undesired
harmonic spikes can be generated during the dead time case, which could cause electromagnetic interface
issues [30], [31]. Figure 8 shows a dead-time control circuit for complementary power switches is used in
this paper to generate a small dead time interval that is used to prevent the issue of the short circuit in the
same phase leg.

S_Upper

S_Lower

∆t

Figure 7. The dead time interval between complementary switches in the inverter phase leg

PWM
To_S1_Driver

R3 R5
10kΩ
1kΩ
C2 R4
1nF 10kΩ

To_S2_Driver

R1 R6
10kΩ
1kΩ
C1 R2
1nF 10kΩ

Figure 8. Dead time control circuit for complementary power switches

3.4. Gate driver circuit

A gate driver circuit is a power amplifier utilized to produce a high current from a low input current
in order to operate the power transistors. Due to the low power output current of the proposed PWM control
circuit, which fails to operate the power transistors of the inverter, this work uses the IR2112 as a gate driver
circuit to amplify the current of the proposed control circuit to the needed voltage level to trigger the
MOSFET. The IC IR2112 from the international rectifier is a high-speed, high-voltage power switch driver
with independent high and low-side output channels [32], [33].
Figure 9 shows the final circuit diagram of the PWM control module for three-phase inverters
including four stages; a square wave generator using a 555-timer, three-phase PWM generator with 120º
phase shift, a dead-time control circuit which is used between two complementary switches in this paper, and
the gate driver stage which is used by IC-IR2112.

Design and implementation of pulse width modulation gate control signals for … (Ezzidin Hassan Aboadla)
806  ISSN: 2302-9285

Figure 9. The proposed PWM control for three-phase inverters with 120º phase shift

4. SIMULATION RESULTS
To verify the performance of the proposed PWM control circuit in Figure 3, the design was
simulated in PSIM and PROTEUS simulation tools. Three-phase inductive load in star connection load is
used in the simulation, R=15 Ω, and L=10 mH. Figure 10 shows the simulation result of the dead-time
control circuit. From Figure 10, the dead-time interval between both signals always remained. However, the
control gate signals of the upper switches are presented in Figure 11.

Figure 10. The simulation result of the dead-time for complementary switches

Figure 11. The output of the PWM control circuit signals for a three-phase inverter with 120º phase shift

As depicted in Figure 11, the output of the proposed PWM control circuit is 50 Hz with a 120º phase
shift for three upper power switches. Figure 12 shows the simulation of the six control PWM signals. As
indicated in Figure 12, the result of the proposed PWM module includes six PWM signals with a 120º for six
power switches MOSFETs or IGBTs. Figure 13 shows the simulation result of line-to-line voltage and the
fast fourier transform (FFT) analysis is presented in Figures 13(a) and (b) respectively. The total harmonic

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distortion (THD) of the three-phase inverter line voltage in the simulation results without using filter is 31%.
Figure 14 illustrates the phase current and its FFT spectrum analysis in Figures 14(a) and (b) respectively.
The THD of the phase current without using a low-pass filter is 17%.

Figure 12. The simulation result of the proposed PWM module with six output signals for six power switches

(a)

(b)

Figure 13. The simulation result of the three-phase inverter for; (a) line-to-line voltage and (b) FFT analysis

Design and implementation of pulse width modulation gate control signals for … (Ezzidin Hassan Aboadla)
808  ISSN: 2302-9285

(a)

THD-I = 17%

(b)

Figure 14. The simulation result of the three-phase inverter for; (a) phase current and (b) FFT spectrum
analysis

5. EXPERIMENTAL RESULTS
To prove the performance of the proposed module, the laboratory experimental prototype for the
PWM control board is implemented and tested with the two-level three-phase inverter as shown in Figure 15.
Figure 16 shows the output of the proposed PWM control circuit is 50 Hz with a 120º phase shift for three
upper power switches. In Figure 17, the output voltage waveform of the line-to-line voltage and the FFT
analysis are presented. It is clear that from Figure 17, the result of the prototype module with the inverter is in
close agreement with the simulation result compared with Figure 13.

Figure 15. PCB prototype board of the PWM control circuit

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Bulletin of Electr Eng & Inf ISSN: 2302-9285  809

Figure 16. Experimental result of the proposed control module for the upper switches of the inverter

Figure 17. Experimental result of line-to-line output voltage using the proposed PWM control module and the
FFT analysis

6. CONCLUSION
This paper proposed a single-input, multi-output 50 Hz PWM control circuit to control two-level,
three-phase inverters. The proposed technique is easy to implement, low cost, and high performance. A
555-timer is used to generate a square wave as a single input to the proposed module, while the output is six
PWM channels for the three-phase inverter to operate six power switches. D flip-flops and logic gates are the
core components in the proposed technique which are used to generate the PWM pulses and 120º phase shift.
A three-phase inverter has been used to evaluate the performance of the proposed control module in
simulation and experimentally, and both results are in close agreement with almost identical values.

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Bulletin of Electr Eng & Inf ISSN: 2302-9285  811

BIOGRAPHIES OF AUTHORS

Ezzidin Hassan Aboadla received the B.Eng. degree in Electronic Engineering

from Collage of Electronics Technology, Beni Walid, Libya, in 1988. He received the master’s
degree in Electrical and Electronics Engineering from University of Tripoli, Libya, in 2007,
and Ph.D. degree in Electrical and Computer Engineering from International Islamic
University Malaysia (IIUM), in 2019. His research interests include power converters, control
of power converters, multilevel inverters, renewable energy, and internet of things (IoT)
battery management system (BMS). He can be contacted at email: [email protected],
[email protected].

Kushsairy Kadir is an Assoc. Prof. at the Electrical Technology Section,

Universiti Kuala Lumpur, British Malaysian Institute. He graduated with Bachelor of Science
in Engineering from University of the West of England, Bristol (1998) and completed a
Master of Science degree in Mechatronic at the International Islamic University (2007). He
was awarded a Ph.D. from Strathclyde University in 2012 in Electronic and Electrical
Engineering. He is an active member of IEEE Society and has been a Senior Member since
2015. Currently he is a Vice Chair of IEEE IMS Malaysia Chapter. His recent research
interests include signal and image processing, robotics for rehabilitation and energy efficient
technology. He has published 120 peer-reviewed articles. Kushsairy Abdul Kadir received 430
citations in Scopus with a H-index of 11. He can be contacted at email:
[email protected].

Sheroz Khan SMIEE 01549179, MIET, C.Eng. has received his B.Sc. in
Electrical Engineering from the N-W.F.P University of Engineering and Technology (UET)
Peshawar, Pakistan. Being the best graduate of the Department of Electrical Engineering in
1982, he was awarded the university scholarship for doing M.Sc. in Microelectronic and
Computer Engineering at Surrey (1988), University, UK. He completed his Ph.D. at
Strathclyde University (UK), and rejoined his parent university in August 1994. After serving
the NWFP UET for five years, he was selected by a Malaysian delegation for work as a
Principal Lecturer at UNITEN from Jan 2000. Upon completing his two-year contract at
UNITEN he started as an associate professor at the International Islamic University Malaysia
from January 2002. He has so far produced twenty two (22) M.Sc. under his direct supervision
and 15 M.Sc. under co-supervision. He has produced ten (10) Ph.D., two (2) Post-Doctorate
under his direct supervision while producing eight (8) Ph.D. under co-supervision. He has
been the Post-graduate Coordinator of ECE Dept. at IIUM, and founding coordinator of the
wireless communication and signal processing research group since 2006. He has been the
research methodology and PG seminar coordinator for the PG programs of the whole faculty
of engineering since 2009 for which he has completed producing Guidelines Booklet. He has
remained Chair of the IEEE Malaysia Chapter for 2012 while working as a secretary of the
IEEE IMS Malaysia Chapter for 2013-2019. He is the co-founder of the International
Conference on Smart Instrumentation, Measurement and Application (ICSIMA 2013) and has
been the Technical Committee of the bi-annual conference IEEE ICCCE. Currently he is
working as full professor within the Department of Electrical Engineering, Onaizah College of
Engineering and Information Technology, Al-Qassimg (Saudi Arabia). He is working to
establish the IEEE Society and IEEE Student Chapters at Onaizah College and is charged with
the task of organizing an international conference. He comes from a humble family origin
from the village of Nawai Wadana. He can be contacted at email: [email protected].

Design and implementation of pulse width modulation gate control signals for … (Ezzidin Hassan Aboadla)