Unit-2 Lecture-1

Today’s Target
✓ Main features of 8085 microprocessor.
✓ Internal architecture: ALU, Registers, Timing and control unit,
interrupt
✓ AKTU PYQs
 AKTU Syllabus : Unit-II
Intel 8085 microprocessor:
Pin Diagram, Internal architecture: ALU, Registers, Timing and control unit, interrupt
Instruction Set of 8085:
Instruction format, op-codes, mnemonics, no. of bytes computation of the instruction, Machine
cycles and T- states and Execution time computation of an instruction. Classification of
instruction with their examples. Writing of assembly Language programs.
 Introduction to 8085 Microprocessor

MAIN FEATURES OF 8085 MICROPROCESSOR

1. It is an 8 bit microprocessor.
2. It is manufactured with N-MOS technology.
3. It has 16-bit address bus and hence can address up to 216 = 65536 bytes (64KB) memory
locations through A0-A15
4. The first 8 lines of address bus and 8 lines of data bus are multiplexed AD0 – AD7
5. Data bus is a group of 8 lines D0 – D7
6. It supports external interrupt request.
7. A 16 bit program counters (PC)
8. A 16 bit stack pointer (SP)
9. Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
10. It requires a signal +5V power supply and operates at 3.2 MHZ single phase clock.
It is enclosed with 40 pins DIP (Dual in line package).
ARCHITECTURE OF 8085 MICROPROCESSOR
 ARITHMETIC & LOGIC UNIT(ALU)

The ALU performs the following arithmetic and logical operations.

Addition
Subtraction
Logical AND
Logical OR
Logical EXCLUSIVE OR
Complement (logical NOT)
Increment (add 1)
Decrement (subtract 1)
Left shift
Clear
REGISTER SET
 GENERAL PURPOSE REGISTERS
The 8085 has six general-purpose registers to store 8-bit data; these are identified as
B, C, D, E, H, and L
They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit
operations
The programmer can use these registers to store or copy data into the registers by
using data copy instructions
The HL register pair is also used to address memory locations
In other words, HL register pair plays the role of memory address register
 SPECIAL PURPOSE REGISTERS

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU).

Program Counter – store address of next instruction to be executed.

Stack Pointer – store the address of stack top, the last filled location of a Stack.
 INSTRUCTION REGISTER/DECODER

The instruction register and the decoder are considered as a part of the ALU
The instruction register is a temporary storage for the current instruction of a
program
The decoder decodes the instruction and establishes the sequence of events to
follow
 FLAGS

The ALU includes five flip-flops, which are set or reset after an operation according
to data conditions of the result in the accumulator and other registers
They are called Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY)
flags
Flags

If the sum in the accumulator id larger than eight bits, the flip-flop uses to indicate a
carry -- called the Carry flag (CY) – is set to one
When an arithmetic operation results in zero, the flip-flop called the Zero (Z) flag is
set to one
In the addition of any two 8-bit numbers, a carry may be generated when we add the
LS hex digits of the two numbers. Such a carry is called intermediate carry also
known as half carry, or auxiliary carry (AC)
Flags

• Parity flag (P): It is set to 1, if the 8-bit result thus produced against any logical and
arithmetic operation has an even number of 1's in it. If there are odd number of 1's
in the 8-bit result, the P flag is reset to 0.
• After any operation if the MSB (B(7)) of the result is 1, it indicates the number is
negative and the sign flag becomes set, i.e. 1.
• The combination of the flag register and the accumulator is called Program Status
Word (PSW) and PSW is the 16-bit unit for stack operation
 INTERRUPTS IN 8085

Interrupt are classi ied into following groups based on their parameter −
Maskable interrupt − In this type of interrupt, we can disable the interrupt by writing some
instructions into the program. For example: RST7.5, RST6.5, RST5.5.
Non-Maskable interrupt − In this type of interrupt, we cannot disable the interrupt by
writing some instructions into the program. For example: TRAP.
Software interrupt − In this type of interrupt, the programmer has to add the instructions
into the program to execute the interrupt. There are 8 software interrupts in 8085, i.e. RST0,
RST1, RST2, RST3, RST4, RST5, RST6, and RST7.
Hardware interrupt − There are 5 interrupt pins in 8085 used as hardware interrupts, i.e.
TRAP, RST7.5, RST6.5, RST5.5, INTA.
Vector interrupt − In this type of interrupt, the interrupt address is known to the
processor. For example: RST7.5, RST6.5, RST5.5, TRAP.
Non-Vector interrupt − In this type of interrupt, the interrupt address is not known to the
processor so, the interrupt address needs to be sent externally by the device to perform
interrupts. For example: INTR.
 Vectored and Non-Vectored Interrupts

Hardware Interrupts Software Interrupts

INTERRUPT VECTOR ADDRESS
INTERRUPT VECTOR ADDRESS
RST 0 00 H
TRAP (RST 4.5) 24 H RST 1 08 H

RST 2 10 H
RST 5.5 2C H
RST 3 18 H

RST 6.5 34 H RST 4 20 H

RST 5 28 H
RST 7.5 3C H
RST 6 30 H

RST 7 38 H
ARCHITECTURE OF 8085 MICROPROCESSOR
University Questions

1. What is stack memory? (2016-17)

2. What is flag? Draw flag register of 8085?(2016-17, 2017-18, 2022-
23)
3. Give the flag status of 8085 when following additions are performed
a)51H+A9H b)2EH+5AH c)76H+A4H. (2016-17)
4. Explain the architecture of 8085 with neat diagram? (2016-17, 2022-
23)
 Unit-2 Lecture-2

Today’s Target
✓ Pin Diagram of the 8085 Microprocessor.
✓ AKTU PYQs
 PIN DIAGRAM OF 8085 MICROPROCESSOR

1. Power Supply and Clock Frequency

2. Address & Data Bus

3. Control and Status Signals

4. Interrupts

5. Externally Initiated Signals

6. Serial I/O Ports

 Power Supply and Clock Frequency
Vcc – +5v power supply
Vss – Ground Reference
XI, X2 – A crystal is connected at these two pins. The
frequency is internally divided by two, therefore, to
operate a system at 3MHZ the crystal should have
frequency of 6MHZ.
CLK (OUT) – This signal can be used as the system
clock for other devices.
 Address & Data Bus
Address Bus
The 8085 has eight signal lines, A15-A8, which are
unidirectional and used as the high order address bus

Multiplexed Address/Data Bus

The signal lines AD7-AD0 are bidirectional. They
serve a dual purpose
 Control and Status Signals
ALE
IO/M’
RD’
WR’
SO, S1
 Interrupts
 INTR
 RST 7.5
 RST 6.5
 RST 5.5
 TRAP
INTA’
Externally Initiated Signals
1. Reset Signals:
RESET IN’
RESET OUT
When the signal on this pin is low for at least 3
clocking cycles, it forces the microprocessor to reset
itself. Resetting means
◦ Clearing the PC and IR.
◦ Disabling all interrupts (except TRAP).
◦ Disabling the SOD pin.
◦ All the buses (data, address, control) are tri-
stated.
◦ Gives HIGH output to RESET OUT pin.

2. DMA Signals:

HOLD
HLDA
Serial I/O Ports:

SID
o It takes 1 bit input from serial port of 8085.
o Stores the bit at the 8th position (MSB) of
the Accumulator.
o RIM (Read Interrupt Mask) instruction is
used to transfer the bit.
SOD
o It takes 1 bit from Accumulator to serial
port of 8085.
o Takes the bit from the 8th position (MSB) of
the Accumulator.
o SIM (Set Interrupt Mask) instruction is used
to transfer the bit.
University Questions

1. Explain the function of externally initiated signal of 8085?

(2016-17)
2. Explain all the interrupts of 8085? List all the vectored
interrupts of 8085 and their vector address? (2015-16, 2016-17,
2023-24)
3. What is the meaning of ALE signal? (2017-18)
4. Explain the pin diagram of 8085 microprocessor? (2015-16)
 Unit-2 Lecture-3

Today’s Target
✓ Instruction format, op-codes, mnemonics, no. of bytes computation
of the instruction
✓ Classification of instruction with their examples.
✓ AKTU PYQs
One Byte Instructions
Two Byte Instructions
THREE Byte Instruction
 INSTRUCTION SET OF 8085

1. Data Transfer Instructions

2. Arithmetic Instructions
3. Logical Instructions
4. Control Instructions
5. Branching Instructions
 Data Transfer Instructions

Opcode Operand Explanation of Instruction Description

MOV Rd, Rs Copy from source(Rs) to This instruction copies the contents of the
M, Rs destination(Rd) source register into the destination register;
Rd, M the contents of the source register are not
altered. If one of the operands is a memory
location, its location is specified by the
contents of the HL registers.
Example: MOV B, C or MOV B, M
MVI Rd, data Move immediate 8-bit The 8-bit data is stored in the destination
M, data register or memory. If the operand is a
memory location, its location is specified by
the contents of the HL registers.
Example: MVI B, 57H or MVI M, 57H
LDA 16-bit address Load accumulator The contents of a memory location, specified
by a 16-bit address in the operand, are
copied to the accumulator. The contents of
the source are not altered.
Example: LDA 2034H
STA 16-bit Store accumulator The contents of the accumulator are copied into
address the memory location specified by the operand.
This is a 3-byte instruction, the second byte
specifies the low-order address and the third byte
specifies the high-order address.
Example: STA 4350H
SHLD 16-bit Store H and L The contents of register L are stored into the
address registers direct memory location specified by the 16-bit address in
the operand and the contents of H register are
stored into the next memory location by
incrementing the operand. The contents of
registers HL are not altered. This is a 3-byte
instruction, the second byte specifies the low-
order address and the third byte specifies the
high-order address.
Example: SHLD 2470H
XCHG none Exchange H and L The contents of register H are exchanged with the
with D and E contents of register D, and the contents of register
L are exchanged with the contents of register E.
Example: XCHG
PUSH Reg. pair Push register pair onto stack The contents of the register pair designated in the
operand are copied onto the stack in the following
sequence. The stack pointer register is
decremented and the contents of the high order
register (B, D, H, A) are copied into that location.
The stack pointer register is decremented again
and the contents of the low-order register (C, E, L,
flags) are copied to that location.
Example: PUSH B or PUSH A
POP Reg. pair Pop off stack to register pair The contents of the memory location pointed out
by the stack pointer register are copied to the low-
order register (C, E, L, status flags) of the operand.
The stack pointer is incremented by 1 and the
contents of that memory location are copied to the
high-order register (B, D, H, A) of the operand. The
stack pointer register is again incremented by 1.
Example: POP H or POP A
OUT 8-bit port Output data from accumulator The contents of the accumulator are copied into
address to a port with 8-bit address the I/O port specified by the operand.
Example: OUT F8H
IN 8-bit port Input data to accumulator The contents of the input port designated in the
address from a port with 8-bit address operand are read and loaded into the accumulator.
Example: IN 8CH
 Arithmetic Instructions
Opcode Operand Explanation of Instruction Description

ADD R Add register or memory, to

The contents of the operand (register or memory)
M accumulator are added to the contents of the accumulator and the
result is stored in the accumulator. If the operand is
a memory location, its location is specified by the
contents of the HL registers. All flags are modified to
reflect the result of the addition.
Example: ADD B or ADD M
ADC R Add register to accumulator The contents of the operand (register or memory)
M with carry and M the Carry flag are added to the contents of the
accumulator and the result is stored in the
accumulator. If the operand is a memory location, its
location is specified by the contents of the HL
registers. All flags are modified to reflect the result
of the addition.
Example: ADC B or ADC M
ADI 8-bit data Add immediate to accumulator The 8-bit data (operand) is added to the contents of
the accumulator and the result is stored in the
accumulator. All flags are modified to reflect the
result of the addition.
Example: ADI 45H
SUB R Subtract register or memory The contents of the operand (register or
M from accumulator memory ) are subtracted from the contents of
the accumulator, and the result is stored in the
accumulator. If the operand is a memory
location, its location is specified by the contents
of the HL registers. All flags are modified to
reflect the result of the subtraction.
Example: SUB B or SUB M
SBB Subtract source and borrow The contents of the operand (register or
R from accumulator memory ) and M the Borrow flag are subtracted
M from the contents of the accumulator and the
result is placed in the accumulator. If the
operand is a memory location, its location is
specified by the contents of the HL registers. All
flags are modified to reflect the result of the
subtraction.
Example: SBB B or SBB M
SBI 8-bit data Subtract immediate from The contents of register H are exchanged with
accumulator with borrow the contents of register D, and the contents of
register L are exchanged with the contents of
register E.
Example: SBI 05H
INR R Increment register or memory The contents of the designated register or memory) are
M by 1 incremented by 1 and the result is stored in the same
place. If the operand is a memory location, its location
is specified by the contents of the HL registers.
Example: INR B or INR M
INX R Increment register pair by 1 The contents of the designated register pair are
incremented by 1 and the result is stored in the same
place.
Example: INX H
DCR R Decrement register or memory The contents of the designated register or memory are
M by 1 M decremented by 1 and the result is stored in the
same place. If the operand is a memory location, its
location is specified by the contents of the HL registers.
Example: DCR B or DCR M
DCX R Decrement register pair by 1 The contents of the designated register pair are
decremented by 1 and the result is stored in the same
place.
Example: DCX H
University Questions

1. Explain the classification of the instruction set of 8085

microprocessor with suitable examples. (2022-23)
2. Identify the addressing modes of 8085 microprocessor and
explain them
• MVI B,45H
• ADD B
• LDA 2050H? (2023-24)
 Unit-2 Lecture-4

Today’s Target
✓ Classification of instruction with their examples.
✓ AKTU PYQs
✓ Practice Question
 Logical Instructions
Opcode Operand Explanation of Description
Instruction

CMP R Compare register or The contents of the operand (register or memory) are M compared with
M memory with the contents of the accumulator. Both contents are preserved . The result
accumulator of the comparison is shown by setting the flags of the PSW as follows:
if (A) < (reg/mem): carry flag is set
if (A) = (reg/mem): zero flag is set
if (A) > (reg/mem): carry and zero flags are reset
Example: CMP B or CMP M
ANA R Logical AND register or The contents of the accumulator are logically ANDed with M the contents
M memory with of the operand (register or memory), and the result is placed in the
accumulator accumulator. If the operand is a memory location, its address is specified
by the contents of HL registers. S, Z, P are modified to reflect the result of
the operation. CY is reset. AC is set.
Example: ANA B or ANA M
ANI 8-bit Logical AND immediate The contents of the accumulator are logically ANDed with the 8-bit data
data with accumulator (operand) and the result is placed in the accumulator. S, Z, P are modified
to reflect the result of the operation. CY is reset. AC is set.
Example: ANI 86H
XRA R Exclusive OR register or The contents of the accumulator are Exclusive ORed with
M memory with accumulator M the contents of the operand (register or memory), and
the result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents
of HL registers. S, Z, P are modified to reflect the result of
the operation. CY and AC are reset.
Example: XRA B or XRA M
XRI 8-bit dataExclusive OR immediate The contents of the accumulator are Exclusive ORed with
with accumulator the 8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of
the operation. CY and AC are reset.
Example: XRI 86H
ORA R Logical OR register or The contents of the accumulator are logically ORed with
M memory with accumulator M the contents of the operand (register or memory), and
the result is placed in the accumulator. If the operand is a
memory location, its address is specified by the contents
of HL registers. S, Z, P are modified to reflect the result of
the operation. CY and AC are reset.
Example: ORA B or ORA M
ORI 8-bit dataLogical OR immediate The contents of the accumulator are logically ORed with
with accumulator the 8-bit data (operand) and the result is placed in the
accumulator. S, Z, P are modified to reflect the result of
the operation. CY and AC are reset.
Example: ORI 86H
RLC none Rotate accumulator left
Each binary bit of the accumulator is rotated left by one
position. Bit D7 is placed in the position of D0 as well as in the
Carry flag. CY is modified according to bit D7. S, Z, P, AC are not
affected.
Example: RLC
RRC none Rotate accumulator right Each binary bit of the accumulator is rotated right by one
position. Bit D0 is placed in the position of D7 as well as in the
Carry flag. CY is modified according to bit D0. S, Z, P, AC are not
affected.
Example: RRC
RAL none Rotate accumulator left Each binary bit of the accumulator is rotated left by one
through carry position through the Carry flag. Bit D7 is placed in the Carry
flag, and the Carry flag is placed in the least significant position
D0. CY is modified according to bit D7. S, Z, P, AC are not
affected.
Example: RAL
RAR none Rotate accumulator right Each binary bit of the accumulator is rotated right by one
through carry position through the Carry flag. Bit D0 is placed in the Carry
flag, and the Carry flag is placed in the most significant
position D7. CY is modified according to bit D0. S, Z, P, AC are
not affected.
Example: RAR
CMA none Complement accumulator The contents of the accumulator are
complemented. No flags are affected.
Example: CMA

CMC none Complement carry The Carry flag is complemented. No other flags
are affected.
Example: CMC

STC none Set Carry Set Carry

Example: STC
Control Instructions
Opcode Operand Explanation of Description
Instruction

NOP none No operation No operation is performed. The instruction is fetched and

decoded. However no operation is executed.
Example: NOP
HLT none Halt and enter The CPU finishes executing the current instruction and halts any
wait state further execution. An interrupt or reset is necessary to exit from
the halt state.
Example: HLT
DI none Disable The interrupt enable flip-flop is reset and all the interrupts except
interrupts the TRAP are disabled. No flags are affected.
Example: DI
EI none Enable The interrupt enable flip-flop is set and all interrupts are enabled.
interrupts No flags are affected. After a system reset or the
acknowledgement of an interrupt, the interrupt enable flip-flop is
reset, thus disabling the interrupts. This instruction is necessary
to re-enable the interrupts (except TRAP).
Example: EI
Opcode Operand Explanation of Description
Instruction

RIM none Read interrupt mask This is a multipurpose instruction used to read the status of
interrupts 7.5, 6.5, 5.5 and read serial data input bit. The
instruction loads eight bits in the accumulator with the
following interpretations.
Example: RIM

SIM none Set interrupt mask This is a multipurpose instruction and used to implement the
8085 interrupts 7.5, 6.5, 5.5, and serial data output. The
instruction interprets the accumulator contents as follows.
Example: SIM
 Branching Instructions
Opcode Operand Explanation of Description
Instruction

JMP 16-bit address Jump The program sequence is

unconditionally transferred to the memory
location specified by the 16-bit
address given in the operand.

Example: JMP 2034H or JMP XYZ

Opcode Description Flag Status
16-bit address Jump The program sequence is
JC Jump on Carry CY = 1
conditionally transferred to the memory
JNC Jump on no Carry CY = 0 location specified by the 16-bit
address given in the operand
JP Jump on positive S=0
based on the specified flag of the
JM Jump on minus S=1 PSW as described below.
JZ Jump on zero Z=1
JNZ Jump on no zero Z=0
Example: JZ 2034H or JZ XYZ
JPE Jump on parity even P=1

JPO Jump on parity odd P=0

Opcode Description Flag Status

CC Call on Carry CY = 1

CNC Call on no Carry CY = 0 The program sequence is

transferred to the memory location
CP Call on positive S=0 specified by the 16-bit address given
16-bit address conditional in the operand. Before the transfer,
subroutine call the address of the next instruction
CM Call on minus S=1
after CALL (the contents of the
program counter) is pushed onto
CZ Call on zero Z=1 the stack.

Example: CALL 2034H or CALL XYZ

CNZ Call on no zero Z=0

CPE Call on parity even P=1

CPO Call on parity odd P=0

University Questions

1. What is the function of JUMP and CALL instruction? (2022-23)

2. Explain the following instructions
a) RRC
b) RAL
c) CMA
 Unit-2 Lecture-5
Today’s Target
✓ Machine cycles and T- states and Execution time computation of an
instruction.
✓ AKTU PYQs
✓ Practice Question
 Timing Diagram

Timing Diagram is a graphical representation. It represents the

execution time taken by each instruction in a graphical format. The
execution time is represented in T-states.

• Instruction Cycle: The time required to execute an instruction is called

instruction cycle.

• Machine Cycle: The time required to access the memory or

input/output devices is called machine cycle.

• T-State:
1. The machine cycle and instruction cycle takes multiple clock periods.
2. A portion of an operation carried out in one system clock period is
called as T-state.
Instruction Cycle
Timing Diagram of Opcode Fetch
Timing Diagram of Read Cycle
Timing Diagram of Write Cycle
University Questions

1. Draw & explain the memory and I/O read cycle of 8085? (2016-17)
2. Define instruction cycle, machine cycle & T-state in microprocessor
operation? (2016-17)
3. How does microprocessor differentiate between data & instruction.
(2015-16)
4. Discuss with the help of timing diagram that how microprocessor can
fetch the opcode and how many T - states are required to complete
this cycle? (2023-24)
 Unit-2 Lecture-6

Today’s Target
✓ Writing of assembly Language programs.
✓ AKTU PYQs
 Writing of assembly Language programs

Assembly language operation codes (op-codes) are easily remembered (MOV

for move instructions, JMP for jump). You can also symbolically express
addresses and values referenced in the operand field of instructions. Since
you assign these names, you can make them as meaningful as the mnemonics
for the instructions.
 Example Programs

1. Statement: Store the data byte 32H into memory location 4000H.
Program 1
MVI A, 32H : Store 32H in the accumulator
STA 4000H : Copy accumulator contents at address 4000H
HLT : Terminate program execution

Program 2
LXI H 4000H: Load HL with 4000H
MVI M, 32H : Store 32H in memory location pointed by HL register pair
(4000H)
HLT : Terminate program execution
2. Statement: Exchange the contents of memory locations 2000H and 4000H
Program 1
LDA 2000H : Get the contents of memory location 2000H into accumulator
MOV B, A : Save the contents into B register
LDA 4000H : Get the contents of memory location 4000H into accumulator
STA 2000H : Store the contents of accumulator at address 2000H
MOV A, B : Get the saved contents back into A register
STA 4000H : Store the contents of accumulator at address 4000H

Program 2
LXI H 2000H : Initialize HL register pair as a pointer to memory location 2000H.
LXI D 4000H : Initialize DE register pair as a pointer to memory location 4000H.
MOV B, M : Get the contents of memory location 2000H into B register.
LDAX D : Get the contents of memory location 4000H into A register.
MOV M, A : Store the contents of A register into memory location 2000H.
MOV A, B : Copy the contents of B register into accumulator.
STAX D : Store the contents of A register into memory location 4000H.
HLT : Terminate program execution.
3. Statement: Add the contents of memory location 4001H from the memory location
4000H and place the result in memory location 4002H.
Sample problem
(4000H) = 14H
(4001H) = 89H
Result = 14H + 89H = 9DH

Source program
LXI H 4000H : HL points 4000H
MOV A, M : Get first operand
INX H : HL points 4001H
ADD M : Add second operand
INX H : HL points 4002H
MOV M, A : Store result at 4002H
HLT : Terminate program execution
4. Statement: Subtract the contents of memory location 4001H from the memory
location 4000H and place the result in memory location 4002H.

Sample problem
(4000H) = 51H
(4001H) = 19H
Result = 51H - 19H = 38H

Source program
LXI H 4000H : HL points 4000H
MOV A, M : Get first operand
INX H : HL points 4001H
SUB M : Subtract second operand
INX H : HL points 4002H
MOV M, A : Store result at 4002H.
HLT : Terminate program execution
University Questions

1. What do you mean by assembly language programming? (2023-

24)
2. Write an assembly level program to find the highest number
from a given number? (2023-24)
3. Write an assembly level program to exchange the data of
memory locations 8501H and 8502H. (2016-17)
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