Acharya Institute of Technology

Bengaluru–560107

Department of
Electronics and Communication E ngineering

LAB MANUAL

Academic Year : 2024–25 (EVEN SEMESTER)

Programme (UG/PG) : UG
Year/Semester : VI
Course Code : BECL606
Course Title : VLSI Design and Testing Lab

Prepared By
Mrs.Veena Sanath Kumar

Reviewed By
Dr. Jayalaxmi H
Asso. Prof., Department of ECE, AIT

Approved By:
Dr.Rajeswari
Prof. & Head, Department of ECE, AIT
 Course Details

Course Name : VLSI Design and Testing Lab

Course Code : BECL606
Course prerequisite : Basic knowledge of Digital circuits , CMOS
circuit design and Programming concepts of
Verilog HDL

Course Objectives
1. Understand the flow of the Full Custom IC design cycle.
2. Simulate the various CMOS digital circuits.
3. Learn DRC, LVS and Parasitic Extraction of the various designs.

Course Outcomes
Upon successful completion of this course, students should be able to:

CO1 : Write a Verilog code / draw schematic of Analog circuits / Digital circuits. L3

CO2 : Simulate Analog circuits / Digital circuits for given specifications. L3

CO3 : Generate Layout /Gate level netlist and verify results. L3
CO4 : Interpret the concepts and results both orally and written. L3

COs, POs, and PSOs mapping

CO-PO-PSO Mapping Table PSOs

PO 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3
CO1 3 3 3 3 3 3 1 1 3

CO2 3 3 3 3 3 3 1 3

CO3 3 3 3 3 3 3 1 3

CO4 3 3 3 3 3 3 1 1 3
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

VISION STATEMENT
“To be a premier engineering department with excellence in teaching, research and innovation, to
meet the global industrial standards and to have significant impact on the wellbeing of the society”.

MISSION STATEMENT
1. To provide student centric learning environment, inculcate profound knowledge in both
fundamental and applied areas of science and technology.
2. To train and mentor the students in developing leadership qualities and team building
skills.

Program Outcomes (POs)

Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.

2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.

3. Design/development of solutions: Design solutions for complex engineering problems and

design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.

4. Conduct investigations of complex problems: Use research-based knowledge and research

methods including design of experiments, analysis and interpretation of data, and synthesis of
the information to provide valid conclusions.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.

9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.

12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
 Program Specific Outcomes (PSOs)

PSO1: Analog / Digital Circuit Design: Apply the conceptual knowledge in the analysis and/or
design, evaluate analog/digital circuits and systems.
PSO2: VLSI, Signal Processing and Embedded Systems: Demonstrate technical competency
in the analysis, design, and validation of components in VLSI, Signal Processing, and Embedded
Systems.
PSO3: Communication and Networking: Apply the domain knowledge in the implementation
and performance analysis of Communication Systems and Computer Networks.

Program Educational Objectives (PEOs)

Upon successful completion of the program, the student will be able to

PEO1: Students shall have a successful professional career in industry, academia, R & D
organization or entrepreneur in specialized field of Electronics & Communication engineering
and allied disciplines.
PEO2: Students shall be competent, creative and valued professional in the chosen field.
PEO3: Engage in life-long learning and professional development.
PEO4: Become effective global collaborators, leading or participating to address technical,
business, environmental and societal challenges.
VLSI Design and Testing Lab BECL606

VTU Syllabus

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List of experiments for VLSI Lab

SL.No Experiments Page No.

Digital Design
1. 4-bit adder

2. 4-Bit Shift and Add Multiplier

3. 32-bit ALU

4. Latch and Flip-Flop ((D, SR, JK)

5. Four-bit / MOD-N counter

Analog Design
5. Schematic and Layout of Inverter

6. Schematic of 2-input CMOS NOR Gate

7. Schematic and Layout of Common Source Amplifier

8. Schematic and Layout of two-stage Op-amp

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Introduction
VLSI is the current trend of manufacturing electronic integrated circuits. As we know that there
are two divisions of electronic circuits (analog and digital) VLSI also have this division. An IC
(Integrated Circuit) consisting of a large number of transistors, usually in the range of around 10
K to 1 Billion is called a VLSI circuit. The invention of Planar Technology for fabrication of
transistors on a silicon wafer made VLSI circuits possible today. The fabrication techniques are
improving every year minimizing process steps, leakage and shrinking transistor size even further.
All these help in building power efficient, fast and reliable electronic circuits

Digital VLSI

Design aspects:
 Mostly the design is automated and HDLs are used to describe the design.

 Transistors are much smaller and operate at lower supply levels than analog circuits.

 Transistors are operated in saturation (ON) and cutoff (OFF) regions.

 Regeneration of signal is easy so long wires is not a big problem for digital circuits.

 Design is mostly CMOS which have less power dissipation, high density, low
cost and easily fabricated.

Testing aspects:
 Circuit can be tested exhaustively giving all possible inputs increasing reliability.

 Testing is easy and automated.

 Phase delays and noise do not affect the system operation.

 Failure conditions can be determined easily.

 The delays have to be analyzed correctly so that the setup and hold time violations do not
happen.

Application aspects:
 Majority of the system is digital.

 Processors and microcontrollers are digital circuits.

 Used almost in all areas of application.

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Analog VLSI

Design aspects:
 It is comparatively difficult to design an analog VLSI circuit than a Digital VLSI circuit.

 Design of circuit is mostly manual.

 It cannot be described using a HDL (Hardware Descriptive Language).

 Analog modules are separated from the entire design because they need separate ground.

 Transistors are operated in linear and conduction regions.

 Transistors used are a bit larger than that used for digital circuits and run at a higher supply
voltage.

 Design is not necessarily a CMOS design.

Testing aspects:
 It is difficult to test the circuit because in real system noise affects more and you cannot inject
noise directly while testing the circuit.

 Phase delays also effect the circuit operation.

Application aspects:
 Only a small portion of an electronic circuit will be analog as their operation is highly affected
by noise.

 These are mostly used for highspeed amplifiers in communication.

 Used in ADCs (Analog to Digital Converters).

 Used at the modems, RF-receiver of mobile phones.

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Part A : ASIC Digital Design

Digital Design Procedure
Step-1 : Creating a Work space

• In Desktop Create a folder to do the digital design flow. Right click in the Desktop and select
New Folder as shown in Figure1.2
• It will create a folder like below and name it as Cadence_Digital_Labs

Note: Give folder name without any space

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• Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.

Figure no. 1.4: Creating and Naming the Sub-Directory

Step-2: Creating Source Codes

Creating Verilog code :

In the Terminal, type gedit <filename>.v or <filename>.vhdl depending on the HDL Language
you are to use (ex: 4b_up_downCount.v).

A Blank Document opens up into which the following source code can be typed down.

Note : File name should be with HDL Extension

Use Save option or Ctrl+S to save the code or click on the save option from the top most right
corner and close the text file.

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Creating Test bench: Similarly, create your test bench using gedit <filename_tb>.v or
<filename_tb>.vhdl to open a new blank document (4bup_down_count_tb.v).

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Click on the Save option and it will look like the below window and then close the file

Figure No.1.5: Verilog and Test bench file for 4bit updown counter

Step-3:Functional Simulation

Invoke the cadence environment by type the below commands

◦ csh (Invokes C-Shell)

◦ source /home/install/cshrc (mention the path of the tools)

◦ (The path of cshrc could vary depending on the installation destination as /home/install/

or /home etc.)

• After this you can see the window like below

 To Launch Simulation tool

◦ linux:/> nclaunch -new& // ―-new‖ option is used for invoking NCVERILOG for the first time
for any design

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◦ linux:/> nclaunch& // On subsequent calls to NCVERILOG

 It will invoke the nclaunch window for functional simulation we can compile, elaborate
and simulate it using Multistep

 Select Multiple Step and then select ―Create cds.lib File‖ as shown in below figure
 Click the cds.lib file and save the file by clicking on Save option

 Save cds.lib file and select the correct option for cds.lib file format based on the HDL
Language and Libraries used.
 Select ―Don‘t include any libraries (verilog design)‖ from ―New cds.lib file‖ and click
on―OK‖ as in below figure
◦ We are simulating verilog design without using any libraries

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 A Click ―OK‖ in the ―nclaunch: Open Design Directory window as shown in below
figure

A ‗NCLaunch window‘ appears as in Figure

• Left side you can see the HDL files. Right side of the window has worklib and
snapshots directories listed.
• Worklib is the directory where all the compiled codes are stored while Snapshot will
have output of elaboration which in turn goes for simulation

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To perform the function simulation, the following three steps are involved Compilation,
Elaboration and Simulation.

Step 1: Compilation:– Process to check the correct Verilog language syntax and usage

Inputs: Supplied are Verilog design and test bench codes

Outputs: Compiled database created in mapped library if successful, generates report else error
reported in log file

Steps for compilation:

1. Create work/library directory (most of the latest simulation tools creates automatically)
2. Map the work to library created (most of the latest simulation tools creates automatically)
3. Run the compile command with compile options

i.e Cadence IES command for compile: ncverilog +access+rwc -compile design.v
 Left side select the file and in Tools : launch verilog compiler with current selection will
get enable. Click it to compile the code
 Worklib is the directory where all the compiled codes are stored while Snapshot will have
output of elaboration which in turn goes for simulation
 compilation it will come under worklib you can see in right side window.

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Select the test bench and compile it. It will come under worklib. Under Worklib you can see the
module and test bench.

The cds.lib file is an ASCII text file. It defines which libraries are accessible and where they are
located. It contains statements that map logical library names to their physical directory paths.
For this Design, you will define a library called ―worklib‖

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Step 2: Elaboration:– To check the port connections in hierarchical design

Inputs: Top level design / test bench Verilog codes

Outputs: Elaborate database updated in mapped library if successful, generates report else error
reported in log file
Steps for elaboration – Run the elaboration command with elaborate options
1. It builds the module hierarchy
2. Binds modules to module instances
3. Computes parameter values
4. Checks for hierarchical names conflicts
5. It also establishes net connectivity and prepares all of this for simulation

Figure no1.14: Elaboration launch option

After elaboration the file will come under snapshot. Select the test bench and elaborate it.

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Step 3: Simulation: – Simulate with the given test vectors over a period of time to observe the
output behaviour

Inputs: Compiled and Elaborated top level module name

Outputs: Simulation log file, waveforms for debugging Simulation allow to dump design and
test bench signals into a waveform

Steps for simulation – Run the simulation command with simulator options

b) Synthesize the design using Constraints and analyse reports, critical path and Max
Operating Frequency.
Step 1: Getting Started
• Make sure you close out all the Incisive tool windows first.
• Synthesis requires three files as follows,
◦ Liberty Files (.lib)
◦ Verilog/VHDL Files (.v or .vhdl or .vhd)
◦ SDC (Synopsis Design Constraint) File (.sdc)
◦ Step 2 : Creating an SDC File
• In your terminal type ―gedit counter_top.sdc‖ to create an SDC File if you do not have one.
• The SDC File must contain the following commands;
i. create_clock -name clk -period 2 -waveform {0 1} [get_ports "clk"]
_uncertainty 0.01 [get_ports "clk"]
v. set_input_delay ii. set_clock_transition -rise 0.1 [get_clocks "clk"]
iii. set_clock_transition -fall 0.1 [get_clocks "clk"]
iv. set_clock
-max 0.8 [get_ports "rst"] -clock [get_clocks "clk"]
vi. set_output_delay -max 0.8 [get_ports "count"] -clock [get_clocks "clk"]
vii. set_input_transition 0.12 [all_inputs]
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viii. set_load 0.15 [all_outputs]

ix. set_max_fanout 30.00 [current_design]
i→ Creates a Clock named ―clk‖ with Time Period 2ns and On Time from t=0 to
t=1. ii, iii → Sets Clock Rise and Fall time to 100ps.

iv → Sets Clock Uncertainty to 10ps.

v, vi → Sets the maximum limit for I/O port delay to 1ps.

• The Liberty files are present in the below path,

/home/install/FOUNDRY/digital/<Technology_Node_number>nm/dig/lib/
• The Available technology nodes are 180nm ,90nm and 45nm.
• In the terminal, initialize the tools with the following commands if a new terminal is being
used.
• csh
• source /home/install/cshrc
• The tool used for Synthesis is ―Genus‖. Hence, type ―genus -gui‖ to open the tool.
• The Following are commands to proceed,
• read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
• read_hdl counter.v
• elaborate
• read_sdc constraints_top.sdc //Reading Top Level SDC
• set_db syn_generic_effort medium //Effort level to medium for generic, mapping
• and optimization
• set_db syn_map_effort medium
• set_db syn_opt_effort medium
• syn_generic
• syn_map
• syn_opt //Performing Synthesis Mapping and Optimisation
• report_timing > counter_timing.rep
• //Generates Timing report for worst datapath and dumps into file
• report_area > counter_area.rep
• //Generates Synthesis Area report and dumps into a file
• report_power > counter_power.rep
• //Generates Power Report [Pre-Layout]
• write_hdl > counter_netlist.v //Creates readable Netlist File

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• write_sdc > counter_sdc.sdc //Creates Block Level SDC

Commands 1-5 are intended for Synthesis process while 11-15 for Generating reports and
Outputs.
Note :-
1) report_timing gives you the path with highest failing slack where
Setup Slack = Required Time – Arrival Time.
2) Worst Setup Slack ==> Highest Arrival time ==> Highest Propagation Delay.
3) Maximum Clock Frequency = 1/ (Max Data Path Delay – Min Clock Path Delay + Tsetup)
All the Information can be gathered from report_timing.
4) The Cells given in the netlist can be checked in the .lib files for their properties.
c) Compilation, Simulation and Synthesis of 32-bit Up/Down Counter.

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Source Code
`timescale 1ns/1ps //Defining a Timescale for Precision
module counter(clk,rst,m,count); //Defining Module and Port List
input clk,rst,m; //Defining Inputs
output reg [31:0]count; //Defining 4-bit Output as Reg type
always@(posedge clk or negedge rst) //The Block is executed when
begin //EITHER of positive edge of clock
if(!rst) //or Neg Edge of Rst arrives
count=0; // Both are independent events
if(m)
count=count+1;
else
count=count-1;
end
endmodule

Test Bench
`timescale 1ns/1ps //Creating Time Scale as in Source Code
module counter_test; //Defining Module Name without Port List
reg clk, rst,m; //Defining I/P as Registers [to Hold Values]
wire [31:0] count; //Defining O/P as Wires [To Probe Waveforms]
initial
begin
clk=0; //Initializing Clock and Reset
rst=0;#25; //All O/P is 4‘b0000 from t=0 to t=25ns.
rst=1; //Up-Down counting is allowed at posedge clk
end
initial
begin
m=1; //Condition for Up-Count
#600 m=0; //Condition for Down-Count
rst=0;#25;
rst=1;
#500 m=0;
end
counter counter1(clk,m,rst, count); //Instantiation of Source Code
always #5 clk=~clk; //Inverting Clk every 5ns
initial
#1400 $finish; //Finishing Simulation at t=1400ns
Endmodule

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The procedure for Simulation and Synthesis remains same as mentioned earlier.

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ASIC Digital design

EXPERIMENT-1:-4-Bit Adder
1. To write a verilog code for 4bit adder and verify the functionality using Test bench.
• Synthesize, Analyse Reports and Netlist, Critical Path and Max Operating Frequency.
• From the report generated find the total number of cells, power requirement and
total area requirement.

Aim: To write a verilog code for 4-bit adder and verify the functionality using Test bench.
• Synthesize, Analyze Reports and Netlist, Critical Path and Max Operating Frequency.
• From the report generated find the total number of cells, power requirement and total area
requirement.
Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus
Design Information and Bock Diagram:
A full adder is a combinational circuit that performs the arithmetic sum of three input bits Ai,
addend Bi and carry in C in from the previous adder. Its results contain the sum Si and the carry
out, C out to the next stage. So to design a 4-bit adder circuit we start by designing the 1 –bit full
adder then connecting the four 1-bit full adders to get the 4-bit adder as shown in the diagram
below. For the 1-bit full adder, the design begins by drawing the Truth Table for the three input
and the corresponding output SUM and CARRY.

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Source Code – fa.v

module full_adder( A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
assign S = A^B^CIN;
assign COUT = (A&B) | (CIN&(A^B));
endmodule

Source Code – fa_4bit.v

module four_bit_adder(A,B,C0,S,C4);
input [3:0] A,[3:0] B; input C0;
output [3:0] S; output C4;
wire C1,C2,C3;
full_adder fa0 (A[0],B[0],C0,S[0],C1);
full_adder fa1 (A[1],B[1],C1,S[1],C2);
full_adder fa2 (A[2],B[2],C2,S[2],C3);
full_adder fa3 (A[3],B[3],C3,S[3],C4);
endmodule

Test Bench – fa_test.v

module test_4_bit;
reg [3:0] A;
reg [3:0] B;
reg C0;
wire [3:0] S;
wire C4;
four_bit_adder dut(A,B,C0,S,C4);
initial begin
A = 4'b0011;B=4'b0011;C0 = 1'b0; #10;
A = 4'b1011;B=4'b0111;C0 = 1'b1; #10;
A = 4'b1111;B=4'b1111;C0 = 1'b1; #10;
end
initial

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#50 $finish;
endmodule

b) Synthesis and Report/Output Analysis

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EXPERIMENT-2: Shift andAdd Multiplier

2. To Write Verilog Code for 4-bit Shift and Add Multiplier.

• Verify the Functionality using Test-bench
• Synthesize the design by setting proper constraints and obtain the netlist.
• From the report generated identify Critical path, Maximum delay, Total number of
cells, Power requirement and Total area required

Aim: To write a verilog code for 4 bit Shift and Add Multiplier and verify the functionality using
Test bench.
a. Synthesize, Analyse Reports and Netlist, Critical Path and Max Operating Frequency.
b. From the report generated find the total number of cells, power requirement and total area
requirement.

Tools Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Flow Chart:

Binary multipliers are used for multiplication of 2 binary numbers and are used mainly in signal
processing and also in other computationally intensive applications. Shift and add binary multiplier is a
type of sequential multiplier. Sequential multipliers generate the partial products sequentially and add
each newly generated partial product to the previously accumulated sum. Shift and add binary multiplier
is a type of sequential multiplier
Consider the multiplication of positive numbers. The first version of the multiplier circuit, which
implements the shift-and-add multiplication method for two n-bit numbers, is shown in Figure 2.1
The 2n-bit product register (A) is initialized to 0. Since the basic algorithm shifts the multiplicand register
(B) left one position each step to align the multiplicand with the sum being accumulated in the product
register, we use a 2n-bit multiplicand register with the multiplicand placed in the right half of the register
and with 0 in the left half.

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Figure 2.1: Block diagram of Shift and Add Multiplier

Figure 2.2: Flow Chart of Shift and Add Multiplier Algorithm

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//VERILOG CODE FOR SHIFT AND ADD MULTIPLIER

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//test bench for Shift and Add Multiplier

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Figure 2.3: Simulation results of Shift and Add Multiplier

b) Synthesis and Report/Output Analysis

Step 1: Getting Started

Make sure you close out all the Incisive tool windows first.
Synthesis requires three files as follows, Liberty Files (.lib)
Verilog/VHDL Files (.v or .vhdl or .vhd)
SDC (Synopsis Design Constraint) File (.sdc)

Step 2 : Creating an SDC File

//Shift and Add Multiplier SDC COMMANDS

read_libs { /home/install/FOUNDRY/digital/180nm/dig/lib/slow.lib}
set DESIGN sftadd
read_hdl "shiftadd.v"
elaborate $DESIGN
set_input_delay -max 0.5 [all_inputs]
set_output_delay -max 0.5 [all_outputs]
set_input_transition 0.1 [all_inputs]
set_max_capacitance 20 [get_ports]
set_load 0.10 [all_outputs]
set_max_fanout 20.00 [current_design]
set_db syn_generic_effort medium
set_db syn_map_effort medium
set_db syn_opt_effort medium
syn_generic
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gui_show
syn_map
gui_show
syn_opt
gui_show
report_power
report_power >sftaddmul_power.rpt
report_area
report_area > sftaddmul _area.rpt
report_timing -unconstrained
report_timing -unconstrained > sftaddmul _timing.rpt
write_hdl
write_sdc
write_hdl sftaddmul_netlist.v
gui_show

Synthesis results- RTL Schematic :

Figure 2.3: Schematic Capture of Shift and Add Multiplier

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Experiment -3 : 32 bit ALU

3.Write a Verilog code for 32-bit ALU supporting four logical and four arithmetic operations, use
case statement and if statement for ALU behavioral modeling.

a. Perform functional verification using test bench.

b. Synthesize the design targeting suitable library by setting area and timing constraints .
c. For various constraints set, tabulate the area, power and delay for the synthesized netlist.
d. Identify the critical path and set the constraints to obtain optimum gate level netlist with
suitable constraints.

Compare the synthesis results of ALU modeled using IF and CASE statements.

Aim: Write a Verilog code for 32 bit ALU supporting four logical and four arithmetic operations,
use case statement and if statement for ALU behavioral modeling.
 To Verify the Functionality using Test Bench
 Synthesize and compare the results using if and case statements
 Identify Critical Path and constraints
Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

The ALU will take in two 32-bit values, and control line. An Arithmetic unit does the following
task like addition subtraction, multi-fiction and logical operations. As the input is given in 32 bit
we get 32 bit output. The arithmetic will show only one output at a time so a selector is necessary
to select one of the operators to select one of the operators.

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Creating a Work space:

• Create a new sub-Directory for the Design and open a terminal from the Sub-Directory.
a) To Verify the Functionality using Test Bench
Source Code – Using Case Statement :
module alu_32bit_case(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
case(f)
3'b000:y=a&b; //AND Operation
3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b010:y=a+b; //Addition
3'b011:y=a-b; //Subtraction
3'b100:y=a*b; //Multiply
default:y=32'bx;
endcase
end
endmodule
Test Bench :

module alu_32bit_tb_case;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;

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alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end
initial
#50 $finish;
endmodule
Source Code - Using If Statement :
module alu_32bit_if(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
if(f==3'b000)
y=a&b; //AND Operation
else if (f==3'b001)
y=a|b; //OR Operation
else if (f==3'b010)
y=a+b; //Addition
else if (f==3'b011)
y=a-b; //Subtraction
else if (f==3'b100)
y=a*b; //Multiply
else

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y=32'bx; end
endmodule
Test bench :
module alu_32bit_tb_if;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_if test(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end initial #50
$finish; endmodule
Wave Forms :

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b) Synthesize Design
• Run the synthesis Process one time for each code and make sure the output File names are
changed accordingly.
Synthesis Process :
1. read_libs /home/install/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl {alu_32bit_if.v (OR) alu_32bit_case.v} //Choose any one
3. elaborate
4. read_sdc constraints_top.sdc //Optional-Reading Top Level SDC
5. set_db syn_generic_effort medium //Setting effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt
//Performing Synthesis Mapping and Optimisation
11. report_timing > alu_timing.rep
//Generates Timing report for worst datapath and dumps into file
12. report_area > alu_area.rep
//Generates Synthesis Area report and dumps into a file
13. report_power > uart_power.rep
//Generates Power Report [Pre-Layout]
14. write_hdl > uart_netlist.v

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//Creates readable Netlist File

15. write_sdc > uart_sdc.sdc
//Creates Block Level SDC

Synthesis RTL Schematic :

Note :-
1. You can tabulate Area, Power and Timing Constraints using any of the SDC Constraints as
instructed.
2. Make sure, during synthesis the Report File Names are changed so that the latest reports do not
overwrite the earlier ones.

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Experiment – 4 D, SR, JK Flip flop

4. Write a verilog code for Latch and Flip-Flop, synthesize the design and compare the
synthesis report (D, SR, JK)
Aim : Write a verilog code for Latch and Flip-flops (D, SR, JK), Synthesize the design and
compare the synthesis report.

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

Latches and flip-flops are the basic elements for storing information. One latch or flip-flop can
store one bit of information. The main difference between latches and flip-flops is that for latches,
their outputs are constantly affected by their inputs as long as the enable signal is asserted.
In other words, when they are enabled, their content changes immediately when their inputs
change. Flip-flops, on the other hand, have their content change only either at the rising or falling
edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising
or falling edge of the clock, the flip-flop content remains constant even if the input changes.
There are basically four main types of latches and flip-flops: SR, D, and JK. The major differences
in these flip-flop types are the number of inputs they have and how they change state. For each
type, there are also different variations that enhance their operations.

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Verilog Codes for D-Flip Flop, JK-Flip Flop and SR-Flip Flop.
Source code for D-Flip Flop :
module DFF( Q,Qbar,D,Clk,Reset);
output reg Q;
output Qbar;
input D,Clk,Reset;
always @(posedge Clk)
begin
if (Reset == 1'b1) //If at reset
Q <= 1'b0;
else
Q <= D;
end
assign Qbar = ~Q;
endmodule
Source code for D-Latch :
module DFF( Q,Qbar,D,en,Reset);
output reg Q;
output Qbar;
input D,en,Reset;
assign Reset = ~D;
always @(en)
begin
if (Reset == 1'b1) //If at reset
Q <= 1'b0;
else
Q <= D;
end
assign Qbar = ~Q;
endmodule
Source code for SR Flip Flop :

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module Main(S,R,clk,Q,Qbar);
input S,R,clk;
output Q,Qbar;
reg M,N;
always @(posedge clk)
begin
M = !(S & clk);
N = !(R & clk);
end
assign Q = !(M & Qbar);
assign Qbar = !(N & Q);
endmodule

Source Code for SR Latch :

module Main(S,R,en,Q,Qbar);
input S,R,en;
output Q,Qbar;
reg M,N;
always @(en)
begin
M <= !(S & clk);
N <= !(R & clk);
end
assign Q <= !(M & Qbar);
assign Qbar <= !(N & Q);
endmodule
Source Code for JK Flip Flop :
module jkff(J, K, clk, Q);
input J, K, clk;
output reg Q,Qm;
always @(posedge clk)
begin
if(J == 1 && K == 0)
Qm = 1;
else if(J == 0 && K == 1)
Qm = 0;
else if(J == 1 && K == 1)
Qm = ~Qm;
end
endmodule

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Source code of JK Latch

: module jkff(J, K, en, Q); input
J, K, en;
output reg Q,Qm;
always @(en)
begin
if(J == 1 && K == 0)
Qm <= 1;
else if(J == 0 && K == 1) Qm <= 0;
else if(J == 1 && K == 1)
Qm <= ~Qm;
End
Endmodule
Wave Forms for D-Flip Flop:

Figure 5: Simulation Waveform of D Flip-Flop

a) Synthesize the Design & Comparing Reports

Synthesis Commands :
1. read_libs /home/install_run/FOUNDRY/digital/90nm/dig/lib/slow.lib
2. read_hdl dff.v
3. elaborate
4. read_sdc constraints_top.sdc
5. set_db syn_generic_effort medium
6. set_db syn_map_effort medium
7. set_db syn_opt_effort medium
8. syn_generic
9. syn_map
10. syn_opt
11. report_timing > dff_timing.rep
12. report_area > dff_area.rep
13. report_power > dff_power.rep
14. write_hdl > dff_netlist.v
15. write_sdc > dff_sdc.sdc

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Example for SDC:

Synthesis RTL Schematic :

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Experiment – 5
5.Four-bit (MOD 10) counter with Asynchronous reset, Verify the functionality, synthesize the
design and compare the synthesis report.
Aim : Write a verilog code for 4-bit (MOD 10) counter with asynchronous reset, Synthesize
the design and compare the synthesis report.
Tools Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus
Design Information :
A Mod-N counter is a type of digital counter that counts up to a specific number (N) and then wraps
back to zero. It's a sequential logic circuit that changes state on each clock pulse, counting through a
predetermined sequence of states. The number of states the counter cycles through before repeating is
called its modulus, and a Mod-N counter has a modulus of N.The counter sequence is the one in which,
the counter increments its value (from 0 to N-1) with each clock pulse. When the counter reaches N-
1, it resets back to 0, completing one count cycle. The modulus of a counter is the number of states it
cycles through before repeating, which is N for a Mod-N counter. For example, a 2-bit counter (with
states 00, 01, 10, 11) has a modulus of 4, making it a Mod-4 counter.
Verilog Codes for a Mod 10 counter with Asynchronous reset
a) Source code for Mod 10 counter with Asynchronous reset

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b)Testbench code for Mod 10 counter with Asynchronous reset

Figure 6: Simulation results of counter

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b) Synthesis and Report/Output Analysis

Figure 6: Synthesis results of counter

3. For the synthesized netlist carry out the following for any two above experiments.

a) Floor planning (automatic), identify the placements of pads

b) Placement and Routing, record the parameters such as no. of layers used for routing, flip
method for placement of standard cells, placement of standard cells, routes of power and
ground, and routing of standard cells.
c) Physical verification and record the LVS and DRC reports.
d) Perform Back annotation and verify the functionality of the design.
e) Generate GDSII and record the number of masks and its color composition.

Aim: For the synthesized netlist carry out the following any two above experiments:

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 Floor planning, identify the placement of pads, placement and Routing

Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus
• Physical Design: Innovus
Mandatory Inputs for PD:
1. Gate Level Netlist [Output of Synthesis]
2. Block Level SDC [Output of Synthesis]
3. Liberty Files (.lib)
4. LEF Files (Layer Exchange Format)
Expected Outputs from PD:
1. GDS II File (Graphical Data Stream for Information Interchange – Feed In for Fabrication
Unit).
2. SPEF, SDF
• Make sure the Synthesis for the target design is done and open a terminal from the
corresponding workspace.
• Initiate the Cadence tools and cmd :innovus (Press Enter)
• For Innovus tool, a GUI opens and also the terminal enters into innovus command prompt
where in the tool commands can be entered.

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Physical Design involves 5 stages as following :

After Importing Design,
→ Floor Planning
→ Power Planning
→ Placement
→ CTS (Clock Tree Synthesis)
→ Routing Module
Importing Design
To Import Design, all the Mandatory Inputs are to be loaded and this can be done either using
script files named with .globals and .view/.tcl or through GUI as shown below. The target design
considered here is counter design The procedure shall remain the same for any other design from
the above discussed experiments.

1. For Synthesis, slow.lib was read as input. Each liberty file contains a pre-defined Process,
Voltage and Temperature (PVT) values which impact the ease of charge movement.
2. Process, Voltage and Temperature individually affect the ease of currents as depicted below.
3. Hence, slow.lib contains PVT combination (corner) with slow charge movement => Maximum
Delay => Worst Performance
4. Similarly, fast.lib contains PVT Combination applicable across its designs to give Fast charge
movement => Minimum Delay => Best Performance.

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5. When these corners are collaborated with the sdc, they can be used to analyse timing for setup
in the worst case and hold in the best case.
6. All these analysis views are to be manually created either in the form of script or using the
GUI.

Script under Default.globals file

Script under Default.view (or) Default.tcl file

Note : Check the paths to properly read in the input files.
• Else, if you would like to import your design using GUI, open the Innovus tool and from the
GUI, go to File → Import Design.
• A new pop-up window appears.
• First load the netlist. You can browse for the file and select ―Top cell : Auto Assign‖.

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Similarly select your lef files from /home/install/FOUNDRY/digital/90nm/dig/lef/ as shown

below.

Once both the Netlist and LEF Files are loaded, your import design window is as follows.

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In order to load the Liberty File and SDC, create delay corners and analysis view, select the ―Create
Analysis Configuration‖ option at the bottom.

An MMMC browser Pops Up.

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The order of adding the MMMC Objects is as follows.

1. Library Sets
2. RC Corners
3. Delay Corners
4. Constraints (SDC)
Once all of them are added, Analysis Views are created and assigned to Setup and Hold.
In order to add any of the objects, make a right click on the corresponding label → Select New.
• Adding Liberty Files under ―Library Sets‖

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 Similarly, add fast.lib with a label Fast or any identifier of your own.
 Adding RC Corners can also be done in a similar process. The temperature value can be
found under the corresponding liberty file. Also, cap table and RC Tech files can be added
from Foundry where available.

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Delay Corners are formed by combining Library Sets with RC Corners.

An example is shown below.

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Similarly, SDC can be read in under the MMMC Object of ―Constraints‖.

Analysis Views are formed from combinations of SDC and Delay Corner.

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Once ―Best‖ and ―Worst‖ Analysis views are created, assign them to Setup and Hold.

 Once all the process is done, Click on ―Save & Close‖ and save the script generated with
any name of your choice.
 Make sure the file extension remains .view or .tcl
 After saving the script, go back to Import Design window and Click ―OK‖ to load your
design

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 rectangular or square box appears in your GUI if and only if all the inputs are read
properly.
 If the box does not appear, check for errors in your log (Either on terminal or log file from
pwd)

The internal area of the box is called ―Core Area‖.

• The horizontal lines running along the width of Core are ―Standard Cell Rows‖. Every alternate
of them are marked indicating alternate VDD and VSS rows.
• This setup is called ―Flipped Standard Cell Rows‖.
→ Floorplan
Steps under Floorplan :
1. Aspect Ratio [Ratio of Vertical Height to Horizontal Width of Core]
2. Core Utilisation [The total Core Area % to be used for Floor Planning]
3. Channel Spacing between Core Boundary to IO Boundary
• Select Floorplan → Specify Floorplan to modify/add concerned values to the above Factors.
On adding/modifying the concerned values, the core area is also modified.

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The Yellow patch on the Left Bottom are the group of ―Unassigned pins‖ which are to be
placed along the IO Boundary along with the Standard Cells [Gates].
→ Power Planning
Steps under Power Planning :
1. Connect Global Net Connects
2. Adding Power Rings

3. Adding Power Strings

4. Special Route
Under Connect Global Net Connects, we create two pins, one for VDD and one for VSS connecting
them to corresponding Global Nets as mentioned in Globals file / Power and Ground Nets.

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1. Select Power → Connect Global Nets.. to create ―Pin‖ and ―Connect to Global Net‖ as shown and
use ―Add to list‖.
2. Click on ―Apply‖ to direct the tool in enforcing the Pins and Net connects to Design and then
Close the window.

In order to Tap in Power from a distant Power supply, Wider Nets and Parallel connections
improve efficiency. Moreover, the cells that would be placed inside the core area are expected to
have shorter Nets for lower resistance.
• Hence Power Rings [Around Core Boundary] and Power Stripes [Across Core Boundary] are
added which satisfies the above conditions.
• Select Power → Power Planning → Add Rings to add Power rings ‗around Core Boundary‘.

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Select the Nets from Browse option OR Directly type in the Global Net Names separated by a
space being Case and Spelling Sensitive.
• Select the Highest Metals marked ‗H‘ [Horizontal] for Top and Bottom and Metals marked ‗V‘
[Vertical] for Right and Bottom. This is because Highest metals have Highest Widths and thus
Lowest Resistance.
• Click on Update after the selection and ―Set Offset : Centre in Channel‖ in order to get the
Minimum Width and Minimum Spacing of the corresponding Metals and then Click ―OK‖.
• Similarly, Power Stripes are added using similar content to that of Power Rings.

Factors to be considered under Power Stripes :

→ Nets
→ Metal and It‘s Direction
→ Width and Spacing [Updated]
→ Set to Set Distance = ( Minimum Width of Metal + Min. Spacing ) x 2

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On adding Power Stripes, The Power mesh setup is complete as shown. However, There are no
Vias that could connect Metal 9 or Metal 8 directly with Metal 1 [VDD or VSS of Standard Cells
are generally made up of Metal 1].
• The connection between the Highest and Lowest Metals is done through Stacking of Vias done
using ―Special Route‖.
• To perform Special Route, Select Route → Special Route → Add Nets → OK.
• After the Special Route is complete, all the Standard Cell Rows turn to the Color coded for Metal
1 as shown below.
The complete Power Planning process makes sure Every Standard Cell receives enough power to
operate smoothly.
→ Pre – Placement :

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After Power Planning, a few Physical Cells are added namely, End Caps and Well Taps.
• End Caps : They are Physical Cells which are added to the Left and Right Core Boundaries acting
as blockages to avoid Standard Cells from moving out of boundary.
• Well Taps : They act like Shunt Resistance to avoid Latch Up effects.
To add End Caps, Select Place → Physical Cell → Add End Caps and ―Select‖ the FILL‘s from
the available list.
• Higher Fills have Higher Widths. As shown Below, The End Caps are added below your Power
Mesh.

To add Well Taps, Select Place → Physical Cell → Add Well Tap → Select →FillX [X → Strength
of Fill = 1,2,4 etc] → Distance Interval [Could be given in range of 30-45u] → OK

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Placement
1. The Placement stage deals with Placing of Standard Cells as well as Pins.
2. Select Place → Place Standard Cell → Run Full Placement → Mode → Enable ‗Place I/O
Pins‘ → OK → OK .

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All the Standard Cells and Pins are placed as per the communication between them, i.e., Two
communicating Cells are placed as close as possible so that shorter Net lengths can be used for
connections as Shorter Net Lengths enable Better Timing Results.

You can toggle the Layer Visibility from the list on the Right. The List of Layers available are
shown on the right under ―Layer‖ tab with colour coding.
Report Generation and Optimization :
1. Timing Report :
1. To generate Timing Report, Timing → Report Timing → Design Stage – PreCTS
2. Analysis Type – Setup → OK
3. The Timing report Summary can be seen on the Terminal.
2. Area Report :
1. cmd : report_area
3. Power Report :

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1. cmd : report_power

In case of any Violating paths, the design could be optimized in the following way.
To optimize the Design, Select ECO → Optimize Design → Design Stage [PreCTS] →
Optimization Type – Setup → OK

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After you run the optimization, the terminal displays the latest Timing report and updated area and
power reports can be checked.
• This step Optimizes your design in terms of Timing, Area and Power. You can Generate Timing,
Area, Power in similar way as above report Post – Optimization to compare the Reports.
Clock Tree Synthesis
• The CTS Stage is meant to build a Clock Distribution Network such that every Register (Flip
Flop) acquires Clock at the same time (Atleast Approximately) to keep them in proper
communication.
• A Script can be used to Build the Clock Tree as follows :

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Report Generation and Design Optimization :

• CTS Stage adds real clock into the Design and hence ―Hold‖ Analysis also becomes prominent.
Hence, Optimizations can be done for both Setup & Hold, Timing Reports are to be Generated for
Setup and Hold Individually.
Setup Timing Analysis :

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Routing :
1. All the net connections shown in the GUI till CTS are only based on the Logical connectivity.
2. These connections are to be replaced with real Metals avoiding Opens, Shorts, Signal Integrity
[Cross Talks], Antenna Violations etc.
3. To run Routing, Select Route → Nano Route → Route and enable Timing Driven and SI Driven
for Design Physical Efficiency and Reliability.

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Area and Power Reports :

Use the commands report_area and report_power for Area and Power Reports respectively.

As an alternate to the setAnalysisMode command, you can use the GUI at Tools → Set Mode →
Set Analysis Mode → Select On-Chip-Variation and CPPR.
• The Report generation is same as shown prior to Design Optimization.

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It is recommended to save Netlist and Design at every stage.

To restore a Design Data Base, type source <DesignName>.enc in the terminal.

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Physical Verification – Capturing DRC and LVS :

•After saving the routed Database, you can proceed for Physical Verification and capture the
DRC and LVS reports.
• Inputs Required – DRC :
◦ Technology Library and Rule Set
◦ GDS format giles of all Standard Cells (Given by Cadence at
/home/install/FOUNDRY/90nm/dig/gds for 90nm Tech node)
• Outputs – DRC :
◦ DRC Violation Report
◦ Physical Netlist (Optional)
From the Innovus GUI, select PVS → Run DRC to open the ―DRC Submission Form‖.

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• The Technology Library is specific for PVS Tool and technology node on which the design is
created.
• On reading the tech lib, the rule set is loaded and the corresponding fabrication rules are read in
to be checked against the design.

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• For example, in the above shown snapshot, the errors associated with N-Implant can be seen.
(Select a error occurrence and click on the right arrow below to highlight/zoom in the location.)
• You can save the DRC Run as a ―Preset‖ file to rerun the DRC if required at a later point of time.
• Saving/loading the Preset File is shown below.

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• From the Innovus GUI, Select PVS → Run LVS to open the LVS run submission form.

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Analog Design

Analog Design Procedure

1. Draw the schematic of the given circuit and create a symbol.

2. Create a test circuit and run the simulation by providing necessary inputs.
3. Extract the components from schematic and draw the layout.
4. Perform DRC, LVS and RC extraction.
5. Back annotate the design and verify the waveforms.

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Experiment 1: CMOS INVERTER

Objective:
(a) Capture the Schematic of a CMOS Inverter with Load Capacitance of 0.1 pF and set the Widths
of Inverter with
(i) WN = WP
(ii) WN = 2 WP
(iii) WN = WP / 2
and Length at selected Technology. Carry out the following:
1. Set the Input Signal to a pulse with Rise Time, Fall Time of 1 ps and Pulse Width of 10 ns, Time
Period of 20 ns and plot the input voltage and output voltage of the designed Inverter
2. From the Simulation Results, compute tpHL, tpLH and tPD for all the three geometrical
settings of Width
3. Tabulate the results of delay and find the best geometry for minimum delay for CMOS Inverter

Solution:
(a) Schematic Capture of CMOS Inverter
Table – 1: Length and Width of NMOS and PMOS Transistors for the condition WN = WP

Library Name Cell Name Comments / Properties

Width, WN = 850 n
gpdk180 Nmos
Length, L = 180 n
Width, WP = 850 n
gpdk180 Pmos
Length, L = 180 n

Table – 2: Length and Width of NMOS and PMOS Transistors for the condition WN = 2 * WP
Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 850 n
Length, L = 180 n
gpdk180 Pmos Width, WP = 1.7 u
Length, L = 180 n
Table – 3: Length and Width of NMOS and PMOS Transistors for the condition WN = WP / 2

Library Name Cell Name Comments / Properties

gpdk180 Nmos Width, WN = 850 n
Length, L = 180 n
gpdk180 Pmos Width, WP = 425 n
Length, L = 180 n

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Pin Names Direction

A, vdd, vout Input
Y Output
The complete Schematic after connecting the pins and terminals for all the three conditions WN =
WP, WN = 2 * WP, WN = WP / 2 is shown in Figure – 1.1(a), 1.1(b) and 1.1(c) respectively.

Figure – 1.1 (a): WN = WP Figure – 1.1 (b): WN = 2 * WP

Figure – 1.1 (c): WN = WP / 2

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SYMBOL:

Figure – 1.2: Inverter Symbol

Test Circuit:
Library Name Cell Name Comments / Properties

analogLib Vdc DC voltage = 1.8 V

analogLib Vpulse Voltage 1 = 0 V, Voltage 2 = 1.8

V, Period = 20n s, Delay time =
10n s, Rise time = 1p s, all time =
1p s, Pulse width = 10n s
analogLib Cap Capacitance = 100f F

analogLib Gnd

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Figure1.3: Test Schematic

Output Waveforms:

Figure – 1.4: Simulated waveforms

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CALCULATION OF tpHL, tpLH AND tPD:

To calculate the Propagation Delay (𝑡𝑡𝑡), the formula used is

where, 𝑡𝑡𝑡𝑡
Delay. To → Low𝑡𝑡
calculate – 𝑡𝑡
High
and Propagation
𝑡𝑡𝑡𝑡, Delay and 𝑡𝑡𝑡𝑡 → High – Low Propagation

1. In waveform window, execute tools calculator. Calculator window pops up.

2. Delete previous analysis by clicking on clear buffer icon.
3. In function panel click on special functions delay. Click on wave radio button.
4. In delay window, click on signal1, minimize calculator window and go to waveform window
and double click on input signal. Similarly select output signal for signal2. Set threshold values
for signal 1 as 0.75 and for signal 2 as 0.75.
a. For tpLH  set edge type for signal1 as falling and for signal2 as rising. Click on apply
ok. Press on execute buffer. Note down delay value.
b. For tpHL  set edge type for signal1 as rising and for signal2 as falling. Click on apply
ok. Press on execute buffer. Note down delay value.

The value of ―Switching Potential‖ should be mentioned under ―Threshold Value 1‖ and
―Threshold Value 2‖.

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Note:
What is Switching Potential?
Switching Potential is defined as the value of Input Voltage for which the Output
Voltage is equal to the Input Voltage.

How to obtain the value of Switching Potential?

To obtain the Switching Potential, use the “intersect” option from the Function Panel,
select the “Signal 1” and “Signal 2” from the DC Analysis waveform window, click
on “Apply”, click on “OK” and click on “Evaluate the buffer and display the results
in a table” icon as shown above to obtain the value.
Use the formula mentioned above to obtain the 𝑡𝑡𝑡. Obtain the values of 𝑡𝑡𝑡𝑡, 𝑡𝑡𝑡𝑡 and
𝑡𝑡𝑡 for all the three geometrical settings of Width.
TABULATED VALUES OF DELAY:

The results of 𝑡𝑡𝑡𝑡, 𝑡𝑡𝑡𝑡 and 𝑡𝑡𝑡 for all the required geometrical settings are tabulated below
Width setting MOSFET Width tpHL tpLH tpd
PMOS 850n
Wn=Wp 3.233E-10 7.049E-10 5.141E-10
NMOS 850n

PMOS 850n
Wn=2Wp 3.337E-10 4.700E-10 4.019E-10
NMOS 1.7u

PMOS 425n
Wn=Wp/2 1.141E-9 3.154E-10 7.282E-10
NMOS 850n

(b) Layout of CMOS Inverter with 𝑡𝑡 = 40

𝑡𝑡 20

Objective:
To draw the Layout of CMOS Inverter with 𝑡𝑡 = 40
using optimum Layout Methods. Verify for
𝑡𝑡 20

DRC and LVS, extract the Parasitics and perform the Post-Layout Simulations, compare the results
with Pre-Layout Simulations and record the observations.
Table - 4: Parameters for NMOS and PMOS Transistors
Library Name Cell Name Comments / Properties
Width, WN = 20u
gpdk180 Nmos
Length, L = 180 n
Width, WP = 40u
gpdk180 Pmos
Length, L = 180 n

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Schematic:

Figure – 1.5: Schematic for CMOS Inverter with 𝑡𝑡 = 40

𝑡𝑡 20

Symbol:

Figure – 1.6: Symbol for CMOS Inverter with 𝑡𝑡 = 40

20
𝑡𝑡

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Test Circuit:

Figure – 1.7: Test Schematic for CMOS Inverter with 𝑡𝑡 = 40

20
𝑡𝑡

Waveform:

Figure – 1.7 (a): Transient Analysis Figure – 1.7(b): DC Analysis

MOSFETOF 𝑡𝑡𝑡𝑡Length
VALUES , 𝑡𝑡𝑡𝑡 AND 𝑡𝑡𝑡:Width tpHL tpLH tpd
PMOS 180n 40u
1.228E-10 3.550E-11 7.920E-11
NMOS 180n 20u

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LAYOUT FOR CMOS INVERTER WITH 𝑡𝑡 = 𝑡𝑡

𝑡𝑡 𝑡𝑡

Figure – 1.8: Completed Layout with Template

VALUES OF 𝑡𝑡𝑡𝑡, 𝑡𝑡𝑡𝑡 AND 𝑡𝑡𝑡:

MOSFET Length Width tpHL tpLH tpd

PMOS 180n 40u
1.23E-10 3.55E-11 7.78E-11
NMOS 180n 20u

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Experiment 2: T W O - INPUT CMOS NOR GATE

Objective:
Capture the schematic of 2-input CMOS NOR gate having similar delay as that of CMOS
inverter computed in experiment above. Verify the functionality of NOR gate and also find
out the delay td for all four possible combinations of input vectors. Table the results.
Increase the drive strength to 2X and 4X and tabulate the results.

SCHEMATIC CAPTURE:

Table- 5: Width and Length of NMOS and PMOS Transistors for CMOS NOR Gate

Library Name Cell Name Comments / Properties

gpdk180 Nmos Width, WN = 1.7 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 1.275 u
Length, L = 180 n

Table-6 : Width and Length of NMOS and PMOS Transistors for CMOS NOR Gate with
Drive Strength “2”

Library Name Cell Name Comments / Properties

gpdk180 Nmos Width, WN = 3.4 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 2.55 u
Length, L = 180 n

Table-7: Width and Length of NMOS and PMOS Transistors for CMOS NOR Gate with
Drive Strength “4”

Library Name Cell Name Comments / Properties

gpdk180 Nmos Width, WN = 6.8 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 5.1 u
Length, L = 180 n

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Schematic:

Figure – 2.1: Schematic Capture of 2 – input CMOS NOR Gate (NOR2X1)

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Symbol:

Figure– 2.4: Symbol of a 2 – input NOR Gate

Test Schematic:

Figure– 2.5: Test Schematic for 2 – input CMOS NOR Gate

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Launch ADE L, select ―Setup → Stimuli‖ as shown in Figure 2.6 to give the required sequence
of inputs to pins A and B.

Figure – 2.6: Setup - Stimuli

Select ―Stimulus Type → Inputs‖ and the input pins A and B get listed out. Select any one of the
Inputs, click on ―Enabled‖ and select ―Function → bit‖. Mention the value of voltages for ―Logic 0‖ and
―Logic 1‖ in ―One value → 1.8‖ and ―Zero value → 0‖.

The “Setup Analog Stimuli” window pops up as shown in Figure – 2.7. Select “Stimulus Type
Inputs” and the input pins A and B get listed out as shown in Figure – 2.7. Select any one of
the Inputs, click on “Enabled” and select “Function bit”.
Mention the value of voltages for “Logic 0” and “Logic 1” in “One value as 1.8” and
“Zero value as 0”. Consider the values of Rise time, Fall time and Period similar to that
considered in Lab – 01.

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Figure – 2.7: Setup Analog Stimuli window

Select “Source type = bit”, “Pattern Parameter data = 11001001”, “Pattern Parameter rptstart
= 1”, “Pattern Parameter rpttimes = 0” and “Trigger=Internal”, click on “Apply” to “Turn ON”
the input and click on “OK”. Select the type of Analysis to be performed on the 2 – input
CMOS NOR Gate. Select the Input and Output Signals to be plotted. Run the Simulation to
check for the functionality of the NOR Gate.

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The Simulated waveforms can be seen as shown in Figure – 2.8.

Figure 2.8 : Transient analysis of 2-input NOR gate

Table -8: Values of Delay for 2 – input CMOS NOR2X1, NOR2X2 and NOR 2X4

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Experiment 3: Construct the schematic for a Boolean expression using

CMOS logic

Objective:
Construct the schematic of the Boolean Expression Y= AB+CD+E using CMOS Logic.
Verify the functionality of the expression. Find out the delay td for some combination of input vectors.
Tabulate the results.

Table – 16: Width and Length of NMOS and PMOS Transistors

Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 6 u
Length, L = 180 n

gpdk180 Pmos Width, WP = 8.85 u

Length, L = 180 n

The completed Schematic is shown in Figure – 3.1.

Figure – 3.1: Schematic of Boolean expression using CMOS-logic

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Figure – 3.2: Symbol of Boolean expression using CMOS-logic

FUNCTIONAL SIMULATION:
The pull up and pull-down network consist of combination of transistor, where two or more
transistors in series are ON only if all of the series transistors are ON. Two or more transistors in
parallel are ON if any of the parallel transistors are ON. This is illustrated in Figure 2 for nMOS and
pMOS transistor pairs. By using combinations of these constructions, CMOS combinational gates can
be constructed. In general, when we join a pull-up network to a pull-down network to form a logic gate
as shown in Figure 1, they both will attempt to exert a logic level at the output. When both pull-up
and pull-down are OFF, the high impedance or floating Z output state results. This is of importance in
multiplexers, memory elements, and tristate bus drivers. The crowbarred (or contention) X level exists
when both pull-up and pull-down are simultaneously turned ON. Contention between the two networks
results in an indeterminate output level and dissipates static power. It is usually an unwanted condition.

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Figure 3.3 Test Schematic of Boolean expression using CMOS-logic

Give the pulse inputs as stated in table below

Voltage Name Time period Pulse Width

V0(A) 160ns 80ns
V1(B) 80ns 40ns
V2(C) 40ns 20ns
V3(D) 20ns 10ns
V4(E) 10ns 5ns

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Figure – 3.4: Simulation Window of Boolean expression using CMOS-logic

Note : For Delay Calculations: Follow the steps as in Inverter design

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Experiment 4: COMMON SOURCE AMPLIFIER WITH PMOS CURRENT MIRROR

LOAD
Objective:
(a) Capture the Schematic of a Common Source Amplifier with PMOS Current Mirror Load and
find its Transient Response and AC Response. Measure the UGB and Amplification Factor by
varying transistor geometries, study the impact of variation in width to UGB.
(b) Draw the layout of Common Source Amplifier, use optimum layout methods. Verify
DRC and LVS, extract the parasitics and perform the post layout simulation, compare the
results with pre layout simulations. Record the observations.
Solution – (a):
SCHEMATIC CAPTURE:
Following the techniques demonstrated in Lab – 01, Create a New Library using the option
―File → New → Library‖, create a New Cell View upon selecting the newly created library
using the option ―File → New → Cell View‖ and instantiate the required devices using the
―Create → Instance‖ option.
The device parameters are listed in Table 9.

Table –9: Width and Length of NMOS and PMOS Transistors

Library Name Cell Name Comments / Properties
gpdk180 Nmos Width, WN = 6 u
Length, L = 180 n
gpdk180 Pmos Width, WP = 8.85 u
Length, L = 180 n
The completed Schematic is shown in Figure 4.1

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Figure – 4.1: Schematic of Common Source Amplifier with PMOS Current Mirror Load

The symbol for the Common Source Amplifier with PMOS Current Mirror Load is shown in
Figure.4.2

Figure – 4.2: Symbol of Common Source Amplifier with PMOS Current Mirror Load

FUNCTIONAL SIMULATION:
Using the symbol created, build the Test Schematic. Create a New Cell View, instantiate the

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symbol of Common Source Amplifier with PMOS Current Mirror Load, DC Voltage Source,
Current Source, AC Voltage Source, Capacitance, Resistance and Ground, connect the using
wires

Figure – 4.3: Test Circuit

The parameters for remaining devices are shown in Table 10.

Table – 10: Parameters for the devices used in Test Schematic

Launch ADE L, import the design variables, mention the values and select the Transient
Analysis, DC Analysis and AC Analysis, mention the parameters and choose the signals to be
plotted as shown in Figure.

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Figure -4.4: Updated ADE L window

The Simulated waveforms can be seen as shown in Figure 4.5.

Figure – 4.5: Transient Analysis

Figure – 4.6: AC Analysis

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To measure the Gain and Unity Gain Bandwidth, go back to the ADE L window, select
―Results → Direct Plot → AC Magnitude & Phase‖ as shown in Figure – 4.7. The Test
Schematic window pops up, select the output net as shown in Figure – 3.8 and click
on ―Esc‖ key on the keyboard. The waveform can be seen as shown in Figure – 4.9. The marker
placed on the low frequency part of the response gives the DC Gain, use the bind key ―M‖ to place
the marker. Place a horizontal cursor at ―0 dB‖ and the crossing frequency gives the Unity Gain
Bandwidth (UGB) as shown in Figure.

Figure-4.7: Results → Direct Plot → AC Magnitude & Phase

Figure-4.8 : Selecting Output Net from the Test Schematic

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Figure – 4.9: Gain and Phase plot

Solution – (b):
LAYOUT:
Follow the techniques demonstrated in Lab – 01 to open the Layout Editor, import the devices
from the Schematic, place the devices as per the requirement and complete the routing. The
completed layout can be seen as shown in Figure 4.10

Figure – 4.10: Layout for Common Source Amplifier with PMOS Current Mirror Load

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Experiment 5: TWO-STAGE OPERATIONAL AMPLIFIER

Objective:
(a) Capture the Schematic of a 2 – Stage Operational Amplifier and measure the following:
1. UGB
2. dB Bandwidth
3. Gain Margin and Phase Margin with and without coupling capacitance
4. Use the Op-Amp in the Inverting and Non-Inverting configuration and verify its
functionality
5. Study the UGB, 3 dB Bandwidth, Gain and Power Requirement in Op-Amp by varying
the stage wise transistor geometries and record the observations.

(b) Draw the layout of 2 – stage Operational Amplifier with the maximum transistor width set to 300
(in 180 / 90/ 45n m Technology), choose appropriate transistor geometries as per the results obtained
in 4(a). Use optimum layout methods. Verify DRC and LVS, extract the parasitics and perform the
post layout simulation, compare the results with pre layout simulations. Record the observations.

Solution – (a): SCHEMATIC CAPTURE:

Create a New Library, select the Technology Node as ―gpdk045‖ (Technology Node used for
this demonstration is 45 nm), Create a New Cell View, instantiate the devices as demonstrated in
Lab – 01. Use the ―Sideways‖ option as shown in Figure – 5.1 to flip the Transistor.

Figure 5.1 “Sideways option to flip the transistors Figure 5.1 (a) before and Figure 5.1(b) after
selecting sideways

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The Transistors before and after flipping are shown in Figure – 5.1(a) and Figure – 5.1(b). The dimensions of
all the devices are given in Table – 11 as shown below.

Table – 11: Device Parameters for 2 – Stage Operational Amplifier.

The Transistors before and after flipping are shown in Figure –5.1(a) and Figure – 5.1(b). The
dimensions of all the devices are given in Table – 11 as shown below.
Library Name Transistor Cell Name Comments /
Properties
gpdk045 M0, M1 pmos2v Width, W = 465 n
Length, L = 150 n
gpdk045 M3, M4 nmos2v Width, W = 490 n
Length, L = 150 n
gpdk045 M5, M7 nmos2v Width, W = 1.09 u
Length, L = 150 n
gpdk045 M2 pmos2v Width, W = 10 u
Length, L = 150 n
gpdk045 M6 nmos2v Width, W = 6.88 u
Length, L = 150 n
gpdk045 M8 pmoscap2v Calculated Parameter=
Capacitance Capacitance
=250.043 f

The completed Schematic as per the dimensions mentioned in Table – 18 is shown in Figure –5.2.

Figure – 5.2: Schematic of 2 – Stage Operational Amplifier

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The Symbol created according to the Techniques demonstrated in Lab – 01 is shown in Figure–
5.3.

Figure – 5.3: Symbol for 2 – Stage Operational Amplifier

FUNCTIONAL SIMULATION USING ADE EXPLORER AND ASSEMBLER:

To test the functionality of Operational Amplifier, build a Test Schematic using the Symbol
that was created as shown in Figure – 4.3. Create a New Cell View, instantiate the symbol.
Instantiate the other devices required for testing the circuit, mention the device parameters as
shown in Table – 19.
Table – 12: Device Parameters for 2 – Stage Operational Amplifier Test Schematic

Library Name Cell Name Comments Properties

analogLib vdc DC voltage = vdd V

analogLib vdc DC voltage = vss V

analogLib Vpulse Voltage 1 = vdc + 0.3 V, Voltage

2 = vdc -

0.3 V, Period = 10u s, Rise time

= 10p s,

Fall time = 10p s

analogLib Idc DC current = ibias A

analogLib Cap Capacitance = CL F

analogLib Gnd

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The Test Schematic after completion of all the interconnections can be seen as shown
in Figure – 5.4

Figure – 5.4: Test Schematic for 2 – Stage Operational Amplifier Schematic for 2

– Stage Operational Amplifier

The specification that has to be achieved on simulating the design are as follows:
• Slew Rate >= 50 MV/s
• DC Open Loop Gain >= 60 dB (1000 V/V)
• Unity Gain Bandwidth >= 50 MHz
• Output Offset <= ± 10 mV
• Settling Time <= 50 ns
The steps to be carried out are listed below:
Step – 1:
Select ―Launch → ADE Explorer‖ as shown in Figure – 4.5.
The ―Launch ADE Explorer‖ window pops up, select ―Create New View‖ and click on ―OK‖ as
shown in Figure – 5.6.

Figure – 5.6: “Launch ADE Explorer” window

The ―Create new ADE Explorer view‖ window pops up as shown in Figure – 5.7. Select the
Cell View Name, ―Open in → new tab‖ and click on ―OK‖

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Figure – 5.7: “Create new ADE Explorer view” window

The ―Virtuoso ADE Explorer Editing‖ window pops up as shown in Figure – 5.8

Select ―Setup → Model Libraries‖

Figure 5.9 Setup Model Libraries

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The ―spectre1: Model Library Setup‖ Select the respective ―.scs‖ file and the process corner as
―tt‖. Click on ―OK‖.

Figure 5.10

To analyze the circuit through Transient Analysis and AC Analysis, select “Click to addanalysis” just below
the “Analyses” option in the “Setup” window as shown in Figure

Figure 5.11
The “Choosing Analyses – ADE Explorer” window pops up as shown in Figure – 5.12.

Select the “tran” for the “Transient Analysis” and “dc” for the “DC Analysis”.
The ADE Explorer window gets updated as shown in Figure – 5.13.
Mention the values for the Design Variables defined in the Schematic of the 2 – Stage Operational
Amplifier The defined values for the respective Design Variables are given in Table – 20. The Design
Variables along with the values in ADE Explorer window is shown in Figure – 5.13.

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Figure 5.12

Figure 5.12

Name of the Variable Value

CL 1p
ibias 10u
vdc 1
vdd 2
vss 0
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Table – 13: Design Variables and its Values.

To specify the outputs for the simulation, select ―Tools → Calculator‖ as shown in Figure –
5.14.

Figure – 5.14: Tools → Calculator

The ―Virtuoso Visualization & Analysis XL calculator‖ window pops up as shown in Figure – 5.15.

Figure – 5.15: “Virtuoso Visualization & Analysis XL calculator” window

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Select ―vt‖ as shown in Figure – 5.15. The Test Schematic pops up as shown in Figure – 5.16.
Select the output net ―OUT‖ from the Schematic and the Buffer window in the Calculator gets
updated as shown in Figure – 5.17.

Figure – 5.16: Test Schematic

Figure – 5.17: Updated Buffer window

Click on ―Send buffer expression to ADE Outputs‖ option to get the expression from the Buffer

window into ADE Explorer as shown in Figure – 5.18

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Figure – 5.19: Updated ADE Explorer

Initially, the ―Name‖ column would be blank, use the left mouse click to rename (for eg:
vout_tran). Similarly, select ―vt‖ again, to select the input net ―IN‖ and then select ―vdc‖ from the
calculator, select the input net and the output net from the Test Schematic, rename it for easier
identification. The updated ADE Explorer can be seen as shown in Figure – 5.19.

Click on the ―Upward Arrow‖ just before the Test Circuit name in the Setup tab to invoke the
ADE Assembler as shown in Figure – 5.20. The ADE Assembler allows multiple tests to be
simulated on the same environment.

Figure – 5.20: ADE Assembler invoked

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Figure – 5.21: Create Test Copy

Expand ―Tests‖ and use the left mouse click to select the Test Circuit and use the right mouse click
to select ―Create Test Copy‖ as shown in Figure – 5.21.
Use a left mouse click to select the ―Copied Test‖ (for eg: FDP_45_opamp_org:Op_amp_
tran_test:1:1) as shown in Figure – 5.22. Left mouse click again to rename it to
FDP_45_opamp_org: Op_amp_ ac_test:1 as shown in Figure – 5.22.

Figure – 5.22: Copied Test

Left mouse click again to rename it to FDP_45_opamp_org:Op_amp_ ac_test:1 as shown in

Figure – 5.23

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Figure – 5.23: Renamed Test

To verify the selected design for ―ac‖ test, right mouse click on the test and select ―Design‖ as shown
in Figure 5.24.

The ―Choose Design – ADE Assembler‖ window pops up as shown in Figure – 5.25.
Select the Library, Cell Name, ―View Name → Schematic‖ and click on ―OK‖.
Select all the tests related to ―ac‖ from the ―Outputs Setup‖ and delete them.
Select the ―ac‖ test from the ―Data View‖ window, expand, select ―Analyses‖ and remove
the―tran‖ and ―dc‖ analysis that were copied.The updated ADE Assembler window is shown in
Figure – 5.26.

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Figure – 5.24: Select “Design” option

Figure – 5.25: Select the “Op_amp_ac” Cell Name

Figure – 5.26: Updated ADE Assembler

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Select ―Click to add analysis‖ option from the Analyses option to select the ―ac‖ analysis for the Test
Schematic. The parameters are shown in Figure – 5.27.Figure – 5.27: “ac” analysis Click on
―Apply‖, click on ―OK‖ to see the ADE Assembler updated as shown in Figure –4.28.

Figure – 5.27: “ac” analysis

Figure 5.28

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Expand the ―Design Variables‖, add ―vac‖ as the variable and ―100m‖ as its value by selecting the
―Click to add variable‖ option. The updated Design Variables are shown in Figure – 4.28.

Figure – 4.28: Updated Design Variables

Select ―Tools → Calculator‖ and select the ―ac‖ analysis test circuit as shown in Figure –
4.29.

Figure – 4.29: Selecting “ac” test from calculator

Select ―vf‖ which accesses voltage over frequency and select the output net from the Test
Schematic. The updated Buffer can be seen in Figure – 4.30.
Figure 5.29

Figure 5.30

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Figure – 5.30: Updated Buffer after “vf” and output net selection
Similarly, select the input net from the Test Schematic. The buffer and stack gets updated as
shown in Figure – 4.31.

Figure – 5.31: Updated Buffer and Stack

Click on ― / ― from the keypad as shown in Figure – 5.31. The expression in the Buffer gets
updated as shown in Figure – 5.32

Figure – 5.32: Updated Buffer and Stack

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Select ―dB20‖ from the Function Panel, the expression in buffer gets updated as shown in
Figure – 5.33.

Figure – 5.33: Updated Buffer after selecting “dB20”

This expression calculates the Gain in dB for the Amplifier. Click on ―Send buffer expression to
ADE Outputs‖. Rename the expression and the updated ADE Assembler can be seen as shown in
Figure – 5.34.

Figure – 5.34: Expression from the Calculator

Click on ―Run Simulation‖ option as shown in Figure – 5.34 to simulate the design. The ADE
Assembler after simulation is shown in Figure – 5.35.

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Figure – 5.35: ADE Assembler after simulation

Select ―Options → Plotting/Printing‖ as shown in Figure – 5.36.

Figure – 5.36: Options → Plotting/Printing

The ―ADE Assembler Plotting/Printing Options‖ window pops up as shown in Figure – 5.3.
Select ―Plotting Option → Auto‖ and uncheck ―Plot Scalar Expressions‖, click on ―OK‖ as shown
in Figure – 5.37.

Figure – 5.37: ADE Assembler Plotting/Printing Options” window

Click on ―Plot All‖ to see the waveforms as shown in Figure – 5.38

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Figure – 5.38: “Plot All” option

The plotted waveforms can be visualized in the ―Virtuoso Visualization & Analysis XL‖

window as shown in Figure – 5.39.

Figure – 5.40: Measurements → Transient Measurement

The Slew Rate can be checked out as shown in Figure – 5.41.
To calculate the Settling Time, consider the time the wave takes to reach and stay between (+/-
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1%) of its final value in comparison with the initial value. This is calculated as follows:
Lower Bound = 99 % * (1.3 V – 0.7 V) + 0.7 V = 1.294 V
Upper Bound = 101 % * (1.3 V – 0.7 V) + 0.7 V = 1.306 V
Right Mouse click on X-axis properties, ―Independent Axis Properties for time‖ window
pops up as shown in Figure – 5.42.

Figure – 5.41: Transient Measurement tab

Figure – 5.42: “Independent Axis Properties for time” window

Select the ―Scale‖ tab, select ―Mode → Manual‖, mention Axis Limits ―Minimum → 4.98us‖,
―Maximum → 5.04u s‖ and Divisions ―Minor → 10‖, ―Major → 30‖, click on ―OK‖ as shown in
Figure – 5.42. This will isolate the edges that are to be analyzed as shown in Figure– 5.43

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Figure – 5.43: Isolated Waveforms

Use left mouse click and drag and drop to combine the waveforms as shown in Figure – 5.45
Use the bind key ―M‖ to setup a Marker at the required time instance as shown in Figure –
5.45.

Figure – 5.45

Use the bind key ―H‖ to setup horizontal cursors at 1.294 V and 1.306 V as shown in Figure –
5.46.

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Use the zooming options to zoom-in and zoom-out as and when required. Setup a marker on
the lower horizontal cursor as shown in Figure – 5.47.

Figure – 5.46: Horizontal cursors at 1.294 V and 1.306 V

Figure – 5.47: Marker on the 2nd horizontal cursor

The difference between the timing instances gives the Settling Time as 12.5n s.
Without closing the waveform window, open the ―maestro‖ in the ADE Assembler.
For this simulation, the output dc value is 1.298 V and the input dc value is 1.3 V.
The difference gives the DC Offset (1.298 V – 1.3 V = 2m V).
From the AC Analysis curve, set the marker on the low frequency portion of the signal as
shown in Figure – 5.48.
The marker reading gives the DC Open Loop Gain which is 50.98 dB.
Setup a horizontal cursor at 0 dB as shown in Figure – 5.49. The point of intersection of the
cursor with the AC Analysis curve gives the Unity Gain Bandwidth.

The Unity Gain Bandwidth is measured as 84.51M Hz.

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GENERATING THE EXPRESSIONS:

To improve productivity, create reusable expressions rather than using the measurements from
waveforms.To generate the expressions, open the ―Outputs Setup‖ tab from ADE Assembler, click
on―Add new output‖ as shown in Figure – 5.51.

Figure – 5.51: “Add new output” option

Select ―FDP_45_opamp_org:Op_amp_tran_test → Expression‖ as shown in Figure 5.51.

Figure – 5.51: FDP_45_opamp_org:Op_amp_tran_test → Expression

For the new expression, click on the ―Details‖ column and click on ―Open expression
builder‖ as shown in Figure – 5.52. Type ―Slew‖ and the auto-completion can be seen. Select
―slewRate‖ as shown in Figure – 5.53

Figure -5.52: Open expression builder

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Figure – 5.53: “slewRate” auto-completion

Scroll down and select ―vout_tran‖, it points to the next parameter. Mention the values and the
completed expression can be seen as shown in Figure – 4.54.

Figure – 5.54: Completed expression

The values for the remaining parameters are given below:
initialValue - 1.3 percentLow - 20
initalValueType – nil percentHigh - 80
finalValue - 0.7 percentHigh - 80
finalValueType - nil numberOfOccurences - nil
sweepName – time
Click on the ―closing parenthesis‖ to complete the expression. Click on the ―Green‖ colored tick
mark to update the expression in the ―Details‖ tab as shown in Figure – 5.55.

Figure – 5.55: Expression updated in ADE Assembler

Mention a ―Name‖ for the created expression as shown in Figure – 5.56.

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Figure – 5.56: Naming the expression

Similarly, include the expression for Settling Time. After completion, ADE Assembler is
updated as shown in Figure – 5.57.

Figure – 5.57: ADE Assembler updated with Settling Time

The expression for DC Offset is shown in Figure – 5.58

Figure – 5.58: DC Offset

The expression for dissipated power is shown in Figure – 5.59. After typing ―2 * ‖, select
―IDC‖ from the list (―2‖ → Total Supply voltage range applied on the op-amp). Click on
―Select from design‖ and select the top pin of the ―DC Voltage Source‖ instantiated for
―VDD‖.

Figure – 5.59: Dissipated Power

To include the expression for DC Gain and Bandwidth, select the AC Analysis and mention
the expressions. The expression for Bandwidth is shown in Figure – 5.60.

The expression for DC Gain is shown in Figure – 5.61.

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After defining all the expressions, the ADE Assembler gets updated as shown in Figure – 5.62.
Figure – 5.62: Updated ADE Assembler with expressions
Go back to the ―Results‖ tab in the ―maestro‖ and click on ―Re-evaluates results using current
settings from the outputs setup table or with partial simulation data‖ option as shown in
Figure – 5.63 to re-simulate the expressions and evaluate the data.

Figure – 5.63: Evaluated Results after re-simulation

Slew Rate and Power Dissipation are seen as negative values after re-simulation. To get the
positive values, change the expression on the Outputs Setup as shown in Figure – 5.64.
Figure – 5.64: Modified expressions to get positive values
Specifications can be mentioned as shown in Figure – 5.65.

After re-evaluation, the results can be seen as shown in Figure – 5.66.

Figure – 5.66: Results after re-evaluation
GAIN MARGIN AND PHASE MARGIN:
The Schematic for measuring the Gain Margin and Phase Margin is shown in Figure – 5.67.

Figure – 5.67: Sche7matic for Gain Margin and Phase Margin measurement
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The ―iprobe‖ (available in ―analogLib‖) acts as a signal source for the stability analysis.
Create a Test Copy for the Stability Analysis as shown in Figure – 5.68.

Figure – 5.68: Test Creation for Stability Analysis

Browse ―Design → Op_amp_tran_test_gm_pm‖ as shown in Figure – 5.69.

Figure – 5.69: Design Selection

Choose ―stb‖ through ―Analyses → Click to add analysis → Choosing Analyses – ADE
Assembler‖. The parameters are shown in Figure – 5.70.

Figure – 5.70: “stb” selection and its parameters

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Click on the ―downward arrow‖ just before the test name as shown in Figure 5.71 to go back to
the ADE Explorer.

Figure – 5.71: Click on downward arrow

The ADE Explorer window pops up as shown in Figure – 5.72.

Figure – 5.72: ADE Explorer

Click on ―Simulation → Netlist and Run‖ similar to the selection in ADE L window. After the
simulation, select ―Results → Direct Plot → Main Form‖ as shown in Figure – 5.73. The
―Direct Plot Form‖ pops up as shown in Figure 5.74. Click on ―Stability Summary‖ to print the
values of Gain Margin and Phase Margin. Click on ―Plot‖ to plot the graph.

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Figure – 5.73: Results → Direct Plot → Main Form

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Figure – 5.74: Direct Plot Form and Stability Summary with Gain Margin and Phase
Margin
LAYOUT:
Follow the techniques demonstrated in Lab – 01 to open the Layout Editor, import the devices
from the Schematic, place the devices as per the requirement and complete the routing. The
completed layout can be seen as shown in Figure 5.75.

Figure – 5.75: Layout for 2 – Stage Operational Amplifier

DRC:
To check for the DRC violations, browse the ―assura_tech.lib‖ file, select ―Assura → Run DRC‖,
verify the Layout Design Source, mention a ―Run Name‖, select ―Technology → gpdk045‖ and
click on ―OK‖ as demonstrated in EXP – 01.

LVS:
To check for the LVS violations, select ―Assura → Run LVS‖, verify the Schematic Design
Source and the Layout Design Source, mention a ―Run Name‖, select ―Technology → gpdk045‖
and click on ―OK‖ as demonstrated in EXP – 01.

QRC:
To extract the Parasitics, select ―Assura → Quantus‖, select ―Technology → gpdk180‖,
―Output → Extracted View‖ from the ―Setup‖ option, select ―Extraction Type → RC‖ and
―Ref Node → VSS‖ from the ―Extraction‖ and click on ―OK‖ as demonstrated in EXP – 01. The
result can be checked from the Library Manager.
BACKANNOTATION:
Import the parasitics into the Test Schematic and re-run the simulation to check their impact
by calculating the delay elements as demonstrated in EXP – 01.

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STEPS FOR ANALOG EXPERIMENTS

General Steps:
1. Create a folder on the desktop ( Part A).

2. Right click on folder and open a terminal.

3. In terminal type virtuoso to invoke Cadence tool. This opens a Cadence Design System
(CDS) window. This is also called a Log window.

4. Create a library:

 In CDS window, execute FileNewLibrary. The NewLibrary form appears.

 In the ―New Library‖ form, type ―Analog_expts in the Name section.

 In the next ―Technology File for New library‖ form, select option Attach to an existing
technology library and click OK.

 In the ―Attach Design Library to Technology File‖ form, select gpdk180 from the
cyclic field and click OK.

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Example for Inverter:

Design an Inverter with given specifications.
a. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis
(iii) Calculate the propagation delay and power dissipated.
b. Draw the layout and verify the DRC, LVS and extract RC.
c. Back annotate the same and verify the design.
(a) Schematic Design

Step 1: Creating a Schematic Cellview

1. In CDS window, execute File – New – Cellview. It pops up a new file form.
2. Set up the New file form as follows:

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3. Click OK when done the above settings. A blank schematic window for the Inverter design
appears.

Step 2: Adding Components to schematic

1. In the Inverter schematic window, to add components execute Create —
Instance or press i.
2. Click on the Browse button. This opens up a Library browser from which you
can select components and the symbol view. You will update the Library
Name, Cell Name, and the property values given in the table on the next page
as you place each component.
3. After you complete the Add Instance form, move your cursor to the schematic
window and click left to place a component. After placing each component, to
come out press esc key.
4. This is a table of components for building the Inverter schematic.

Library name Cell Name Properties/Comments

gpdk180 pmos For M0: Model name = pmos1, W= 2u, L=180n
gpdk180 nmos For M1: Model name = nmos1, W= 2u, L=180n

Note: If you place a component with the wrong parameter values, use the Edit— Properties— Objects
( or press q) command to change the parameters. Use the Edit— Move ( or press m) command if you
place components in the wrong location.

Step 3: Adding pins to Schematic

1. Click the Pin fixed menu icon in the schematic window. You can also execute Create — Pin
or press p. The Add pin form appears.
2. Type the following in the Add pin form in the exact order leaving space between the pin names.

Pin Names Direction

vin vdd vss Input
Vout Output
3. Press esc after placing the pins.

Step 4: Adding Wires to a Schematic

1. Click the Wire (narrow) icon in the schematic window. You can also press the w key, or
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execute Create — Wire (narrow).

2. In the schematic window, click on a pin of one of your components as the first point for your
wiring. A diamond shape appears over the starting point of this wire.
3. Follow the prompts at the bottom of the design window and click left on the destination point
for your wire. A wire is routed between the source and destination points.
4. Complete the wiring as shown in figure and when done wiring press ESC key in the schematic
window to cancel wiring.

Step 5: Saving the Design

1. Click the Check and Saveicon in the schematic editor window.
2. Observe the CIW output area for any errors.

Step 6: Symbol Creation

1. In the Inverter schematic window, execute Create — Cellview— From Cellview.
2. Verify that the From View Name field is set to schematic, and the To View Name field is set
to symbol, with the Tool/Data Type set as SchematicSymbol.

3. Click OK in the Cellview From Cellview form. The Symbol Generation Form appears.
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4. Modify the Pin Specifications as follows:

5. Click OK in the Symbol Generation Options form.

6. A new window displays an automatically created Inverter symbol as shown here.

7. Editing a Symbol
 Move the cursor over the automatically generated symbol, until the green rectangle is
highlighted, click left to select it.
 Click Delete icon in the symbol window, similarly select the red rectangle and delete that.
 Execute Create – Shape – polygon, and draw a shape similar to triangle.
 After creating the triangle press ESC key.
 Execute Create – Shape – Circle to make a circle at the end of triangle.
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 You can move the pin names according to the location.

 Execute Create — Selection Box. In the Add Selection Box form, click Automatic. A
new red selection box is automatically added.
 After creating symbol, click on the save icon in the symbol editor window to save the
symbol. In the symbol editor, execute File — Close to close the symbol view window.

Step 7: Building the Inverter_Test Design

1. In the CDS window, execute File— New— Cellview.
2. Set up the New File form as follows:

3. Click OK when done. A blank schematic window for the Inverter_Test design appears.
4. In schematic window, Create — Instance or by pressing Iadd the following components
Note: To rotate components press r. None of the components should be place inside the selection box.
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Library name Cellview name Properties/Comments

Analog_expts Inverter Symbol
analogLib Vpulse v1=0, v2=1.8, delay =0 Rise time = 1ns fall
time = 1ns Pulse width =10ns period =20ns
analogLib Vdc vdd=3.3
analogLib Gnd vss

5. Click the Wire (narrow) icon or press w and wire your schematic.
6. Add output pin by pressing p and name it vout.
7. Click on the Check and Save icon to save the design.
8. The schematic should look like this.

9. Leave your Inverter_Test schematic window open for the next section

Step 8: Analog Simulation with Spectre

8.1 Starting the Simulation Environment
1. In the Inverter_Test schematic window, execute Launch – ADEL (Analog Design Environment
Launch)
2. To select spectre simulator execute setupSimulatorDirectoryhost. Set simulator as
spectre. Press ok.
3. Execute Setup - Model Libraries.
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4. To complete the Model Library Setup, move the cursor and click OK.

8.2 Choosing Analyses

1. In the Simulation window (ADE), click the Choose - Analyses icon. You can also execute
Analyses - Choose.
2. To setup for transient analysis (a). In the Analysis section select tran, (b). Set the stop time as
200n, (c). Click at the moderate or Enabled button at the bottom, and then click Apply.

3. To set up for DC Analyses:

a. In the Analyses section, select dc.
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b. In the DC Analyses section, turn on Save DC Operating Point.

c. Turn on the Component Parameter.
d. Double click the Select Component, Which takes you to the schematic window.
e. Select input signal vpulse source in the test schematic window.
f. Select ―DC Voltage‖ in the Select Component Parameter form and click OK.
f. In the analysis form type start and stop voltages as 0 to 4( must be greater than vdd
value)respectively.
g. Check the enable button and then click Apply.

4. Click OK in the Choosing Analyses Form.

8.3 Setting Design Variables

1. In the Simulation window, click the Edit Variables icon. The Editing Design Variables form
appears.
2. Click Copy From at the bottom of the form.
3. Click OK or Cancel in the Editing Design Variables window.
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8.4 Selecting Outputs for Plotting

1. Execute Outputs – To be plotted – Select on Schematic in the simulation window.
2. Follow the prompt at the bottom of the schematic window, Click on output net Vout, input net
Vin of the Inverter. Press ESC with the cursor in the schematic after selecting it.

8.5 Running the Simulation

1. Execute Simulation – Netlist and Run in the simulation window to start the Simulation or the
icon, this will create the netlist as well as run the simulation.
2. When simulation finishes, the Transient, DC plots automatically will be popped up along with
log file.
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8.6 Saving the Simulator State (Optional)

1. In the Simulation window, execute Session – Save State. The Saving State form appears.
2. Set the Save as field to state1_inv and make sure all options are selected under what to save
field.
3. Click OK in the saving state form. The Simulator state is saved.

8. 7Loading the Simulator State (Optional)

1. From the ADE window execute Session – Load State.
2. In the Loading State window, set the State name to state1_inv as shown
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3. Click OK in the Loading State window.

Step 9: Calculation of propagation delay

5. In waveform window, execute tools calculator. Calculator window pops up.
6. Delete previous analysis by clicking on clear buffer icon.
7. In function panel click on special functions delay. Click on wave radio button.
8. In delay window, click on signal1, minimize calculator window and go to waveform window
and double click on input signal. Similarly select output signal for signal2. Set threshold values
for signal 1 as 0.9 (vin/2) and for signal2 as 1.65 (vout/2).
c. For tpdf (falling edge delay)  set edge type for signal1 as rising and for signal2 as falling.
Click on apply ok. Press on execute buffer. Note down delay value.
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d. For tpdr (rising edge delay)  set edge type for signal1 as falling and for signal2 as rising.
Click on apply ok. Press on execute buffer. Note down delay value.
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Demonstration Experiment : UART

Write a verilog code for UART and carry out the following:

• To Verify the Functionality using test Bench

• Synthesize Design using constraints
• Tabulate Reports using various Constraints
• Identify Critical Path and calculate Max Operating Frequency

Aim: Write a verilog code for UART and carry out the following:
• To Verify the Functionality using test Bench
• Synthesize Design using constraints
• Tabulate Reports using various Constraints
• Identify Critical Path and calculate Max Operating Frequency
Tool Required:
• Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
• Synthesis: Genus
Design Information and Bock Diagram:
The UART is ―Universal Asynchronous Receiver/Transmitter‖, and it is an inbuilt IC within a
micro-controller but not like a communication protocol (I2C & SPI). The main function of UART
is to serial data communication. In UART, the communication between two devices can be done
in two ways namely serial data communication and parallel data communication. The transmitter
section includes three blocks namely transmit hold register, shift register and also control logic.
Likewise, the receiver section includes a receive hold register, shift register, and control logic.
These two sections are commonly provided by a baud-rate-generator. This generator is used for
generating the speed when the transmitter section & receiver section has to transmit or receive the
data.
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Source Code – Transmitter

// This code contains the UART Transmitter. This transmitter is able
// to transmit 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When transmit is complete o_Tx_done will be
// driven high for one clock cycle.
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217

module UART_TX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_TX_DV,
input [7:0] i_TX_Byte,
output o_TX_Active,
output reg o_TX_Serial,
output o_TX_Done
);
parameter IDLE = 3'b000;
parameter TX_START_BIT = 3'b001;
parameter TX_DATA_BITS = 3'b010;
parameter TX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;
reg [2:0] r_SM_Main = 0;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0;
reg [7:0] r_TX_Data = 0;
reg r_TX_Done = 0;
reg r_TX_Active = 0;
always @(posedge i_Clock)
begin
case (r_SM_Main)
IDLE :
begin
o_TX_Serial <= 1'b1; // Drive Line High for Idle
r_TX_Done <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (i_TX_DV == 1'b1)
begin
r_TX_Active <= 1'b1;
r_TX_Data <= i_TX_Byte;
r_SM_Main <= TX_START_BIT;
end
else
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r_SM_Main <= IDLE;

end // case: IDLE
// Send out Start Bit. Start bit = 0
TX_START_BIT :
begin
o_TX_Serial <= 1'b0;

// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish

if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= TX_DATA_BITS;
end
end // case: TX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish
TX_DATA_BITS :
begin
o_TX_Serial <= r_TX_Data[r_Bit_Index];
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
// Check if we have sent out all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= TX_STOP_BIT;
end
end
end // case: TX_DATA_BITS
// Send out Stop bit. Stop bit = 1
TX_STOP_BIT :
begin
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o_TX_Serial <= 1'b1;

// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_STOP_BIT;
end
else
begin
r_TX_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
r_TX_Active <= 1'b0;
end
end // case: TX_STOP_BIT
// Stay here 1 clock
CLEANUP :
begin
r_TX_Done <= 1'b1;
r_SM_Main <= IDLE;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_TX_Active = r_TX_Active;
assign o_TX_Done = r_TX_Done;
endmodule
Source Code – Receiver
// This file contains the UART Receiver. This receiver is able to
// receive 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When receive is complete o_rx_dv will be
// driven high for one clock cycle.
//
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217
module UART_RX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_RX_Serial,
output o_RX_DV,
output [7:0] o_RX_Byte
);
parameter IDLE = 3'b000;
parameter RX_START_BIT = 3'b001;
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parameter RX_DATA_BITS = 3'b010;

parameter RX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;
reg [7:0] r_Clock_Count = 0;

reg [2:0] r_Bit_Index = 0; //8 bits total

reg [7:0] r_RX_Byte = 0;
reg r_RX_DV = 0;
reg [2:0] r_SM_Main = 0;
// Purpose: Control RX state machine
always @(posedge i_Clock)
begin
case (r_SM_Main)
IDLE :
begin
r_RX_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (i_RX_Serial == 1'b0) // Start bit detected
r_SM_Main <= RX_START_BIT;
else
r_SM_Main <= IDLE;
end
// Check middle of start bit to make sure it's still low
RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
begin
if (i_RX_Serial == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the middle
r_SM_Main <= RX_DATA_BITS;
end
else
r_SM_Main <= IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_START_BIT;
end
end // case: RX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles to sample serial data
RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
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r_Clock_Count <= r_Clock_Count + 1;

r_SM_Main <= RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_RX_Byte[r_Bit_Index] <= i_RX_Serial;
// Check if we have received all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= RX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= RX_STOP_BIT;
end
end
end // case: RX_DATA_BITS
// Receive Stop bit. Stop bit = 1
RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_STOP_BIT;
end
else
begin
r_RX_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
end
end // case: RX_STOP_BIT
// Stay here 1 clock
CLEANUP :
begin
r_SM_Main <= IDLE;
r_RX_DV <= 1'b0;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_RX_DV = r_RX_DV;
assign o_RX_Byte = r_RX_Byte;
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endmodule // UART_RX

Test bench

// This testbench will exercise the UART RX.

// It sends out byte 0x37, and ensures the RX receives it correctly.
`timescale 1ns/10ps
`include "uart_tx.v"
`include "uart_rx.v"
module UART_TB ();
// Testbench uses a 25 MHz clock
// Want to interface to 115200 baud UART
// 25000000 / 115200 = 217 Clocks Per Bit.
parameter c_CLOCK_PERIOD_NS = 40;
parameter c_CLKS_PER_BIT = 217;
parameter c_BIT_PERIOD = 8600;
reg r_Clock = 0;
reg r_TX_DV = 0;
wire w_TX_Active, w_UART_Line;
wire w_TX_Serial;
reg [7:0] r_TX_Byte = 0;
wire [7:0] w_RX_Byte;
UART_RX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_Inst
(.i_Clock(r_Clock),
.i_RX_Serial(w_UART_Line),
.o_RX_DV(w_RX_DV),
.o_RX_Byte(w_RX_Byte)
);
UART_TX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_Inst
(.i_Clock(r_Clock),
.i_TX_DV(r_TX_DV),
.i_TX_Byte(r_TX_Byte),
.o_TX_Active(w_TX_Active),
.o_TX_Serial(w_TX_Serial),
.o_TX_Done()
);
// Keeps the UART Receive input high (default) when
// UART transmitter is not active
assign w_UART_Line = w_TX_Active ? w_TX_Serial : 1'b1;
always
#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;

// Main Testing:
initial
begin
// Tell UART to send a command (exercise TX)
@(posedge r_Clock);
VLSI Design and Testing Lab
BECL606

@(posedge r_Clock);
r_TX_DV <= 1'b1;
r_TX_Byte <= 8'h3F;
@(posedge r_Clock);
r_TX_DV <= 1'b0;
end endmodule