Sh ee: ners? ‘However, there are instructions mal—an ee ae rame. id stack Frame 5 are orthogor always points to a valid stack FA tosoyou can equally well apply t0 2°Y © en thereat 4and 15in 8B NT) oe eto progam status registers: ES In addition to the 16 data newe™ oe respectively «Fe rogram status Fegisterss ch registers (the current and saved program A available (0 ea The register file contains a0 Or on the current mode of the PrOCESSCT) a) visible to the programmer depen 0 es aD oe sis 2.2 curRRENT PROGRAM STATUS REGISTER , i tions. The cpsr is ‘The ARM core uses the cpsr to monitor and control internal ee te to 4 dedicated 32-bit register and resides in the register fite- of, generic program status register. Note thaf*the Shaded parts are reserved for future id control. insion. 7 ‘The cpsris divided into four fields, each 8 bits wide: flags, status, extensio: n and status fields are reserved for future us@y The control In current designs the extei field contains the processor mode, state, and interrupt mask bits. The flags field contains the condition flags. Some ARM processor cores have extra bits allocated. For example, the J bit, which can be found in the flags field, is only available on Jazelle-enabled processors, which executehad of He HICH the Ulipvigy ; 22 Current Program Status Register ‘23° aslae Tu Fields ;Fisgs__,__Status___ Extension Controt eet Bit 31302928 i p : 4 Conlin onal eater > we Thumb Aare = ire 2 ae eer tee anna Nos | a ‘ , 2) Slot) §) Grd 8-bit instructions. We will discuss Jazelle more in Section 2.2.3. It is highly probable that future designs will ign extra bits for the monitoring and control of new features. For a full description of the cpsr, refer to Appendix B. 2.21” PROCESSOR MODES The processor mode determines which registers are active and the access rights to the cpsr register itself. Each processor mode is either privileged or nonprivileged: A privileged mode allows full read-write access to the epsr. Conversely, a nonprivileged mode only allows read access to the control field in the cpsr butstill allows read-write access to the condition flags. There are seven processor Modes in total: six privileged modes (abort, fast interrupt request, interrupt request, supervisor, system, and wae and\one npnprivileged mode (user). é ips) oy ‘The processor enters abort mode when there sa faled atompLinaces memo Fast interrupt requestand interrupt request modes correspond to the two interruptievels available on the ARM processor. Supervisor modes. the mode that the processor is in after reset and is generally the mode that an operating system kernel operates inj System migdeisa special version of user niode that allows fall read-write access to the epsr. Undefined mode is used when the protes0r encounters ai instruction that Is Undefiniéd or not supported by the implementation. User mode is used for programs and applications. 2.2.2 BANKED REGISTERS USCA pred > used gr Ta 4 : i isters in the regi i hidden from Figure 2.4 shows all 37 registers in thé register file. Of those, 20 registers are a program at different times. These registers are called banked registers and ee aoe by the shading in the diagram. They are available only when the processors 2° P Nultipe Gyre SEo ahiChapter? _ ae Fast [2 | interrupt [75_} request Interrupt request Supervisor (eee ao wa) oe) mare 2.4 Complete ARM register set. mode; for example, abort mode has banked registers r13_abt, r14_abt and spsr_abt. Banked registers of a particular mode are denoted by an underline character post-fixed to the mode femonic or _mode, Every processor rhde except user mode can change mode by writing di to the mode bits of the cps] All processor modes except a le by writing directly to ei banked registers tha area subset of the main 16 Pt x mode have a set of associat one onto a user mode register. If you change prea /A banked register maps one-to- new mode will replace an existing register, For example, when the ini interrupt execute still access registers named 713 request mode, the instructions you feist 13 rg and rig The wer ee ares these registers are the banked pine suction referencing these registers, A pass oe a4 T14_usr are not affected Tegisters r0 to r12, Program still has no; 1 Rothe other be changed by Processor core has to be in privi @ Program that wri Privileged mode) or by ieee ay to the cpsr (the hen the core responds to 1ode, a banked register from the2.2 Current Program Status Register 25 z r0 ee 710 Interrupt TIT request ri2 mode [ #13_irg L714ira | ‘Spsr_irg Figure 2.5 Changing mode on an exception. an exception or interrupt. The following exceptions and interrupts cause a mode change: reset, interrupt request, fast interrupt request, software interrupt, data abort, prefetch abort, and undefined instruction. Exceptions and interrupts suspend the normal execution of sequential instructions and jump to a specific location. Figure 2.5 illustrates what happens when an interrupt forces a mode change. The figure shows the core changing from user mode to interrupt request mode, which happens when an. interrupt request occurs due to an external device raising an interrupt to the processor core. ‘This change causes user registers r13 and r14 to be banked. The user registers are replaced with registers r13_irq and r14_irg, respectively. Note r14_irq contains the return address and r13_irg contains the stack pointer for interrupt request mode. Figure 2.5 also shows a new register appearing in interrupt request mode: the saved program status register (spsr), which stores the previous mode's cpsr|You can see in the diagram the cpsr being copied into spsr_irg. To return back to user mode, a special return instruction is used that instructs nif to restore the original cpsr from the spst_irq and bank in the user registers r13 and r14. Note that the spsr can. only be modified and readina privileged mode. There is no spsr available in user modeestes ss 12 ARM Pro“ processor mode: privileged Mode( 40] or Funda 26. Chapte! pie hor eee <= yes 10111 Mode _ a yes 10001 Abort 4 perp ig a toon request as ‘sve yes li System eI eS fie un aa 10000 User into the spsr when a The saving of the cpsr Another important feature to note is that the eet a ory mode change is forced due to a program writing directly 1p the nly occurs when an exception or interrupt is rals Figure2.3 shows that the current ative processor bits ofthe epsr. When power is applied to the core, privileged. Starting na privileged mode is useful since fo the cpsrto setup the stacks for each of the other modes. nf ‘node occupies the five least significant it starts in supervisor mode, which is alization code can use full access Table 2.1 lists the various modes and the associated binary patterns. The last colump of the table gives the bit patterns that represent each of the processor modes in the psr. c ” STATE AND INSTRUCTION SETS i | Best ft ae detains which srction set sing executed. There ae th inaruonstARM, Thumb, and Je, The ARM instruction set is only active =a | ARM state, Similarly the Thumb instruction set is only active whe: | | the processor is in Thu ris imb state, Once i Thumb 16-bit instructions, You cannot i ‘lumb state the processor is executing purely instructions. intermingle sequential ARM, Thumb, and Jazelle Jand Tits are 0, the the proc case when power is appli Thumb state. To change ‘compares the ARM and ‘The ARM designers ssor is in ARM stat ed tothe processor. Wh version ofthe Java virtual machin, “tthe Jazell Jazelle Only supports a subset of tie oan Plus a specially modified es the =2.2 Current Program Status Register 27 Table 2.2 ARM and Thumb instruction set features. ARM (cpsr T= 0) Instruction size 32-bit Core instructions 38 cocoa execution® _ most only branch instructi pa instruction: ca prOeaens seni barrel shifter and _ separate barrel shifter Bi ALU instruction Ea status register _read-write in privileged mode _no direct ae -gister usage 15 general-purpose registers _8 general-purpose registers +pc “+7 high registers +pc @ See Section 2.2.6. we Boy dle exinder rs Jazelle instruction set featuyes. Table 2.3 Jazelle (cpsr T = 0, J = 1) (meas a : \ ; J Instructionsize 8-bit Gay 1a ER) ad Core instructions Over 60% of the Java bytecodes are implemented in hardware; ~ the rest of the codes are implemented in software. was Amen ce ‘The Jazelle instruction set is a closed instruction set and is pa geqic wail Table 2.3 gives the Jazelle aoa set featurgta,) ur exlensto conve v1 r testo! areadio ent?) aa INTERRUPT MASKS Interrupt masks are used to stop spe ‘There are two interrupt request levels available on the ie creat (IRQ) and fast interrupt request (FIQ). la ; ne f vorerrupt mask bts, and 6 (or 1 and ty ef Montrol the masking cific interrupt requests from interrupting’ the processor. processor core—interrupt ‘The cpsr has tw , h of IRQ aaa FIQ, respectively. The J bit * aks TRO when sétto binary 1, and similarly the F bit masks F1Q when st to binary i Ady Sonshhirg Sis oh o ’ (> Diabl 2 CONDITION FLAGS pe : i ions that speci iti ted by comparisons and the result of. ALU operation’ eee ee example, ifa SUBS subtract. instruction results in! eee toe ae set. This particular su! ‘act instruction Spe ly of zero, then the 7 flag in the cpst is. updates the cpst.28 Table 2.4 2 ha pots > ARM Pr chapter? cose OE ——— ak k werflow and/or saturation —~ a the res overfl uses a signed overflow uration the result ¢ renee Q oVerflow sult causes anu carry oe Vv ov iS the cer pe frequently used to indicate equality os se ult is a binary 1 : zee pit 31 of the rest / Negative a { N = ox ql Ki " tees shotinclude the DSP extensions, the eee ‘With processor aaa in an enhanced DSP ‘ote ee ia the or saturation Ds Mare ony sets cit fag: 70 Cleat GIG © cpar sense that the hat oe us the Jbit reflects the state ofthe core; fit is set, the core i rally usableandis only available on some processor cores, ware has to be licensed from both ARM Limited and irectly. Tn Jazelle-enabled processors, in Jazele state. The Jit is not gene! To take advantage of Jazelle, extra so Sun Microsystems. ; E Most ARM instructions can be executed conditionally on the value of the condition flags. Table 2.4 lists the condition flags and a short description on what causes them to be set. These flags are located in the most significant bits in the epsr. These bits are used for conditional execution. Figure 2.6 shows a typical value for the cpsr with both DSP extensions and Jazelle. In this book we use a notation that presents the cpsr data in a more human readable form. When a bit is a binary 1 we use a capital letter; when a bit is a binary 0, we use a lowercase letter. For the condition flags a capital letter shows thatthe flag has been set. For interrupts a pe letter shows that an interrupt is disabled, + in r Rta eae ere Flaw hae ag is the only condition flag set. The rest bits are set. The IRQ interrupts are a oes ae eee abled, and FIQ interrupts are disabled. Finally, you2.3 Pipeline 29 Table 2.5 Condition mnemonics. Mnemonic ane 2 Condition flags fd equal Zz a pti not equal . cats carry set/unsigned higher or same C cs carry clear/unsigned lower c ui minus/negative N ee para or zero n overflow ie no overflow 4 Hi unsigned higher 2c : unsigned lower or same Zorc signed greater than or equal NVorny fd signed less than Nyor nV el signed greater than N2Vor nzv signed less than or equal Zor Nvor nV AL always (unconditional) ignored Joo! can see from the figure the processor is in supervisor (SVC) mode since the model 4:0} is equal to binary 10011. 2.2.6 CONDITIONAL EXECUTION —_—_— me Conditional execution controls whether or not the core will execute an instruction. Most instructions have a condition attribute that determines if the core will execute it based on the setting of the condition flags. Prior to ‘execution, the processor compares the condition attribute with the condition flags in the cpsr. If they match, then the instruction is executed; otherwise the instruction is ignored. ’ ‘The condition attribute is postfixed to the Instruction mnemonic, which is encoded into the instruction. Table 2.5 lists the conditional execution code mnemonics. When a condition mnemonic is not present, the default behavior is to set it to always (AL) execute. 2.3 -PI PELINE A pipeline is the mechanism a RISC processor uses to execute instructions. Usinga pipeline speeds up execution by fetching the next instruction while other instructions ar¢ be decoded and executed. One way to view the pipeline is to think of it as an automo ile assembly line, with each stage carrying out a particular task to ‘manufacture the vehicle.pen at essor Fundamentals 30. Chapter 2 ARM Prot (a=) Figure 2.7 ARM7 Three-st ge pipeline. jigure2.7 4 = 4 shows a three-stage pipeline ion from memory: fe Ferchloads an instruction fre a struction to be exec \d writes the result back to a register. = Decode identifies the ‘e _ Execute processes the instruction an‘ sample It shows a sequence of three ipeli imple cigure 2.8 illustrates the pipeline using a simp : : ee fee a tended, and executed by the processor. Each instruction takes jecycle the pipeline is filled. ) a single cycle to complete after the pip a ects ee instruct Jaced into the pi The three instructions are pI pine core fetches the ADD instruction from memo! a U8 instruction and decodes the ADD instruction. In the third cycle, both the SUB and ‘ADD instructions are moved along the pipeline. The ADD instruction is executed, the SUB instruction is decoded, and the CMP instruction is fetched. This procedure is called filling the pipeline” The pipeline allows the core to execute an instruction every cycl&: = “GS the pipeline length increases, the amount of work done at each stage is reduced, which allows the processor to attain a higher operating frequency. This in. turn increases Bel aeeeig ane vem later, also ae ee it takes more cycles to fill the ieee becca ean instruction, (The increased pipeline length also means y between certain stages. You can write code to reduce this dependency by using instruction scheduli i i i i Scare ‘uling (for more information on instruction schedulingigure 2.9 gure 2.10 2 i PIPELINE EXECUTING CHARACTERISTICS z) 7: So oad joy (Tisch) bess) ffs) nemo) 2.3 Pipeline 31 gto dds \ ARMB five-stage pipeline. Fok Oy art Feld netacks Je talute fee Mero yyw ARM six-stage pipeline. ox \we polod ‘The pipeline design for each ARM family differs, For example, The ARM9 core increases the pipeline length to five stages, as shown in Figure 2.9. The ARM9 adds a memory and writeback stage, which allows the ARM9 to process on average 1.1 Dhrystone MIPS per MHz—an increase in instruction throughput by around 13% compared with an ARM7. ‘The maximum core frequency attainable using an ARM9 is also higher. ‘The ARM10 increases the pipeline length still further by adding a sixth stage, as shown in Figure 2.10. The ARMIO can process on average 1.3 Dhrystone MIPS per MHz, about 34% more throughput than an ARM7 processor core, but again at a higher latency cost. Even though the ARM9 and ARM1O pipelines are different, they still use the same pipeline executing characteristics as an ARM7. Code written for the ARM7 will execute on an ARM9 or ARM10. PSK ‘The ARM pipeline has not processed an instruction until it passes completely through the execute stage. For example, an ARM7 pipeline (with three stages) has executed an instruction only when the fourth instruction is fetched. nae Figure 2.11 shows an instruction sequence on an ARM7 pipeline. fre : instruction ig used to enable IRQ interrupt, which only occurs once the WSR instruction completes the execute stage te edd-it clears the I bit in the cpsr to enable the IRQ inter” rupts. Once the ADD instruction enters the execute stage ofthe pipeline, IRQ interrupts are enabled. Figure 2.12 illust stage, the pe always poil ot ate the pc always points to the address o e instru e I ue The important when the pe is used for calculating a relative 0 rates the use of the pipeline and the program counter pc In ibe a instruction plus 8 bytes. In other wor’s, nts to the address of the instruction Pp eo tion being executed plus two ti r fl ffset and is ans ls sdamental Furs geess0r 12 ARM PP eee 32. Chaptet __ | Fetch | | cycle 3 SUB. | cyte . Figure2.11 ARM instruction sequenc 0x8000 LOR pc, (pc. #0] 0x8008 NOP + 0x8008 DCD jumpAddress Time Decode | Execute Fetch oco_}+-{]_nor_}++{]i7uoR pe+8 (0x8000 + 8) Figure 2,12 Example: pc = address + 8. architectural characteristic across all the pipelines. Note when the processor is in Thumb state the pcis the instruction address plus 4. There are three other characteristics of the Pipeline worth mentioning. First, the exe- cation of a branch instruction or branching by the direct modification of the pe causes the ARM core to flush its pipeline. Second, ARM10 uses branch prediction, which reduces the effect ipeline fl : predicting Possible branches and loading the new branch eae ae ees Fe Third, an instruction in the execute stage will been raised. Other instructions in the pipeline will be aband ats 5 start filling the pipeline from the appropriate entry in the ene a complete even though an interrupt has i