ee a snudamentals 34 Chapter? ARM processor Fi di E A est buts reserved forhardware FIQs are not masked in sKe epsr, a Fastinte requiring (; E EXTENSIONS (2.5 coR ered in this section aFe) standard purer st a chatwae eens e gge Oe ations. Each sa ARM cor Ty ie exbny mS ee gppcations Each ARM ely nd are designed to provide fons available ground the core: cache and tightly has different extensi ‘There are three coupled memory; wraps hardware extel ions ‘ARM soavory managements and ee coprocessor interface: UpLED MEMORY 2.5.1 CACHE AND TIGHTLY CO! between main memory and te sore: Ttallows for The cache isa block of fast memory place amore efcient fetches from some memory tYPSS, With a cache the processor core can run for the majority of the time without having to wait for data from slow external memory. the internal to the processor. Most ARM-based embedded systems use @ single-level cac Ofcourse, many small embedded systems do not require the performance gains that a cache brings. Ml kes two forms of cache. The first is found attached to the Von Neumann-style ae , combines both data and instruction into a single unified cache, as shown in igure 2.13, For simplicity, we have called the glue logic that connect the m to the AMBA bus logic and control. ‘ se com Figure 2.13 Asim iplified Von Neumann archit. lecture with2.5 Core Extensions 35 Logic and control : Data }{ Instruction) PD} 7 TCM TCM D+! On-chip AMBA bus Figure 2.14 A simplified Harvard architecture with TCMs. ep .2 ae By contrast, the second form, attached to the Harvard-style cores, has separate caches, for data and instructior ae A cache provides an overall increase in performance but at the expense of predictable execution. But for real-time systems it is paramount that code execution is deterministic— the time taken for loading and storing instructions or data must be predictable. This is achieved using a form of memory called tightly coupled memory (TCM). TCM is fast SRAM located close to the core and guarantees the clock cycles required to fetch instructions or data —critical for real-time algorithms requiring deterministic behavior. TCMs appear as memory in the address map and can be accessed as fast memory. An €xample of a processor with TCMs is shown in Figure 2.14. | By combining both technologies, ARM processors can have both improved performance and predictable real-time responsg. Figure 2.15 shows an example core with a combination of caches and TCMs. MEMORY MANAGEMENT Embedded systems often use multiple memory devices. It is usually necessary o have @ method to help organize these devices and protect the system from applications tring to make inappropriate accesses to hardware. This is achieved with the assistance of memory management hardware. pe ee "ARM cores have three different types of memorymanagementhardware—n0 oT providing no protection, a memory protection unit (MPU) providing limited yrotection, and a memory management unit (MMU) providing. full protection: = Nonprotected memory s fixed and provides very litle flexibility. Its normally wed S small, simple embedded systems that require no protection from rogue appli iFigure se p+ Ey: On-chip AMBA bus s and TCMs. 2.15 A simplified Harvard architecture with caches and Je system that uses a limited number of memory regions. ‘These ih set of special coprocessor registers, and each region is ns. This type of memory management is used but don’t have a complex memory map. = MPUs employ a sim} regions are controll: defined with specific access permission for systems that require memory protection The MPU is explained in Chapter 13. MMUs are the most comprehensive memory management hardware available on the ARM. The MMU uses a set of translation tables to provide fine-grained control over memory. These tables are stored in main memory and provide a virtual-to-physical address map as well as access permissions. MMUs are designed for more sophisti- cated platform operating systems that support multitasking, The MMU is explained in Chapter 14. OPROCESSORS ARM processor. A coprocessor extends Processing ! by extending the instructin role ee isters. More than one coprocessor can be ded wo he AO core via the lid re coprocessor interface. The coprocessor can be accessed that provide a load-store a ae i soup of dal coprocessor 15: The TCMs,2.6 Architecture Revisions 37 be added to the standard ARM meee: instruction set to process vector floating-point (VEP These new instructi. ee aa poses Processed in the decode stage of the ARM pipeline. If the , sor instruction, then it offers it to th 3 P fers it to the relevant coprocessor. ut if the coprocessor is not present or doesn’t recognize the instruction, ther the ARM takes an undefined instruction exception, which allows you to emulate the behavior of the » whi mulate E Evel ).6 ARCHITECTURE REVISIONS Every ARM processor implementation executes a specific instruction set architecture (ISA), although an ISA revision may have more than one processor implementation. The ISA has evolved to keep up with the demands of the embedded market. This evolution has been carefully managed by ARM, so that code written to execute on an earlier architecture revision will also execute on a later revision of the architecture. ee seotution of the architecture, we must introduce the ARM. Se