Implementing MIPS

 We're ready to look at an implementation of the MIPS instruction set

 Simplified to contain only
 arithmetic-logic instructions: add, sub, and, or, slt
 memory-reference instructions: lw, sw
 control-flow instructions: beq, j

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op rs rt rd shamt funct R-Format

6 bits 5 bits 5 bits 16 bits

op rs rt offset I-Format
6 bits 26 bits

op address J-Format
Overview: Processor Implementation
Styles
 Single Cycle
 perform each instruction in 1 clock cycle
 clock cycle must be long enough for slowest instruction; therefore,
 disadvantage: only as fast as slowest instruction
 Multi-Cycle
 break fetch/execute cycle into multiple steps
 perform 1 step in each clock cycle
 advantage: each instruction uses only as many cycles as it needs
 Pipelined
 execute each instruction in multiple steps
 perform 1 step / instruction in each clock cycle
 process multiple instructions in parallel – assembly line
Functional Elements
 Two types of functional elements in the hardware:
 elements that operate on data (called combinational elements)
 elements that contain data (called state or sequential elements)
State Elements on the Datapath:
Register File
 Registers are implemented with arrays of D-flipflops
Clock

5 bits R ead reg ister

nu m ber 1 R ead 32 bits
data 1
5 bits R ead reg ister
nu m ber 2
Register file
5 bits W rite
re giste r
R ead 32 bits
W rite data 2
32 bits
da ta W rite

Control signal

Register file with two read ports and

one write port
State Elements on the Datapath:
Register File
 Port implementation:
Clock
Clock

Write

Read register C
number 1 0
Register 0
Register 0 1 D
Register 1 M n-to-1 C
Register number
u Read data 1 decoder Register 1
Register n – 1 x D
n– 1
Register n n
Read register
number 2
C
Register n – 1
M D
u Read data 2 C
x Register n
Register data D

Read ports are implemented Write port is implemented using

with a pair of multiplexors – 5 a decoder – 5-to-32 decoder for
bit multiplexors for 32 registers 32 registers. Clock is relevant to
write as register state may change
only at clock edge
Single-cycle Implementation of MIPS
 Our first implementation of MIPS will use a single long clock
cycle for every instruction
 Every instruction begins on one up (or, down) clock edge
and ends on the next up (or, down) clock edge
 This approach is not practical as it is much slower than a
multicycle implementation where different instruction
classes can take different numbers of cycles
 in a single-cycle implementation every instruction must take
the same amount of time as the slowest instruction
 in a multicycle implementation this problem is avoided by
allowing quicker instructions to use fewer cycles
 Even though the single-cycle approach is not practical it is
simple and useful to understand first

 Note : we shall implement jump at the very end

 MIPS Datapath II: Single-Cycle

Separate adder as ALU operations and PC

increment occur in the same clock cycle
Add

Read Registers
ALU operation
register 1 3 MemWrite
PC Read
Read Read MemtoReg
address
register 2 data 1 ALUSrc Zero
Instruction ALU ALU
Write Read Address Read
register data 2 M result data
u M
Instruction Write x u
memory Data x
data memory
Write
RegWrite data
16 Sign 32 MemRead
extend
Separate instruction memory
as instruction and data read
occur in the same clock cycle
Adding instruction fetch
 MIPS Datapath III: Single-Cycle

PCSrc New multiplexor

M
Add u
x
4 Add ALU
result
Shift
left 2 Extra adder needed as both
adders operate in each cycle
Registers
Read 3 ALU operation
MemWrite
Read register 1 ALUSrc
PC Read
address Read data 1 MemtoReg
register 2 Zero
Instruction ALU ALU
Write Read Address Read
register M result data
data 2 u M
Instruction u
memory Write x Data x
data memory
Write
RegWrite data
16 32
Sign
extend MemRead
Instruction address is either
PC+4 or branch target address

Adding branch capability and another multiplexor

Important note: in a single-cycle implementation data cannot be stored
during an instruction – it only moves through combinational logic