Vol 55, No 4—November 2021

I2C Communication Protocol:

Understanding I2C Primer,
PMBus, and SMBus
Mary Grace Legaspi, Firmware Engineer, and
Eric Peňa, Firmware Engineering Manager

Abstract Aside from the most commonly used I2C Primer, there are two additional
I2C, or Inter-Integrated Circuit, is a commonly used serial communication variations of I2C that focus on the usage for system and power applications.
protocol in establishing communication between devices, especially for two These are called System Management Bus (SMBus) and Power Management
or more different circuits. I2C Primer is the most commonly used I2C. This Bus (PMBus).
article will provide the basic features and standards for I2C Primer, primarily By definition, Inter-Integrated Circuit (I2C)—also known as Inter IC—is a hardware
to address proper usage during communication implementation. From the communication protocol that uses synchronous communication with a multi-
fundamentals of I2C, we’ll walk through the availability of its variant subsets, main, multi-node, and serial communication bus. Synchronous communication
System Management Bus (SMBus) and Power Management Bus (PMBus), and means two (or more) devices exchanging data share a common clock line. I2C
their differences. Each of the three has dedicated functions intended to is widely used for connecting lower speed peripheral ICs to processors and
address different customer requirements. microcontrollers. The I2C bus was designed by Philips to allow easy communica-
tion between components that reside on the same circuit board.
Why Is It Important?
I2C provides benefits to the designer in establishing simple, 2-way, flexible
I2C Primer
communication between numerous nodes in a system. I2C reduces complexity Interface
by using just two bidirectional wires for transmitting and receiving information. Connections are minimized by using a serial data (SDA) line, a serial clock (SCL)
It also allows designers to configure communication between multiple main- line, and a common ground to carry all communications.
node system ICs. I2C also benefits developers in managing the system and
Main Node
power, which gives them the advantage to create a high quality product inside
the best possible timeline.
SDA SDA
“Communication works for those who work at it.”
—John Powell
Communication protocol plays a big role in organizing communication between SCL SCL

devices. It is designed in different ways based on system requirements, and these Figure 1. Integrated circuits directly communicate with each other.
protocols have specific, agreed-upon rules to achieve successful communication.
There are two wires in each I2C device:
You’ve probably used I2C if you’ve ever built systems with LED displays, sensors,
or even accelerometer modules, to name a few. I2C supports the feature of X The SDA is the line for the main device and node to send and receive data.
connecting multiple nodes to a single main device and multiple main devices X The SCL is the line that carries the clock signal. The SCL is always generated
to multiple nodes. This feature is helpful if you want to maximize having one by the I2C main. The specification requires minimum periods for the low and
microcontroller logging data to a single memory card or displaying text to a high phases of the clock signal.
single LCD.
The I2C bus uses only two bidirectional lines: SDA and SCL for each device for
simple inter-IC communication.

VISIT ANALOG.COM
 VDD Reserved I2C Node Address
Rp Rp
There are 16 reserved I2C addresses. These addresses correspond to one of two
SCL patterns: 0000 XXX or 1111 XXX. Table 2 shows I2C addresses reserved for special
purposes.
SDA

Table 2. I2C Reserved Addresses

Main Node Node Node
I2C Node Address R/W Bit Description
Figure 2. An I2C pull-up resistor connection.
0000 000 0 General call address
The most important hardware parts are pull-up resistors, which are used by the 0000 000 1 Start byte
SDA and SCL lines. I2C compatible devices connect to the bus with open collector 0000 001 X CBUS address
or open drain pins, which pull the line low. When there is no transmission of
0000 010 X Reserved for different bus format
data, the I2C bus lines idle in a high state; the lines are passively pulled high.
0000 011 X Reserved for future purposes
Transmission occurs by toggling the lines, by pulling low and releasing high. Bits
are clocked on falling clock edges. 0000 1XX X High speed-mode main code
1111 1XX X Reserved for future purposes
Open drain outputs require a pull-up resistor (Rp in Figure 2) in order to properly
1111 0XX X 10-bit node address
output high. The pull-up resistor is connected between the output pin and the
output voltage (VDD in Figure 2) that is desired for a high state.
How Does I2C Work?
Four thousand seven hundred ohms (4700 Ω) is the most used value of pull-up I2C data is transferred in messages, which are broken up into frames of data.
resistors with typical values of VCC and VDD (5 V). The read and write protocol contains the address frame with the binary address
For reference, shielded 2 AWG twisted pair cables have capacitance in the range of the node and another data frame that contains the data being transmitted,
of 100 pF/m to 240 pF/m. So, the maximum bus length of an I2C link is about start and stop conditions, repeated start bits, read/write bits, and acknowledge/
1 meter at 100 kBaud, or 10 meters at 10 kBaud. Unshielded cable typically has much not acknowledge bits between each data frame.
less capacitance but should only be used within an otherwise shielded enclosure.
Timing Specification Table
Table 1 summarizes the key characteristics of I2C. The I2C timing table is also important as it allows engineers to design ICs that are
compatible with the bus requirement. Each data rate has its own timing specifi-
Table 1. I2C Summary
cation to which the main and node must adhere for correct data transfer.
Features Specs
Table 3 shows the symbols and parameters available on a timing specification table.
Wires 2
Standard mode = 100 kbps Table 3. Sample I2C Timing Specification Table
Fast mode = 400 kbps
Maximum Speed Symbol Parameter Units
High speed mode = 3.4 Mbps
Ultrafast mode = 5 Mbps fSCL SCL clock frequency kHz
Synchronous or Asynchronous? Synchronous tHD(STA) Hold time (repeated) start condition µs
Serial or Parallel? Serial tLOW Low period of the SCL pin µs
Maximum Number of Mains Unlimited tHIGH High period of the SCL pin µs
Maximum Number of Nodes 1008 tSU(STA) Set-up time for a repeated start condition µs

Theoretically, the maximum number of nodes is 2 or 2 for addressing mode;

7 10 tHD(DAT) Data hold time µs
however, 16 addresses are reserved for special purposes. tSU(DAT) Data set-up time ns
tr Rise time for SDA signals ns
I2C is synchronous, so the output of bits is synchronized to the sampling of bits
tf Fall time for SDA signals ns
by a clock signal shared between the main and the node. The clock signal is
always controlled by the main. tSU(STO) Set-up time for stop condition µs

Figure 3. An I2C message.

2 I 2C COMMUNICATION PROTOCOL: UNDERSTANDING I2C PRIMER, PMBUS, AND SMBUS

I2C Transmission Sub-Protocols I2C doesn’t have node select lines like SPI, so it needs another way to let the
node know that data is being sent to it, and not another node. It does this by
Transmission over the bus is either a read or write operation. The reading and
addressing. The address frame is always the first frame after the start bit in
writing protocols build upon a series of sub-protocols such as start and stop
a new message.
conditions, repeated start bits, address bytes, data transfer bits, and acknowl-
edge/not acknowledge bits. The main sends the address of the node it wants to communicate with to every
node connected to it. Each node then compares the address sent from the main
Start Condition to its own address. If the address matches, it sends a low voltage ACK bit back to
As the name suggests, a start condition always occurs at the start of a transmis- the main. If the address doesn’t match, the node does nothing, and the SDA line
sion and is initiated by the main device. This is done to wake the idling node remains high.
devices on the bus. The SDA line switches from a high voltage level to a low
voltage level before the SCL line switches from high to low. See Figure 4.
Read/Write Bit
The address frame includes a single bit at the end that informs the node whether
Repeated Start Condition
the main wants to write data to it or receive data from it. If the main wants to
Without issuing a stop condition, a start condition can be repeated during send data to the node, the read/write bit is at a low voltage level. If the main is
a transmission. This is a special case, called the repeated start, and is used requesting data from the node, the bit is at a high voltage level. See Figure 7.
for changing data transmission direction, repeating transmission attempts,
synchronizing several ICs, or even controlling serial memory. See Figure 5.
ACK/NACK Bit
Each frame in a message is followed by an acknowledge/not acknowledge bit.
Address Frame
If an address frame or data frame was successfully received, an ACK bit is
The address frame contains a 7-bit or 10-bit sequence, depending on the returned to the sender from the receiving device.
availability (refer to the data sheet). See Figure 6.
Legend: For the following figures, the white box represents the node while the
blue box is for the main. See Figure 8.

tf
70%
SDA
70%
30%

tSU(STA) tHD(STA)
30%

70%
SCL

30%

Figure 4. Start condition.

Figure 5. Repeated start condition.

Figure 6. Address frame.

Figure 7. Read/write bit.

Figure 8. Acknowledge/not acknowledge bit.

VISIT ANALOG.COM 3
Data Frame Step 2
After the main detects the ACK bit from the node, the first data frame is ready to The main sends each node the 7-bit or 10-bit address of the node it wants to
be sent. The data frame is always 8 bits long and sent with the most significant communicate with, along with the write bit.
bit first. Each data frame is immediately followed by an ACK/NACK bit to verify For example, a 7-bit address is 0x2D. Adding a write bit equivalent to 0, it will be 0x5A.
that the frame has been received successfully. The ACK bit must be received by
either the main or the node (depending on who is sending the data) before the Step 3
next data frame can be sent. See Figure 9. Each node compares the address sent from the main to its own address. If the
address matches, the node returns an ACK bit by pulling the SDA line low for one
Stop Condition bit. If the address from the main does not match the node’s own address, the
After all the data frames have been sent, the main can send a stop condition to node leaves the SDA line high.
the node to halt the transmission. The stop condition is a voltage transition from
low to high on the SDA line after a low-to-high transition on the SCL line, with the ACK is possible by bringing the SDA line low during the ninth pulse of the SCL and
SCL line remaining high. floating high for NACK.

The SDA line switches from a low voltage level to a high voltage level after the Step 4
SCL line switches from low to high. See Figure 10. The main sends or receives the data frame.

Steps of I2C Transmission: Write Step 5

For an example of I2C transmission of a write single location, see Figure 11. After each data frame has been transferred, the receiving device returns another
ACK bit to the sender to acknowledge successful receipt of the frame.
Step 1
Step 6
The main sends the start condition to every connected node by switching the
To stop the data transmission, the main sends a stop condition to the node by
SDA line from a high voltage level to a low voltage level before switching the SCL
switching SCL high before switching SDA high.
line from high to low.

70% 70%

30% 30%
tSU(DAT) tSU(DAT)

70%
70% 70%
30%
30% 30%

Figure 9. Data frame.

70% tr
SDA
30%

tSU(STO)
70%

70%
SCL 30%

30%

Figure 10. Stop condition.

P
SDA
MSB Acknowledgement Acknowledgement Sr
Signal from Node Signal from Receiver
Byte Complete,
Interrupt Within Node
Clock Line Held Low While
Interrupts Are Serviced

SCL S Sr
or 1 2 7 8 9 1 2 3–8 9 or
Sr P
ACK ACK
Start or Repeated Stop or Repeated
Start Condition Start Condition

Figure 11. Data sheet example for I2C transmission of write single location.

4 I 2C COMMUNICATION PROTOCOL: UNDERSTANDING I2C PRIMER, PMBUS, AND SMBUS

Figure 12. Data sheet example for I2C transmission of read single location.

Steps of I2C Data Transmission: Read Single Main with Multiple Nodes
Step 1 Because I2C uses addressing, multiple nodes can be controlled from a single
main. With a 7-bit address, 128 (27) unique addresses are available. Using 10-bit
The main sends the start condition to every connected node by switching the
addresses is uncommon but provides 1024 (210) unique addresses. To connect
SDA line from a high voltage level to a low voltage level before switching the SCL
multiple nodes to a single main, wire them with 4.7 kΩ pull-up resistors connect-
line from high to low.
ing the SDA and SCL lines to VCC.
Step 2
The main sends each node the 7-bit or 10-bit address of the node it wants to
Multiple Mains with Multiple Nodes
communicate with, along with the write bit. Multiple main devices can be connected to a single node or multiple nodes. The
problem with multiple main devices in the same system comes when two mains
For example, a 7-bit address is 0x2D. Adding a write bit equivalent to 0, it will try to send or receive data at the same time over the SDA line.
be 0x5A.
To solve this problem, each main needs to detect if the SDA line is low or high
Step 3 before transmitting a message.
Each node compares the address sent from the main to its own address. If the If the SDA line is low, this means that another main has control of the bus, and
address matches, the node returns an ACK bit by pulling the SDA line low for one the main should wait to send the message. If the SDA line is high, then it’s safe
bit. If the address from the main does not match the node’s own address, the to transmit the message. To connect multiple mains to multiple nodes, use the
node leaves the SDA line high. diagram shown in Figure 13, with 4.7 kΩ pull-up resistors connecting the SDA and
Step 4 SCL lines to VCC.

After the initial start, addressing, and acknowledge, since the main already Main Node

knows its node and the address to point to, some devices have a repeated start
condition to clean the transaction. SDA SDA

Note: For reading purposes only!

Step 5 SCL SCL

The main sends each node the 7-bit or 10-bit address of the node it wants to Main Node
communicate with, along with the read bit.
For example, a 7-bit address is 0x2D. Adding a read bit equivalent to 1, it will SDA SDA

be 0x5B.

Step 6 SCL SCL

Each node compares the address sent from the main to its own address. If the
Main Node
address matches, the node returns an ACK bit by pulling the SDA line low for one
bit. If the address from the main does not match the node’s own address, the
SDA SDA
node leaves the SDA line high.

Step 7
SCL SCL
After the ACK bit, the main receives the data frame from the node.

Step 8 VCC VCC

After each data frame has been transferred, the main returns another ACK bit to Figure 13. Multiple mains with multiple nodes connected.
the sender to acknowledge successful receipt of the frame, or the main returns
a NACK if the read request is already done. Arbitration
Several I2C multi-main devices can be connected to the same I2C bus and oper-
Step 9 ate concurrently. By constantly monitoring the SDA and SCL for start and stop
To stop the data transmission, the main sends a stop condition to the node by conditions, they can determine whether the bus is currently idle or not. If the
switching SCL high before switching SDA high. bus is busy, the main device delays pending I2C transfers until a stop condition
indicates that the bus is free again.

VISIT ANALOG.COM 5
However, it may happen that two main devices start a transfer at the same Which I2C Node Devices Need Clock Stretching?
time. During the transfer, the mains constantly monitor the SDA and SCL. If one
Whether or not clock stretching is needed depends on the functions of the node
of them detects that SDA is low when it should be high, it assumes that another
device. Here are two examples:
main is active and immediately stops its transfer. This process is called arbitra-
tion. Both mains generate a start bit and proceed with their transmissions. X A processing device, such as a microprocessor or a microcontroller, may
need additional time to process an interrupt, receive and manage data, and
If the mains happen to choose the same logic levels, nothing happens.
perform the appropriate function(s).
As soon as the mains attempt to impose different logic levels, the main driving X A simpler device, such as an EEPROM, does not process data internally, so it
the signal low is proclaimed the winner; the loser detects the logic mismatch
does not need clock stretching to perform any of its functions.
and abandons its transmission.
Take a moment to appreciate the simplicity and efficacy of this arrangement: I2C Data Sheet Sample Overview
There are different approaches in terms of creating a data sheet depending on
X The winner continues its transmission without interruption—no corrupted
different companies and manufacturers. As a starter, Figure 13 shows a sample
data, no driver contention, no need to restart the transaction.
data sheet and basic I2C details including registers and electronic specifications.
X Theoretically the loser could monitor the node address during the arbitration
process and make a proper response if it happens to be the addressed node.
X If the competing mains are both requesting data from the same node, the
arbitration process does not unnecessarily interrupt either transaction—no
mismatch will be detected, and the node will output its data to the bus such
that multiple mains can receive it.

Clock Stretching
This is also referred to as clock synchronization.
Note: The I2C specification does not specify any timeout conditions for clock
stretching—that is, any device can hold down SCL if it likes.
In I2C communication protocol, the clock speed and signals are always gener-
ated by the main device. The signal generated by the I2C main device provides
synchronization between the main and node connection.
There are instances where a node or subnode is not fully working and needs to
slow down prior to receiving the generated clock from the main. This is accom-
plished through a mechanism known as clock stretching.
During the clock stretching period, in order to reduce the bus speed, the node is
allowed to hold down the clock. While on the main side, it is necessary that, after Figure 15. Microcontroller memory map.
its high state, the clock signal must be read back. Then it must wait until the line
has reached the high state. Table 4 shows the most used I2C registers. Names and descriptions may vary
depending on the data sheet, but the functionality and usage is common.
Bandwidth
Table 4. I2C Register Description
While clock stretching is a common practice, there is an effect on the bandwidth
side. In using clock stretching, the total bandwidth among the shared bus might Name Description
be significantly decreased. Bus performance must still be reliable and fast even I2C_ADDR1 Main address byte 1
using this technique. It is necessary to cover the estimated effects of using clock
I2C_ADDR2 Main address byte 2
stretching, especially on I2C buses shared by multiple devices.
I2C_BYT Start byte
I2C_ID Node address device ID
I2C_MCTL Main control
I2C_MRX Main receive data
I2C_SCTL Node control
I2C_SRX Node receive
Figure 14. Microcontroller data sheet. I2C_STAT Main and node FIFO status

Clock stretching allows an I2C node device to force the main device into a wait
state. A node device may perform clock stretching when it needs more time to
manage data—for example, to store received data or prepare to transmit another
byte of data. This typically occurs after the node device has received and
acknowledged a byte of data.

6 I2C COMMUNICATION PROTOCOL: UNDERSTANDING I2C PRIMER, PMBUS, AND SMBUS

The creation of I2C may vary depending on usage. Table 5 shows a sample of VDD = 5 V VBUS = 3 V

basic I2C driver API requirements.

SMBus SMBus
RP RP
Table 5. I2C Driver Development Device Device

SMBCLK
Main Node
SMBDAT
Initialization
Tx Handler Tx Handler Figure 16. SMBus topology.

Rx Handler Rx Handler
SMBus Pull-Up Circuitry
Event Interrupt
VBUS VBUS VDD
Error Interrupt
OR IP IP SMBus
RP RP
SMBus Device

SMBus is known to be used in applications that require critical monitoring of SMBCLK

parameters. It is most commonly used in computer motherboards and embedded SMBDAT

system applications. It has additional monitoring specifications for temperature, Exponential Signal Rise Linear Signal Rise

supply voltage, fan monitor, and/or control integrated chips. Figure 17. SMBus pull-up circuitry.

The SMBus is a 2-wire bus that is similar to the I C bus that was developed by
2
SMBus Address
Philips in the 1980s. The two main signals are the clock, or SMBCLK, and data, SMBus addresses are 7 binary bits long and are conventionally expressed as
or SMBDAT. The I2C primer and SMBus are compatible with each other, but there 4 bits followed by 3 bits followed by the letter b—for example, 0001 110b. These
are notable differences such as: addresses occupy the high 7 bits of an 8-bit field on the bus. The low bit of this
X The SMBus logic level thresholds are fixed and not proportional to a device’s field, however, has another semantic meaning that is not part of an SMBus address.
supply voltage. This allows devices with different supply voltages to operate
on the same primer. For example, one SMBus might have devices powered
from 1.8 V, 3.3 V, and 5 V.
X They both operate on the same speed up to 100 kHz, but the I2C primer has Figure 18. Node address.
400 kHz and 2 MHz versions. A 7-bit destination address is sent from the main to one or more devices (such
X The SMBus provides for a minimum clock speed and limits the amount the as with the general call address) on the bus.
clock may be stretched in one transaction. A violation of the timeout limits
Note the start and stop conditions are transitions, not bits, and are shown with-
causes all SMBus devices to reset their I/O logic to allow the bus to restart.
out a bit count number above the symbol. When shown in a transaction diagram,
This enhances the robustness of the bus.
the repeated start is also a transition, not a bit, and is shown without a bit count
X The timeout for both is also different. The I2C primer has no timeout while above the symbol.
the SMBus has a timeout—consider 35 ms for a 10 kHz minimum clock speed.
X Packet error checking (PEC) was originally defined for SMBus. A packet error
code byte is added at the end of each transaction.
X Some of the remaining differences involve transfer types, alert line, suspend Figure 19. An SMBus message.
line, and power down or up. SMBus Timing Measurements
It is an explicit requirement that an SMBus device must acknowledge (ACK) its
Table 6. SMBus Parameters
own address every time it is received, regardless of what else the device may be
doing. This assures that a main device can accurately determine what devices Symbol Parameters Units
are active on the bus. fSMB SMBus operating frequency kHz

All SMBus transactions are carried out through one of the specified SMBus protocols. tBUF Bus free time between stop and start condition µs
THD-STA Hold time after (repeated) start condition µs
The SMBus includes an optional signal, SMBALERT#, that node devices can use to
TSU-STA Repeated start condition set-up time µs
quickly notify the main or system host that it has information for the main, such
as reporting a fault condition. tSU(STO) Stop condition set-up time µs
tHD(DAT) Data hold time ns
tSU(DAT) Data set-up time ns
tTIMEOUT Detect clock low timeout ms
tLOW Clock low period µs
tHIGH Clock high period µs

VISIT ANALOG.COM 7
PMBus: Power Management Redefined Pull-Ups
In addition to SMBus comes a variant, the PMBus, which is an open standard Only weak pull-up resistors shall be on the SCL or SDA lines inside the power
power management protocol. This flexible and highly versatile standard allows supply. The main pull-up resistors are provided by the system and may be con-
for communication between devices based on both analog and digital technolo- nected to 3.3 V or 5 V. For the system design, the main pull-ups shall be located
gies, and provides true interoperability, which will reduce design complexity and external to the power supply and derive their power from the standby rail.
shorten time to market for power system designers.
Data Speed
PMBus is used in digital management of power supplies with power control and The PMBus device in the power supply shall operate at the full 100 kbps SMBus
management components. It has commands and structures to support the require-
speed and avoid using clock stretching as much as possible, as it can slow down
ment for power management. This means both I2C primer and PMBus are compatible
the bus.
and interoperable on the electrical requirements and command semantics.
One of the essential parameters in power management is monitoring of overvolt- Summary
age level, and PMBus provides a command for setting and reading it. By adding Table 8 provides a general view and summary in terms of specifications:
to the available features of I2C primer and SMBus, PMBus acts as a protocol layer signaling, timing, and electrical among I2C Primer, SMBus (both for high and low
on top of the existing standards, especially the SMBus. power), and PMBus.
The I2C specification only describes the physical layer, timing, and flow control
How Are I2C Primer, SMBus, and PMBus Related?
of a 2-wire bus. The I2C specification does not describe the format of messages
(like the SMBus protocols) and does not describe the content of the messages. Originally developed to facilitate battery management systems, SMBus uses I2C
hardware but adds second-level software, which ultimately allows devices to be
The PMBus specification is a complete power management protocol. It includes hot swapped without restarting the system. PMBus extends SMBus by defining
how to get the bits and bytes from one device to another (that is, transport); it a set of device commands specifically designed to manage power converters,
also describes a command language that gives meaning to those bits and bytes. exposing device attributes such as measured voltage, current, temperature,
and more. In general, I2C primer, SMBus, and PMBus devices can share a bus
Addressing
without any major issues.
For redundant systems there are up to three signals to set the address location
of the power supply once it is installed in the system: Address2, Address1, and I2C, SMB, PMB Advantages
Address0. For non-redundant systems, the power supply device address location X Only uses two wires
should be B0h. X With ACK/NACK bit
Hardware X Well-known protocol
The device in the power supply shall be compatible with SMBus 2.0 high power
X Supports multiple main devices and multiple nodes
specifications for I2C VDD-based power and drive (for VDD = 3.3 V). This bus shall X Hardware is less complicated than UART
operate at 3.3 V. X Widely used method

Power Sourcing Disadvantages

The circuits inside the power supply shall derive their power from the standby X Slower data transfer rate than SPI
output. For redundant power supplies, the device(s) shall be powered from the sys- X Size of the data frame is limited to 8 bits
tem side of the OR’ing device. The PMBus device shall be on whenever AC power is X More complicated hardware needed to implement than SPI
applied to the power supply or a parallel redundant power supply in the system.
tR tF
tLOW
SMBCLK
VIH(MIN) + 0.15 V

VIL(MAX) – 0.15 V

tHD(STA) tHD(DAT) tSU(DAT) tSU(STA) tSU(STO)

tHIGH
SMBDAT
VIH(MIN) + 0.15 V

VIL(MAX) – 0.15 V

tBUF
P S S P

Figure 20. SMBus timing measurements.

Table 7. PMBus Addressing

Main Addressing Used for Most Server Power Additional Addresses If Three Addressing Pins
Addresses Used
Supplies with Two Addressing Pins Are Provided on the Power Supplies
System Addressing
0/0/0 0/0/1 0/1/1 0/1/1 1/0/0 1/0/1 1/1/0 1/1/1
Address2/Address1/Address0
PMBus Device Read Addresses B0h/B1h B2h/B3h B4h/B5h B6h/B7h B8h/B9h BAh/BBh BCh/BDh BEh/BFh

8 I2C COMMUNICATION PROTOCOL: UNDERSTANDING I2C PRIMER, PMBUS, AND SMBUS

Use Cases References
X Sensor reading “Advantages and Limitations of I2C Communication.” Total Phase, August 2016.
X Sensor writing Afzal, Sal. “I2C Primer: What Is I2C? (Part 1).” Analog Devices, Inc.
X EEPROM, temperature sensor, touch screen, proximity
Afzal, Sal. “I2C Timing: Definition and Specification Guide (Part 2).”
X Transmitting and controlling user directed actions Analog Devices, Inc.
X Communicating with multiple microcontrollers
Campbell, Scott. “Basics of the I2C Communication Protocol.” Circuit Basics.
X Consumer electronics
I2C Quick Guide. Analog Devices, Inc.
X System management
X Power management “I2C—What’s That?” I2C Bus.
X Debugging
Table 8. Summary Specifications for I2C Primer, SMBus, and PMBus
Specification I2C Primer SMBus PMBus
High Power | Low Power
Signaling Packet Error Checking (Optional) — — — —
SMBALERT (Optional) — — — —
Block Size Limit — 32 bytes 32 bytes 255 bytes
Timing Data Rate: 100 kbps 100 kbps 100 kbps 100 kbps
• Standard Mode 400 kbps — — 400 kbps
• Fast Mode 1 Mbps — — —
• Fast Mode Plus 3.4 Mbps — — —
• High Speed Mode 0 Hz to 3.4 MHz 10 kHz to 100 kHz 10 kHz to 100 kHz 10 kHz to 400 kHz
Clock Speed 25 ms to 35 ms 25 ms to 35 ms 25 ms to 35 ms
Bus Timeout — 50 μs 50 μs 50 μs
Bus Main Request Delay (Min) — — — —
SCL Hold Time (Max) — 2 ms 2 ms 2 ms
Data Hold Time (Min) — 300 ns 300 ns 300 ns
Electrical Capacitance Load per Bus Segment (Max) 400 pF 400 pF — 400 pF
Rise Time (Max) 1 μs at 100 kHz, 300 ns at 400 kHz 1 μs 1 μs 1 μs at 100 kHz, 300 ns at 400 kHz
Pull-Up Current at 0.4 V (Max) 3 mA (standard and fast mode) 4 mA 350 μA 4 mA
Leakage Current per Device (Max) ±10 μA ±10 μA ±5 μA ±10 μA
VIL Input Logic Low Threshold (Max) 0.3 VDD or 1.5 V 0.8 V 0.8 V 0.8 V
VIH Input Logic High Threshold (Min) 0.7 VCC or 3 V 2.1 V 2.1 V 2.1 V
VOL Output Logic Low Threshold (Max) 0.4 V 2.4 V 0.4 V 0.4 V

About the Author

Mary Grace Legaspi is a firmware engineer and part of the Design and Layout Team working with the Consumer Software
Engineering Group at Analog Devices. She joined ADI in Cavite, Philippines in September 2018. She graduated from Tarlac State
University with a bachelor’s degree in electronics engineering. She is currently studying toward a Master of Management at the
University of the Philippines. She can be reached at [email protected].

About the Author

Eric Peňa is a firmware engineering manager and part of the Design and Layout Team working with the Industrial Platform and
Networking Group at Analog Devices. He joined ADI in Cavite, Philippines in April 2019. He graduated from Adamson University in
Manila with a bachelor’s degree in computer engineering. Eric previously worked at Technology Enabler Designer as a firmware
engineer and also as a systems engineer at Fujitsu Ten Solutions. He can be reached at [email protected].

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