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Axi TB

The document describes a testbench for an AXI interface in a hardware design, including the generation of clock signals and the instantiation of a DUT (Device Under Test). It defines various tasks for reading and writing data, as well as initializing and managing registers related to PMBus status and error handling. The test sequence simulates various conditions to validate the functionality of the AXI interface and the associated hardware components.

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praveenb123pavi
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9 views8 pages

Axi TB

The document describes a testbench for an AXI interface in a hardware design, including the generation of clock signals and the instantiation of a DUT (Device Under Test). It defines various tasks for reading and writing data, as well as initializing and managing registers related to PMBus status and error handling. The test sequence simulates various conditions to validate the functionality of the AXI interface and the associated hardware components.

Uploaded by

praveenb123pavi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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import pmbus_csr_pkg::*;

module axi_tb;

parameter AW = 32;
parameter DW = 32;

// DUT signals
logic clk;
logic rst;

logic awvalid;
logic [AW-1:0] awaddr;
logic [3:0] awlen; // Tie to 0
logic [2:0] awsize; // Tie to 2 (for 4-byte/32-bit)

logic awready;

logic wvalid;
logic [DW-1:0] wdata;
logic wready;

logic bvalid; // Not used, tie to 1


logic bready; // Tie to 1
logic [1:0] bresp; // Tie to 0

logic arvalid;
logic [AW-1:0] araddr;
logic [3:0] arlen; // Tie to 0
logic [2:0] arsize; // Tie to 2

logic arready;

logic rvalid;
logic [DW-1:0] rdata;
logic rready;

logic [31:0] hw_cmdlut_rd_addr ;


logic hw_cmdlut_rd_en ;
logic [31:0] hw_data_cmdlut ;
logic hw_data_cmdlut_val ;//logic [31:0] hw_read_data0 ;

// ⬇️ Struct variables (this is your actual question)


reg_ro_port_list in_port_list_tb;
reg_rw_port_list out_port_list_tb;

// Clock generation
always #5 clk = ~clk;

logic [31:0] data_out;

// Tie unused signals


assign awlen = 4'd0;
assign awsize = 3'd2; // 32-bit = 4 bytes
assign arlen = 4'd0;
assign arsize = 3'd2;
assign bready = 1'b1;
//assign bresp = 2'b00;
//assign bvalid = 1'b1;

//always_ff @(posedge clk or negedge rst)


// begin
// if (!rst)
// bready <= 1'b0 ;
// else if(bvalid)
// begin
// bready <= 1'b1 ;
// #10;
// bready <= 1'b0 ;
// end
// end

// DUT instantiation
axi_csr_cmdlut_intf
// #(
// .INIT_FILE("mem_init.mem")
// )
u_dut(
.clk_i(clk),
.rst_n_i(rst),
.awvalid_i(awvalid),
.awaddr_i(awaddr),
.awlen_i(awlen),
.awsize_i(awsize),
.awready_o(awready),
.wvalid_i(wvalid),
.wdata_i(wdata),
.wready_o(wready),
.bvalid_o(bvalid),
.bready_i(bready),
.bresp_o(bresp),
.arvalid_i(arvalid),
.araddr_i(araddr),
.arlen_i(arlen),
.arsize_i(arsize),
.arready_o(arready),
.rvalid_o(rvalid),
.rdata_o(rdata),
.rready_i(rready),

.in_port_list(in_port_list_tb),
.out_port_list(out_port_list_tb),
.hw_cmdlut_rd_addr (hw_cmdlut_rd_addr ),
.hw_cmdlut_rd_en (hw_cmdlut_rd_en ),

.hw_data_cmdlut (hw_data_cmdlut ),
.hw_data_cmdlut_val(hw_data_cmdlut_val)

);

// --------------------------
// WRITE TASK
task automatic axi_write(input [AW-1:0] addr, input [DW-1:0] data);
begin
@(posedge clk);
awvalid <= 1;
awaddr <= addr;
wvalid <= 1;
wdata <= data;
wait (awready)
@(posedge clk);
awvalid <= 0;
wvalid <= 0;
wdata <= 0;//data;
// Wait for ready
//wait (wready );
//@(posedge clk);
//awvalid <= 0;
//wvalid <= 0;

// Handle write response


//bready <= 1;
/*wait (bvalid);
@(posedge clk);
bready <= 1 ;
@(posedge clk);
bready <= 0 ;*/
end
endtask

// --------------------------
// READ TASK
task automatic axi_read(input [AW-1:0] addr, output [DW-1:0] data_out);
begin
@(posedge clk);
arvalid <= 1;
araddr <= addr;
//rready <= 0;

wait (arready);
@(posedge clk);
arvalid <= 0;

wait (rvalid);
@(posedge clk);
rready <= 1;
araddr <= 0 ;
@(posedge clk);
rready <= 0;
end
endtask

// --------------------------
// WRITE ONE TO CLEAR TASK
task automatic axi_w1c(input [AW-1:0] addr, input [DW-1:0] bits_to_clear);
begin
axi_write(addr, bits_to_clear);
end
endtask
always_ff @(posedge clk or negedge rst)
begin
if (!rst)
in_port_list_tb.c0_pmbus_rx_dbuf_rx_data <= 0 ;
else if (out_port_list_tb.rx_data_pop)
in_port_list_tb.c0_pmbus_rx_dbuf_rx_data <= 32'hDEADBEEF ;
end

// --------------------------
// TEST SEQUENCE
initial begin
clk <= 0;
rst <= 0;
awvalid <= 0;
wvalid <= 0;
arvalid <= 0;
rready <= 0;
awaddr <= 0;
wdata <= 0;
araddr <= 0;
hw_cmdlut_rd_addr <=0 ;
hw_cmdlut_rd_en <=0 ;
//----HW READ INPUTS --
//in_port_list_tb.hw_read_addr = 32'h0;
//in_port_list_tb.hw_read_en = 32'h0;

//---------fast interupt status register-----------

in_port_list_tb.c0_pmbus_sts0_stopf <= 1'h0;


in_port_list_tb.c0_pmbus_sts0_cmd_data_avlf <= 1'h0;
in_port_list_tb.c0_pmbus_sts0_rx_buf_of <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_tx_buf_lowf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_tx_buf_urf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_slv_busyf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_multif <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_cmd_valf <= 1'h0;
in_port_list_tb.c0_pmbus_sts0_data_avlf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_rpt_start_valf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_ext_cmd_valf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_rd_valf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_err_detf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_pg_detf <= 2'b0;
in_port_list_tb.c0_pmbus_sts0_rx_data_buf_fill_cntf <= 3'b0;
in_port_list_tb.c0_pmbus_sts0_tx_data_buf_fill_cntf <= 3'b0;
in_port_list_tb.c0_pmbus_sts0_cmdf <= 8'b0;

//---------normal interupt status register ---------


in_port_list_tb.c0_pmbus_sts1_stopn <= 1'h0;
in_port_list_tb.c0_pmbus_sts1_cmd_data_avln <= 1'h0;
in_port_list_tb.c0_pmbus_sts1_rx_buf_on <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_tx_buf_lown <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_tx_buf_urn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_slv_busyn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_multin <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_cmd_valn <= 1'h0;
in_port_list_tb.c0_pmbus_sts1_data_avln <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_rpt_start_valn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_ext_cmd_valn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_rd_valn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_err_detn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_pg_detn <= 2'b0;
in_port_list_tb.c0_pmbus_sts1_rx_data_buf_fill_cntn<= 3'b0;
in_port_list_tb.c0_pmbus_sts1_tx_data_buf_fill_cntn<= 3'b0;
in_port_list_tb.c0_pmbus_sts1_cmdn <= 8'b0;

#20;
rst = 1;

in_port_list_tb.c0_pmbus_err_sts0_pec_errf <= 1'b1;


in_port_list_tb.c0_pmbus_err_sts0_cmd_errf <= 1'b1;
in_port_list_tb.c0_pmbus_err_sts0_misc_err_encf<= 3'b11 ;
in_port_list_tb.c0_pmbus_err_sts0_to_encf <= 3'b111;
in_port_list_tb.c0_pmbus_err_sts0_araf <= 1'b0 ;

in_port_list_tb.c0_pmbus_err_sts1_pec_errn <= 1'b1;


in_port_list_tb.c0_pmbus_err_sts1_cmd_errn <= 1'b1;
in_port_list_tb.c0_pmbus_err_sts1_misc_err_encn<= 3'b11 ;
in_port_list_tb.c0_pmbus_err_sts1_to_encn <= 3'b111;
in_port_list_tb.c0_pmbus_err_sts1_aran <= 1'b0 ;

repeat(2)@(posedge clk);
in_port_list_tb.c0_pmbus_sts0_stopf <= 1'h1;
in_port_list_tb.c0_pmbus_sts0_cmd_data_avlf <= 1'h1;
in_port_list_tb.c0_pmbus_sts0_rx_buf_of <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_tx_buf_lowf <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_tx_buf_urf <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_slv_busyf <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_multif <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_cmd_valf <= 1'h1;
in_port_list_tb.c0_pmbus_sts0_data_avlf <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_rpt_start_valf <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_ext_cmd_valf <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_rd_valf <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_err_detf <= 1'b1;
in_port_list_tb.c0_pmbus_sts0_pg_detf <= 2'b1;
in_port_list_tb.c0_pmbus_sts0_rx_data_buf_fill_cntf <= 3'b11;
in_port_list_tb.c0_pmbus_sts0_tx_data_buf_fill_cntf <= 3'b111;
in_port_list_tb.c0_pmbus_sts0_cmdf <= 8'b11111111;

//---------normal interupt status register ---------


in_port_list_tb.c0_pmbus_sts1_stopn <= 1'h1;
in_port_list_tb.c0_pmbus_sts1_cmd_data_avln <= 1'h1;
in_port_list_tb.c0_pmbus_sts1_rx_buf_on <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_tx_buf_lown <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_tx_buf_urn <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_slv_busyn <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_multin <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_cmd_valn <= 1'h1;
in_port_list_tb.c0_pmbus_sts1_data_avln <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_rpt_start_valn <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_ext_cmd_valn <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_rd_valn <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_err_detn <= 1'b1;
in_port_list_tb.c0_pmbus_sts1_pg_detn <= 2'b1;
in_port_list_tb.c0_pmbus_sts1_rx_data_buf_fill_cntn <= 3'b11;
in_port_list_tb.c0_pmbus_sts1_tx_data_buf_fill_cntn <= 3'b111;
in_port_list_tb.c0_pmbus_sts1_cmdn <= 8'b11111111;

repeat(2)@(posedge clk);
in_port_list_tb.c0_pmbus_sts0_stopf <= 1'h0;
in_port_list_tb.c0_pmbus_sts0_cmd_data_avlf <= 1'h0;
in_port_list_tb.c0_pmbus_sts0_rx_buf_of <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_tx_buf_lowf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_tx_buf_urf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_slv_busyf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_multif <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_cmd_valf <= 1'h0;
in_port_list_tb.c0_pmbus_sts0_data_avlf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_rpt_start_valf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_ext_cmd_valf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_rd_valf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_err_detf <= 1'b0;
in_port_list_tb.c0_pmbus_sts0_pg_detf <= 2'b0;
in_port_list_tb.c0_pmbus_sts0_rx_data_buf_fill_cntf <= 3'b0;
in_port_list_tb.c0_pmbus_sts0_tx_data_buf_fill_cntf <= 3'b0;
in_port_list_tb.c0_pmbus_sts0_cmdf <= 8'b0;

//---------normal interupt status register ---------


in_port_list_tb.c0_pmbus_sts1_stopn <= 1'h0;
in_port_list_tb.c0_pmbus_sts1_cmd_data_avln <= 1'h0;
in_port_list_tb.c0_pmbus_sts1_rx_buf_on <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_tx_buf_lown <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_tx_buf_urn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_slv_busyn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_multin <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_cmd_valn <= 1'h0;
in_port_list_tb.c0_pmbus_sts1_data_avln <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_rpt_start_valn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_ext_cmd_valn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_rd_valn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_err_detn <= 1'b0;
in_port_list_tb.c0_pmbus_sts1_pg_detn <= 2'b0;
in_port_list_tb.c0_pmbus_sts1_rx_data_buf_fill_cntn <= 3'b0;
in_port_list_tb.c0_pmbus_sts1_tx_data_buf_fill_cntn <= 3'b0;
in_port_list_tb.c0_pmbus_sts1_cmdn <= 8'b0;

repeat(5)@(posedge clk);

axi_write(32'h00000000, 32'hFFFFDEAD);
repeat(3)@(posedge clk);

// Read back
axi_read(32'h00000000, data_out);
$display("Read Data = 0x%08X", data_out);

repeat(3)@(posedge clk);

//@(posedge clk);
axi_write(32'h00000004, 32'hDEADFFFF);
repeat(3)@(posedge clk);
// Read back
axi_read(32'h00000004, data_out);
$display("Read Data = 0x%08X", data_out);

repeat(3)@(posedge clk);
// Normal write
axi_write(32'h00000008, 32'hFFFFFFFF);
repeat(3)@(posedge clk);

// Read back
axi_read(32'h00000008, data_out);
$display("Read Data = 0x%08X", data_out);
repeat(3)@(posedge clk);

axi_write(32'h00000012, 32'hABCDABCD);
repeat(3)@(posedge clk);

// Read back
axi_read(32'h00000012, data_out);
$display("Read Data = 0x%08X", data_out);

repeat(3)@(posedge clk);

repeat(5)@(posedge clk);
// W1C operation
axi_w1c(32'h00000040, 32'hFFFFFFFF);//STATUS REGISTER FAST

repeat(4)@(posedge clk);
axi_w1c(32'h00000048, 32'hFFFFFFFF);//STATUS REGISTER NORMAL

repeat(5)@(posedge clk);
axi_read(32'h00000040, data_out);//READING FAST STATUS INFORMATION AFTER WRITE
ONE TO CLEAR

repeat(4)@(posedge clk);
axi_read(32'h00000048, data_out);//READING NORMAL STATUS INFORMATION AFTER
WRITE ONE TO CLEAR

@(posedge clk);
axi_write(32'h00000080, 32'hABCDABCD);
repeat(3)@(posedge clk);
axi_read(32'h00000064, data_out);
@(posedge clk);
axi_write(32'h00000804, 32'hABCDABCD);
repeat(3)@(posedge clk);
axi_read(32'h000000804, data_out);
@(posedge clk);
axi_write(32'h00000C00, 32'hDEADBEEF);
repeat(3)@(posedge clk);
axi_read(32'h000000C00, data_out);

repeat(3)@(posedge clk);
hw_cmdlut_rd_addr <=32'h00000804 ;
hw_cmdlut_rd_en <= 1'b1 ;
@(posedge clk);
hw_cmdlut_rd_addr <=32'h0 ;
hw_cmdlut_rd_en <= 1'b0 ;
repeat(3)@(posedge clk);
hw_cmdlut_rd_addr <=32'h00000C00 ;
hw_cmdlut_rd_en <= 1'b1 ;
@(posedge clk);
hw_cmdlut_rd_addr <=32'h0 ;
hw_cmdlut_rd_en <= 1'b0 ;

#2000 $finish;
end

endmodule

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