EC3058D-VLSI Circuits and Systems

Winter Semester-2025-26
Problem Sheet-2

1. Ans:

i 1 2 3 4 5 6 7 8
Ri (Ω) 0.25 0.25 0.5 100 0.25 0.75 0.75 1000 For an RC tree, the Elmore delay at a
Ci (pF ) 250 750 250 250 1000 250 500 250
node is given by:

n
X
τ= Rpath to i · Ci
i=1

For the path from node A to B:

τAB = R1 C1 + R1 C2 + R1 C4 + (R1 + R3 )C3 + (R1 + R3 )C5

+ (R1 + R3 )C7 + (R1 + R3 + R6 )C6 + (R1 + R3 + R6 + R8 )C8
τAB (ps) = 62.5 + 187.5 + 62.5 + 187.5 + 750 + 750 + 375 + 250375
τAB = 252.3745ns

2. Ans:

(a) Stick diagram

(b) Logic function

′
Y = [(A + B + C) · D]
(c) and (d)

1
3. Ans:

Euler Path: A → B → E → C → D
Stick Diagram:

2
4. Ans:

When x = 2.5, the pass transistor has a VGS = 2.5 and a VDS = 2.5, so it is velocity saturated.

Ix=2.5 = (115)(1.5)(0.63)(2.5 − 0.43 − 0.63/2)(1 + 0.06 · 2.5) = 219 µA

When x = 1.25, the pass transistor has VDS = 1.25 and VGS = 1.25. It is still velocity saturated, but
notice that VGS has decreased. Thus,

Ix=1.25 = (115)(1.5)(0.63)(2.5 − 0.43 − 0.63/2)(1 + 0.06 · 1.25) = 205 µA

The average Mn current is then IM navg = 211µA.

For Mr , Ix=2.5 = 0 since VDS = 0.
For x = 1.25, the PMOS device is velocity saturated, so:

Ix=1.25 = (−30)(1)(−1)(−2.5 + 0.4 + 1/2)(1 + 0.1 · 1.25) = −54 µA

The average Mr current is then IM ravg = −27µA.

Hence average discharge current Iavg = 185µA.
C∆V
t=
Iavg
50f F × 1.25V
=
185µA
= 338ps

5. Ans:
(a) Three input NOR gate with minimum number of NMOS transistors

(b)
2 2
   
VDSAT n VOL
kn (VGSn − VT n )VDSAT n − = 3kn (VGSn − VT n )VOL −
2 2
2 2
   
0.6 V
(2.5 − VOL − 0.4) × 0.6 − = 3 (2.5 − 0.4)VOL − OL
2 2
VOL = 0.16V

(c) When the output is at logic zero, VOL = 0.16V . During this time both the pull down and pull up
networks ar on. Hence there will be continuous current flow from VDD . Hence static power dissipation
will be non-zero.

3
6. Ans:

(a) The circuit is a NAND gate.

(b) When A = B = VDD , the voltage at node x is VX = VDD − VtN . This causes static power dissipation
at the inverter the pass transistor network is driving.
(c) Replace the pass transistors with transmission gates.
(d) Answer is

7. Ans:

where R is the equivalent resistance of transmission gate and C is the capacitance at each node of trans-
mission gate stack.
C = 10f F
1
R≈ = 15.87kΩ
kp (−VDD − VT p )
In order to reduce delay of the network it is decided to insert buffers after every m transmission gates.
Then overall delay is
n(m + 1) n 
tp = 0.69R C+ − 1 tbuf f
2 m
To find optimum value of m
∂tp
=0
∂m
r
2tbuf f
⇒ mopt = = 0.427
0.69RC
Hence
mopt = 1

8. Ans:

4
Given that tR = tL = 1 and tS = 1. Let tdi be th epath delay of path Pi
(a) For path P1:
td1 = tR + 2tL + tS = 1 + 2 + 1 = 4

For path P2:

td2 = tR + 3tL + tS = 1 + 3 + 1 = 5

For path P3:

td3 = tR + tL + tS = 1 + 1 + 1 = 3

For path P4:

td4 = tR + tL + tS = 1 + 1 + 1 = 3

For path P5:

td5 = tR + tL + tS = 1 + 1 + 1 = 3
Minimum clock period T is given by

Tmin = max(td1 , td2 , td3 , td4 , td5 ) = 5

(b) When clock skew δ = 4

(c) For path P1:
td1 = tR + 2tL + tS − δ = 1 + 2 + 1 − 4 = 0

For path P2:

td2 = tR + 3tL + tS − δ = 1 + 3 + 1 − 4 = 1

For path P3:

td3 = tR + tL + tS = 1 + 1 + 1 = 3

For path P4:

td4 = tR + tL + tS = 1 + 1 + 1 = 3

For path P5:

td5 = tR + tL + tS + δ = 1 + 1 + 1 + 4 = 7
Minimum clock period T is given by

Tmin = max(td1 , td2 , td3 , td4 , td5 ) = 7

(d) When clock skew δ = 4 and clock jitter tjitter = 2

5
 (e) For path P1:
td1 = tR + 2tL + tS − δ + 2tjitter = 1 + 2 + 1 − 4 + 4 = 4

For path P2:

td2 = tR + 3tL + tS − δ + 2tjitter = 1 + 3 + 1 − 4 + 4 = 5

For path P3:

td3 = tR + tL + tS + 2tjitter = 1 + 1 + 1 + 4 = 7

For path P4:

td4 = tR + tL + tS + 2tjitter = 1 + 1 + 1 + 4 = 7

For path P5:

td5 = tR + tL + tS + δ + 2tjitter = 1 + 1 + 1 + 4 + 4 = 11
Minimum clock period T is given by

Tmin = max(td1 , td2 , td3 , td4 , td5 ) = 11

9. Ans:

(a) At t = 0+ :

VG = VDD = 3.3V
Vb = VDD = 3.3V
Vs = 0V
VGS = Vg − Vs = 3.3 − 0 = 3.3V
VDS = Vb − Vs = 3.3 − 0 = 3.3V
VGS − VT = 3.3 − 1 = 2.3V

Since VDS > VGS − VT , the transistor is in saturation at t = 0+ .

At t → ∞, the source node Vs charges up close to Vb , and when Vgs = VT , the transistor enters the
cutoff region.
(b) Cs will get charged to a voltage Vs where

VS = Vw − VT
= 3.3 − 1 = 2.3V

Then charge across CS will be

QS = CS VS
= 50f F × 2.3V
= 11.5pC