Alliance:
FPGA Express
&
Design Manager
Y.T.Chang/2001.02/XLNX_HDL Ali-1
How FPGA Express Fits in the Design CIC
Flow
Y.T.Chang/2001.02/XLNX_HDL Ali-2
FPGA Express Design Flow CIC
Tool Bar Online Help Tip Bar Find information about specific tasks
and synthesis and optimization
Create HDL Design procedures
Create VHDL and Verilog HDL Design
Set Up Project source files
Create Project directory. Identify and analyze
source files
Select Target Architecture
& Synthesize Logic Select the target architecture and device.
Synthesize gate-level logic from HDL
source code
Enter Constraints
Set design constraints and optimization
control such as system clock rate and port
and path delays
Optimize Design
Optimize logic for FPGA/CPLD device.
Create FPGA netlist.
Analyze Timing
Analyze delay information for timing
analysis and debugging.
Generate Reports
Generate synthesis and optimization reports.
Y.T.Chang/2001.02/XLNX_HDL Ali-3
Different Design Environments CIC
HDL HDL & Schematic
Design Schematic
Design Design
Functional Functional
Simulation Simulation
Place
HDL XNF & Route
FPGA
Express
Synthesis
Timing
Simulation
Optimization
Design Constraints Timing Analysis Program
FPGA Device
FPGA Netlist
Y.T.Chang/2001.02/XLNX_HDL Ali-4
FPGA Express CIC
! How to Start FPGA Express
! 開始 > 程式集 > Xilinx Foundation Series > Accessories >
Foundation Express
Y.T.Chang/2001.02/XLNX_HDL Ali-5
Online Help System CIC
! Tools Bar and Tip Bar
Tool Bar
Tip Bar
! Context-Sensitive Help
! Shift - F1
! question mark button
! Detailed Online Help
Y.T.Chang/2001.02/XLNX_HDL Ali-6
Process for designing an FPGA with CIC
FPGA Express I
! 1. Create the design
! Write the HDL source code for the design. FPGA Express process the
HDL code to produce an optimized netlist that is ready for FPGA
place and route tools.
! 2. (Optional) Verify the design functionally.
! Use an HDL simulator.
! 3. Set up the design and analyze the source files.
! File > New Project...
Y.T.Chang/2001.02/XLNX_HDL Ali-7
Process for designing an FPGA with CIC
FPGA Express II
! 4. Synthesize a design
! select the top level design name from the drop down list.
! Then choose the target FPGA device to synthesize a new
design implementation
! If you want to enter design constraints, uncheck “Skip
constraint entry”
Y.T.Chang/2001.02/XLNX_HDL Ali-8
Process for designing an FPGA with CIC
FPGA Express III
! 5. Enter design constraints
! Select the design implementation, click the right mouse
button, and select Edit Constraints to open the design
constraint and optimization-control tables.
Y.T.Chang/2001.02/XLNX_HDL Ali-9
Process for designing an FPGA with CIC
FPGA Express IV
! 6. Optimize the design logic
! 1. Click the design implementation in the Chips window to
select it. Its name is displayed in the top-level design field of
the tool bar.
! 2. Click the right mouse button and select Optimize Chip, or
click Optimize Button in the tool bar.
Y.T.Chang/2001.02/XLNX_HDL Ali-10
Process for designing an FPGA with CIC
FPGA Express V
! 7. Analyze timing
! To view the results of optimization:
! 1. Open an optimized implementation by clicking the right
mouse button and selecting View Results.
! 2. Check the Clocks constraint table to see the maximum clock
frequencies FPGA Express calculated for each of the clocks in
the design. Clock frequency violations appear in red.
Y.T.Chang/2001.02/XLNX_HDL Ali-11
Process for designing an FPGA with CIC
FPGA Express VI
! 8. View schematics
! View an RTL or Generic Design
! 1. In the Chips window, right-click on the un-optimized implementation.
! 2. From the popup menu, select View Schematic.
! View a Gate-level (or Mapped / Optimized) Design
! 1. In the Chips window, right-click on the optimized implementation.
! 2. From the popup menu, select View Schematic.
Y.T.Chang/2001.02/XLNX_HDL Ali-12
Process for designing an FPGA with CIC
FPGA Express VII
! 9. Generate optimized FPGA netlists and reports.
! You can generate XNF or EDIF files formatted for immediate place-
and-route by the FPGA vendor systems, or
! You can generate VHDL or Verilog files for functional simulation.
! Generating Netlist Files(*.xnf) & Simulation Files
! 1. Select the optimized design implementation.
! 2. Click Export Netlist button in the tool bar, or
click the right mouse button and select Export
Netlist.
Y.T.Chang/2001.02/XLNX_HDL Ali-13
Process for designing an FPGA with
CIC
FPGA Express VIII
! Generating a Report
! 1. Select the project, library, design, or chip icon in the project
window.
! 2. Click the right mouse button and select the report menu, or
click
on the tool bar. Specify the name and choose the location for
the report.
! 10. (Optional) In FPGA Express, analyze timing
information to verify acceptable circuit performance.
Y.T.Chang/2001.02/XLNX_HDL Ali-14
Design Manager
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What is Design Manager CIC
! Suite for implementing a design into a Xilinx FPGA or CPLD.
! Provides access to all the tools you need to read a design file
from a design entry tool and implement it in a Xilinx device.
! Design Manager Capabilities
! Organize and manage your design implementation data, including
projects, design versions, and implementation revisions
! Target different devices
! Manage data for and access to the following tools in the Xilinx
Design Manager system. The tools differ for FPGA and CPLD
families.
! Flow Engine (FPGA and CPLD)
! Timing Analyzer (FPGA and CPLD)
! Floorplanner (Spartan and XC4000 families only)
! PROM File Formatter (FPGA)
! Hardware Debugger (FPGA)
! EPIC Design Editor (FPGA)
! JTAG Programmer (CPLD)
! Generate timing simulation data for external simulation tools
! Generate configuration data & Program a device
Y.T.Chang/2001.02/XLNX_HDL Ali-16
Xilinx Design Manager CIC
! How to Start FPGA Express
! 開始 > 程式集 > Xilinx Foundation Series > Accessories >
Design Manager
Flow Engine
Timing Analyzer
Floorplaner
PROM File Formatter
Hardware Debugger
FPGA Editor
JTAG Programmer
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Process for designing an FPGA with CIC
Design Manager I
! 1. Set up the Project
! File > New Project...
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Process for designing an FPGA with CIC
Design Manager II
! 2. Implementation
! Design > Implement…
! Set up Options...
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Process for designing an FPGA with CIC
Design Manager III
! Run Flow Engine
Y.T.Chang/2001.02/XLNX_HDL Ali-20
Process for designing an FPGA with CIC
Design Manager IV
! 3. (Optional) Simulate the design with back-
annotated timing delays.
! 4. Program the FPGA device.
! Hardware Debugger
Y.T.Chang/2001.02/XLNX_HDL Ali-21
