Chapter 2

In-Depth Tutorial — HDL-Based Design

This chapter guides you through a typical HDL-based design
procedure using a design of a runner’s stopwatch called Watch. The
design example used in this tutorial demonstrates many device
features, software features and design flow practices which you can
apply to your own design. This design targets an XC4000E device;
however, all of the principles and flows taught are applicable to any
Xilinx device family, unless otherwise noted.
For an example of how to design with CPLDs, see the online help by
selecting Help → Foundation Help Contents from the Project
Manager. Under Tutorials, select CPLD Design Flows.
In the first part of the tutorial, you use the Foundation design entry
tools to complete the design. The design is composed of HDL
elements and a LogiBLOX macro; you will synthesize the design
using the Express tools.
Then, you will functionally simulate the design using the Foundation
Logic Simulator. In the third part, you will implement the design
using the Xilinx Implementation Tools. Finally, you will verify the
design through timing simulation, and then download the bitstream
to a Xilinx FPGA Demonstration Board. The simulation,
implementation, and bitstream generation are described in
subsequent chapters.
This chapter includes the following sections.
• “Getting Started”
• “Design Description”
• “The Project Manager”
• “Design Entry”
• “Synthesizing the Design”

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• “The Express Constraints Editor (Foundation Express Only)”

• “Using the Express Constraints Editor (Foundation Express
Only)”
• “Viewing Synthesis Results (Foundation Express Only)”

Getting Started
The following subsections describe the basic requirements for
running the tutorial.

Nomenclature
In this tutorial, the following terms are used:
• “XC4000 family” includes XC4000E, XC4000L, XC4000EX,
XC4000XL, and XC4000XV devices.
• “Right-click” means click the right mouse button. Unless
specified, all other mouse operations are performed with the left
mouse button.
Throughout this tutorial, file names, project names, and directory
names (paths) are specified in lower case, and the design is referred
to as Watch.

Required Software
The Xilinx Foundation Series package, Version 1.5, is required to
perform this tutorial. The design requires that you have installed the
XC4000E libraries and device files and are licensed for Foundation
Express or Base Express. These options are selected by default in the
install program for either Express configuration.
Note: A Foundation Express license is required to access the Express
Constraints GUI.

Installing the Tutorial

This tutorial assumes that the software is installed in the default
location c:\fndtn\active. If you have installed the software in a
different location, substitute your installation path for
c:\fndtn\active.

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The tutorial projects are optionally installed (as sample projects) in

the c:\fndtn\active\projects directory when you install the
Foundation Series software. If you have installed the software, but
are not sure whether the tutorial projects were installed, check for
directories named c:\fndtn\active\projects\wtut*. These directories
contain the various tutorial files.

Tutorial Project Directories and Files

During the software installation, the WTUT_VHD and WTUT_VER
directories are created within c:\fndtn\active\projects, and the
tutorial files are copied into these directories. These directories
contain incomplete versions of the design, done in VHDL and
Verilog, respectively. You will complete the design in the tutorial.
However, solutions projects with all completed input and output files
are also provided. The following table lists the associated project.
Table 2-1 Tutorial Project Directories

Directory Description
WTUT_VHD Incomplete Watch Tutorial - VHDL
WTUT_VER Incomplete Watch Tutorial - Verilog
WATCHVHD Solution for Watch - VHDL
WATCHVER Solution for Watch - Verilog

The WATCHVHD and WATCHVER solution projects contain the

design files for the completed tutorials, including HDL files and the
bitstream file.To conserve disk space, some intermediate files are not
provided. Do not overwrite any files in the solutions directories.
The WTUT_VHD and WTUT_VER projects contain incomplete
copies of the tutorial design. You will create the remaining files when
you perform the tutorial. As described in a later step, you have the
option to copy the Watch project to another area and perform the
tutorial in this new area if desired.

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VHDL or Verilog?
This tutorial has been prepared for both VHDL and Verilog designs.
This document applies to both designs simultaneously, noting
differences where applicable. You will need to decide which HDL
language you would like to work through the tutorial when you open
the project.

Starting the Project Manager

1. Double click the Foundation Series Project Manager icon on your
desktop or select Programs → Xilinx Foundation Series →
Xilinx Foundation Project Manager from the Start menu.

2. A Getting Started dialog box opens. You can select a recently

opened project from this box. If have not opened this tutorial
project before now, click the More Projects... button.

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Figure 2-1 Getting Started Dialog Box

3. In the Directories list, browse to c:\fndtn\active\projects. In the
Projects list, open WTUT_VHD or WTUT_VER by double
clicking.

Copying the Tutorial Files

You can either work within the project directory as it has been
installed from the CD, or you can make a copy to work on. To make a
working copy of the tutorial files, begin with an opened project and
perform the following steps.
Note: Whenever copying projects in Foundation, it is important to
use the “Copy Project” feature in the Project Manager to ensure that
the project’s directory structure is kept intact.
1. Select File → Copy Project.
2. Under the Destination section, type “wtch_hdl” in the Name
field.
3. Click OK.
4. Select File → Open Project.
5. Scroll down in the project list and select the wtch_hdl project
name. Click Open.

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6. The wtch_hdl project will contain two UCF files. If this is the
case, select wtut_vhd.ucf or wtut_ver.ucf. Select Document →
Remove or press Del to remove the file (wtut_ver.ucf or
wtut_vhd.ucf). Click Yes to confirm the removal of the file.
This does not delete the file from the disk. It merely removes it
from the project so that it is not used during compilation. The file
still exists in the project directory on the disk. If you mistakenly
remove a file from a project, select Document → Add to add it
back.

Design Description
The design used in this tutorial is a hierarchical, HDL-based design,
meaning that the top-level design file is an HDL file that references
several other lower-level macros. The lower-level macros are either
HDL modules or LogiBLOX modules.
The design begins as an unfinished design. Throughout the tutorial,
you complete the design by generating some of the modules from
scratch and by completing some others from existing files. When the
design is complete, you simulate it to verify the design’s
functionality.
Watch is a simple runner’s stopwatch. There are two external inputs,
and three external output buses in the completed design. The system
clock is an internally generated signal produced by the OSC4, the
internal oscillator in the XC4000 devices. The following list summa-
rizes the input lines and output buses.
Inputs:
• STRTSTOP —Starts and stops the stopwatch. This is an active
low signal which acts like the start/stop button on a runner’s
stopwatch.
• RESET—Resets the stopwatch to 00.0 after it has been stopped.
Outputs:
• TENSOUT[6:0]—7-bit bus which represents the Ten’s digit of the
stopwatch value. This bus is in 7-segment display format
viewable on the 7-segment LED display on the Xilinx
demonstration board.

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• ONESOUT[6:0]—Similar to TENSOUT bus above, but represents

the One’s digit of the stopwatch value.
• TENTHSOUT[9:0]—10-bit bus which represents the Tenths’ digit
of the stopwatch value. This bus is one-hot encoded.
• GSRT—Active low global reset signal connected to the STARTUP
block.
• EXT_CLK, CLK_SELECT, CLK_OUT_15HZ—Signals required
for the hardware verification chapter of this tutorial.
The completed design consists of the following functional blocks.
• OSC4
Xilinx Unified Library component which represents the XC4000
on-chip oscillator.
• STATMACH
State Machine module.
• CNT60
HDL-based module which counts from 0 to 59, decimal. This
macro has 2 4-bit outputs, which represent the ones and tens
digits of the decimal values, respectively.
• TENTHS
Logiblox 10-bit, one-hot encoded counter. This macro outputs the
tenths digit of the watch value as a 10-bit one-hot encoded value.
• HEX2LED
HDL-based macro. This macro decodes the ones and tens digit
values from hexadecimal to 7-segment display format for
viewing on the FPGA Demonstration Board.
• SMALLCNTR
A simple Counter.
• DEBUG_CKT
HDL-based macro containing the necessary logic to perform
hardware debugging and readback using the Hardware
Debugger.

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The Project Manager

The Project Manager controls all aspects of the design flow. Through
the Project Manager, you can access all of the various design entry
and design implementation tools. You can also access the files and
documents associated with your project. The Project Manager
maintains revision control over multiple design iterations.
The Project Manager is divided into three main subwindows. To the
left is the Design Hierarchy Browser which displays the elements
included in the project. To the right is a set of tabs, each one brings up
a separate functional window. The third window at the bottom of the
Project Manager is the Message Console and shows status messages,
errors, and warnings and is updated during all project actions. These
windows are discussed in more detail in the following sections.

Figure 2-2 Project Manager

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Hierarchy Browser
In the Files tab of the Hierarchy Browser, design source files and
libraries are displayed. Next to each filename is an icon which tells
you the file type (HDL file, state machine, schematic, library, text file,
for example). If a file contains lower levels of hierarchy, the icon has a
+ to the left of the name. HDL files have this + to show the entities
(VHDL) or modules (Verilog) within the file. You can expand the tree
by clicking this icon. You can open a file to edit by double clicking the
filename in the browser.
A Versions tab is also available behind the Files tab. Since this is a
new design which has not yet been implemented, the Versions tab is
empty. This tab is discussed in more detail later in the tutorial during
design implementation.

Project Manager Functional Tabs

As mentioned previously, the right-hand side of the Project Manager
contains a series of functional tabs. The functions of these tabs
follows:
• Flow—Provides access to tools you use to complete your entire
design, arranged in a flow-chart style to guide you through the
design flow. Status indicators in the upper right corner of each
phase box indicate whether the step has been completed
successfully.
• Contents—Lists the contents and date of the last modification of
the file selected in the Hierarchy Browser.
• Reports—Accesses design flow reports.
You have the option to browse through these tabs at this time, and at
any time during the tutorial to see how the tabs are updated during
the design flow process.

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Message Console Window

Errors, warnings, and informational messages are displayed in the
Message Window. Errors are displayed in red, warnings in blue, and
informational messages in black.
Information about synthesis results are displayed under the HDL
Errors, HDL Warnings, and HDL Messages tabs. Because the HDL
messages, errors and warnings are associated with a specific file or
version, you must select a synthesis version (functional structure or
optimized structure) or a specific file in the Files or Version tab to see
messages.

Design Entry
In this hierarchical design, you will examine HDL files, correct syntax
errors, create an HDL macro, and add a LogiBLOX module. This
tutorial gives you experience with creating and using each type of
design macro so that you can apply these procedures to your own
design.

Adding Source Files

You must add HDL files to the project before they can be synthesized.
Four HDL files have already been added to this project, but have not
yet been analyzed. Use Synthesis → Analyze All HDL Source
Files to update these files.
Now add the remaining HDL file to the project. Select Synthesis →
Add HDL Source Files and select SMALLCNTR.VHD or
SMALLCNTR.V from the project directory.
This file will be analyzed when it is added to the project. HDL files
that have been added to the project always have one of four status
indicators associated with the file. These indicators are:
• A red question mark means the file has been modified and needs
to be re-analyzed. Right-click the file and select Analyze.

• A red X means errors have been found. Select this file and
examine the errors under the HDL Errors tab. Errors are also
given in the HDL Editor.

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• A red exclamation point means warnings have been issued.

Select the file and examine the warnings under the HDL
Warnings tab. Many warnings can be safely ignored.

• A green check means that the file is up-to-date with no errors or

warnings.

Correcting HDL errors

The SMALLCNTR design contains a syntax error that must be
corrected. The red “x” next to the filename indicates an error was
found during analysis. The Project Manager reports errors in red and
warnings in blue in the console.
Note: To open help on Express errors or warnings, select the error or
message in the HDL Error or Warning tab, then press the F1 key.
1. Open SMALLCNTR.VHD or SMALLCNTR.V in the HDL Editor
by double clicking the file name in the Files tab of the Hierarchy
Browser.
2. Correct any errors in the HDL source file. The comments next to
the error explain this simple fix.
3. Select File → Save to save the file.
4. Re-analyze the file by selecting Synthesis → Check Syntax, in
the HDL Editor or by right-clicking the HDL file in the Project
Manager and selecting Analyze.

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Starting the HDL Editor

There are three different ways to open the HDL Editor tool.
• From the Flow tab, click the HDL icon within the Design Entry
phase button.

or,
• Double click an HDL file in the Files tab.
or,
• Right-click an HDL file in the Files tab and select Edit.
If you need to stop the tutorial at any time, save your work by
selecting File → Save from the menus.

Creating an HDL-Based Module

With Foundation, you can easily create modules from HDL code. The
HDL code is connected to your top-level HDL design through
instantiation and compiled with the rest of the design.
You will create a new HDL module. This macro serves to convert the
two 4-bit outputs of the CNT60 module into a 7-segment LED display
format.

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Using the HDL Design Wizard and HDL Editor

You enter the name and ports of the component in the HDL Wizard
and the Wizard creates a “skeleton” HDL file which you can complete
with the remainder of your code.
1. From the Flow tab in the Project Manager, click the HDL Editor
button.
2. A dialog box opens, asking if you want to create an empty HDL
file, select an existing HDL file, or use the HDL Wizard to create a
new file. Click the radio button next to Use HDL Design Wizard
and click OK.
3. Follow the instructions from the Wizard. When you are
prompted for a preferred HDL language, choose whichever one
you want, VHDL or Verilog.
4. When you are prompted for a file name, type HEX2LED.
5. The HEX2LED component has a 4-bit input port named HEX and
a 7-bit output port named LED. To enter these ports, first click the
New button in the Ports dialog box. Select Input as the direction
and type HEX in the Name field. Then, click the arrow next to the
Bus field to select 3:0, which is the width of the bus. In the Name
field, you should now see HEX[3:0], and a corresponding pin
should appear on the symbol diagram on the left.

Figure 2-3 HDL Wizard

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6. Repeat the previous step for the LED[6:0] output bus. Be sure that
the direction is set to Output.
7. Click Finish to complete the Wizard session. A “skeleton” HDL
file now displays in the HDL Editor.

Figure 2-4 Skeleton VHDL File

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Figure 2-5 Skeleton Verilog File

In the HDL Editor, the ports are already declared in the HDL file, and
some of the basic file structure is already in place. Keywords are
printed in red, comments in green, and values are gray. This color-
coding enhances readability and recognition of typographical errors.

Using the Language Assistant

You use the templates in the Language Assistant for commonly used
HDL constructs, as well as synthesis templates for commonly used
logic components such as counters, D flip-flops, multiplexers, and
global buffers. You can add your own templates to the Language
Assistant for components or constructs you use often.
1. To invoke the Language Assistant, select Tools → Language
Assistant from the HDL Editor pulldown menu.
2. The Language Assistant is divided into three sections: Language
Templates, Synthesis Templates, and User Templates. To expand
the view of any of these sections, click the + next to the topic.
Click any of the listed templates to view the template in the right
hand pane.

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3. Use the template called HEX2LED Converter located under the

Synthesis Templates heading. Locate this template and preview it
in the right hand pane by clicking the template. This template
provides source code to convert a 4-bit value to 7-segment LED
display format.

Figure 2-6 Language Assistant

4. Before adding this template to your HDL file, be sure that the
cursor in the HDL Editor is positioned below the line with the
comments “<<enter your statements here>>” for VHDL. For
Verilog, enter code after the “// Add your code here” line. When
you use the template, the code is placed wherever the cursor
currently is in the HDL Editor.
5. To add the HEX2LED Converter template code, click the Use
button in the Language Assistant while the HEX2LED Converter
template is selected. The code is automatically placed in the HDL
file.
6. Close the Language Assistant by clicking the X in the upper right
corner of the window.
7. (Verilog only) After the “//add your declarations here”
statement and before the HEX2LED converter that you just
added, add the following line of code to the HDL file to allow an
assignment.
reg LED;

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8. You now have complete and functional HDL code and can check
the syntax using Synthesis → Check Syntax.
9. After you successfully complete the syntax check, save the file by
selecting File → Save from the HDL Editor.
10. Add this HDL file to your current project by selecting Project
→ Add to Project.
11. Exit the HDL Editor.

Examining the Top-Level HDL

Open STOPWATCH.VHD or STOPWATCH.V in the HDL Editor.
This is the top level of the design and consists mainly of the top level
ports and connections to the lower hierarchical blocks. Two Xilinx
library components have been instantiated in this HDL file: OSC4
and the BUFG.
OSC4: The XC4000 devices contain an on-chip oscillator that you can
use to generate internal clock signals. To access the internal oscillator,
you must instantiate the OSC4 component. Nominal clock
frequencies of 8 MHz, 500 kHz, 16 kHz, 490 Hz, and 15 Hz are
available and are specified by corresponding output pins of the OSC4
symbol. In the Watch design, you use the 15Hz clock output of the
OSC4 component as the system clock in the design. The frequency of
these clock signals is not precise. Do not use the OSC4 when you
require a high degree of clock speed precision.
BUFG: All Xilinx devices contain a set of Global Buffers that provide
low-skew distribution of high fanout signals. The number and type of
global buffers differs depending on the Xilinx device family you want
to target. Consult the Xilinx Libraries Guide for more information
regarding the various types of global buffers available.
In the Watch design, a BUFG component drives the clock signal from
the OSC4. The signal on the output of the BUFG is the buffered clock
signal which drives all the clocks in the system. Express infers global
clock buffers, but since this clock signal is generated by the
instantiated OSC4 component, the BUFG must also be instantiated.
Consult the “Instantiated Components” appendix in the Foundation
Series User Guide for a list of components that can be instantiated.

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Creating a LogiBLOX Module

LogiBLOX is a graphical interactive design tool you use to create
high-level modules such as counters, shift registers, RAM and
multiplexers. You can customize and pre-optimize the modules to
take advantage of the inherent architectural features of the Xilinx
FPGA architectures, such as Fast Carry Logic for arithmetic functions,
and on-chip RAM for dual-port and synchronous RAM.
In this section, you create a LogiBLOX module called Tenths. Tenths
is a 10-bit one-hot encoded counter. It counts the tenths digit of the
stopwatch’s time value. The encoding is set to one-hot counter so that
the digit is easily viewed on the FPGA Demo Board when
downloaded. A series of LED lights display the Tenths digit, where
one light will be on for each count of the tenths digit.

Running the LogiBLOX Module Selector

You select the type of module you want in the GUI of the LogiBLOX
Module Selector dialog box as well as the specific features of the
module. You can invoke this GUI from either the Project Manager, the
HDL Editor, or the Schematic Editor. The operation of the tool is the
same regardless of where you invoke it.
1. If you have closed the HDL Editor, open STOPWATCH.VHD or
STOPWATCH.V.
2. From within the HDL Editor, select Synthesis → LogiBLOX.
3. The Setup window opens if this is your first call to the LogiBLOX
module generator. If the Setup window does not open, click the
Setup button. Enter the following items.
a) Under the Device Family tab, use the pulldown to select
xc4000e.
b) Under the Options tab, select VHDL Template or Verilog
Template, depending on the language you are using.
c) If you plan to simulate with an HDL simulator, select
Behavioral VHDL Netlist or Structural Verilog netlist,
depending on the HDL simulator you want to use.
4. Click OK when you have defined all of the options.

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Figure 2-7 LogiBLOX Setup for VHDL Designs

5. Fill in the LogiBLOX Module Selector with the following settings.
• Module Type: Counters
Defines the type of module.
• Module Name: Tenths
Defines the name of the module.
• Bus Width: 10
Defines the width of the data bus. You either choose from the
pulldown menu, or type in a value.
• Operation: Up
Defines how the counter will operate. This field is dependant
on the type of module you select.
• Style: Maximum Speed
Defines the type of optimization strategy for the module.
This dictates how the layout of the module is defined.
• Encoding: One Hot
Defines the register encoding for the module.

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• Async Val: 0000000001

Defines the value of the module on power-up and reset.
6. Check or uncheck the appropriate boxes on the module diagram
so that only the following pins are used.
• Async. Control
• Clock Enable
• Q_OUT
• Terminal Count

Figure 2-8 LogiBLOX Module Selector

7. Click OK. The module is created and automatically added to the
project library.

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A number of files are added to the project directory. These files

follow:
• TENTHS.NGC
This file is the netlist that is used during the Translate phase
of implementation.
• TENTHS.VHI or TENTHS.VEI
This is the instantiation template that is used to incorporate
the LogiBLOX module in your source HDL.
• TENTHS.VHD or TENTHS.V
This is the HDL file to be used only for functional simulation.
Do not attempt to synthesize this file. Also do not add this
file to the Foundation project.
• TENTHS.MOD
This file stores the configuration information for the Tenths
module.
• LOGIBLOX.INI
This file stores the LogiBLOX configuration for the project.

Instantiating the LogiBLOX Module in the HDL Code

VHDL Flow
1. If you have closed the HDL Editor, open STOPWATCH.VHD.
2. Place your cursor after the line that states:
“-- Place the LogiBLOX Component Declaration for Tenths here”
Select Edit → Insert File and choose Tenths.vhi. The VHDL
template file for the LogiBLOX instantiation is inserted.
The Component Declaration does not need to be modified.
3. Highlight the inserted code from “--Component Instantiation” to
“TERM_CNT=>);”. Select Edit → Cut.

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Figure 2-9 VHDL Component Declaration of LogiBLOX Module

4. Place the cursor after the line that states:
“--Place the LogiBLOX Component Instantiation for Tenths
here.”
Select Edit → Paste to place the instantiation here.
Change “instance_name” to “XCOUNTER”.
5. Edit this instantiated code to connect the signals in the Stopwatch
design to the ports of the LogiBLOX module. The completed code
looks like the following.

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Figure 2-10 VHDL Component Instantiation of LogiBLOX

Module
6. Save the design and close the HDL Editor.

Verilog Flow
1. If you have closed the HDL Editor, open STOPWATCH.V
2. Place your cursor after the line that states:
“-- Place the LogiBLOX Module Declaration for Tenths here”
This line is at the end of the file.
Select Edit → Insert File and choose Tenths.vei. The Verilog
template file for the LogiBLOX instantiation is inserted.
The Component Declaration does not need to be modified.
Note: Alternatively, the remaining module declaration can be placed
in a new Verilog file (name it TENTHS.V) and added to the project. Be
careful not to overwrite the Verilog simulation model, also named
TENTHS.V, if one has been created. This module declaration is
required to define the port directions of the ports of the LogiBLOX
module.

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3. Highlight the inserted code from “Tenths instance_name” to

“.TERM_CNT=());”. Select Edit → Cut.

Figure 2-11 Verilog Module Declaration of LogiBLOX Module

4. Place the cursor after the line that states:
“--Place the LogiBLOX Component Instantiation for Tenths
here.”
Select Edit → Paste to place the instantiation here.
Change “instance_name” to “XCOUNTER”.
5. Edit this code to connect the signals in the Stopwatch design to
the ports of the LogiBLOX module. The completed code is shown
in the following figure.

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Figure 2-12 Verilog Component Instantiation of LogiBLOX

Module
6. Save the design and close the HDL Editor.

Synthesizing the Design

Now that the design has been entered and analyzed, the next step is
to synthesize the design. In this step, the HDL files are translated into
gates and optimized to the target architecture.
1. Set the global synthesis options by selecting Synthesis →
Options. Set the Default Frequency to 20MHz, and check the
Export Timing Constraints box. Click OK to accept these values.
2. Click the + next to STOPWATCH.VHD (or STOPWATCH.V). This
shows the entities (or modules) within the HDL file. Some files
may have multiple entities (or modules).
3. Right click the entity named “stopwatch” and select
Synthesize.

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This step can also be done by clicking the Synthesis button under
the flow tab. Select the stopwatch entity or module by using the
pulldown in the Top Level field. Be sure that the Version Name
field has an entry.
4. Complete the Target Device fields with this information:
• Family: XC4000E
• Device: 4003EPC84
• Speed Grade: -3
5. Check the boxes labeled Edit Synthesis/Implementation
Constraints and View Estimated Performance after Optimization.
Selecting the Edit Synthesis/Implementation Constraints box
automatically opens the Express Constraints Editor after
synthesis is complete.
Selecting the View Estimated Performance after Optimization
box automatically opens the Optimized dialog box which
displays the results of the synthesis and optimization.

Figure 2-13 Synthesis/Implementation Window

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6. Click Run. Express synthesizes the design and opens the Express
Constraints Editor.
Note: The Express Constraints Editor is not available to non-
registered users or with Base Express licenses. All the functionality
covered by the Express Constraints Editor can be achieved by
component instantiation (Pullups, Pulldowns, Clock Buffers, I/O Flip
Flops), UCF file (timing constraints, pin location constraints), or MAP
options (merging flip flops into IOBs). If you are a Base Express
customer, skip to the “In-Depth Tutorial — Functional Simulation”
chapter.

The Express Constraints Editor (Foundation

Express Only)
You control optimization options and pass timing specifications to
the Place and Route software through a GUI in the Express Synthesis
software. This editor is only available with the Foundation Express
product not Base Express. All timing specifications are passed in the
netlist directly to the place and route engine and are used in the
synthesis process for timing estimation purposes only.
• Clocks
The Default Frequency set in Synthesis → Options is applied
to all clocks in the design. To change the specification of a clock,
click inside the box to the right of the clock and select Define.
Enter the clock period or give the rise and fall times.
• Paths
All types of paths that can be covered by timing specifications are
listed here, with unique specifications given for each clock in the
design. To modify these specifications, enter a new delay in the
Req. Delay column.
To create a subpath within a path, right click the source or
destination and select New Subpath. Give the subpath a new
name and delay value, then select sources and destinations by
double clicking the instances. You can also use wildcards in the
selection filters to choose a group of elements.

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• Ports
With the Ports tab, you set input and out delay requirements,
assign clock buffers, insert pullup or pulldown resistors in the I/
O, set delay properties for input registers, set slew rate, disable
the use of I/O registers, and assign pin locations. For all but the
pin locations, click in the box to use the pulldown menu. For pin
locations, type the pin number in the box.
• Modules
With the Modules tab, you to keep or eliminate hierarchy and
disable resource sharing. You can also override the default
settings for effort and area versus speed at the module level.
• Xilinx Options
The Ignore unlinked cells during GSR mapping option directs
Express to infer a global reset signal (and, therefore, insert the
STARTUP module), even if black boxes have been instantiated.
Express cannot know the reset characteristics of any logic in black
boxes, so it will not insert STARTUP unless you check this option.

Using the Express Constraints Editor (Foundation

Express Only)
Xilinx recommends that you let the automatic placement and routing
program, PAR, define the pinout of your design. Pre-assigning
locations to the pins can sometimes degrade the performance of the
place-and-route tools. However, it is usually necessary, at some point,
to lock the pinout of a design so that it can be integrated into a PCB
(printed circuit board).
Define the initial pinout by running the place-and-route tools without
pin assignments, then locking down the pin placement so that it
reflects the locations chosen by the tools. Assign locations to the pins
in the Watch design so that the design can function in a Xilinx
demonstration board. Because the design is simple and timing is not
critical, these pin assignments do not adversely affect the ability of
PAR to place-and-route the design. For HDL-based designs, these pin
assignments can be done in a User Constraints File (.UCF) or with the
Express Constraints Editor. Although .UCF files are provided for this
tutorial, you will assign the pin location constraints in the Express
Constraints Editor.

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1. In the Express Constraint Editor, click the Import Constraints

button. Select WATCHVHD.EXC or WATCHVER.EXC,
depending on the language you are using. These files are located
in the project directory.
This file has been created for you. The only difference you should
see between your initial constraints and the ones saved in the
.EXC file is the set of pin locations under the Ports tab.
You can save Constraint Editor settings for a design by selecting
File → Export Constraints. When this .EXC file is read in
for a later synthesis run, all constraints are re-established in the
GUI, as long as they can be matched to instances in the current
version.
2. Under the Paths tab, click in the box in Row 2 below the Req.
Delay header (from All Input Ports to RC-oscout). Change the
delay to 35. Under the Ports tab, the Input Delays for RESET and
STRTSTOP have changed to 35, as these represent all the Pad to
Setup delays.
You can change the values of individual Input or Output Delays
by clicking the value in the Ports tab and either editing the value
there or using the pulldown tab to select a value or define a new
one. Change the values on one of the output signals using one of
these methods.

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Foundation Series 1.5a In-Depth Tutorials

Figure 2-14 Ports Tab Display

3. Under the Paths tab, right click either RC-oscout or All
Output Ports in the sixth row and select New Subpath. The
Create/Edit Timing Subpath window opens.
Give this new subpath a name, Sub_flops_to_out, and a Delay
value, 30. On the left hand side, double click all four flip flops
that contain the name /stopwatch/sixty/lsbcount/qout*, to
determine the sources of this subpath. On the lower right hand
side, use the filter to select the destinations. Type ONE* in the
field and click the Select button. All the ports beginning with
ONESOUT will be highlighted. Click OK to see your new
subpath.
Note: Base Express users cannot access the Express Constraints
Editor. Pin location constraints must therefore be defined in a UCF
file, which Xilinx has provided. Select Implementation →
Implementation Options. Click the Browse button next to User
Constraints and select BASE.UCF.

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Figure 2-15 Editing Subpath in the Express Constraints Editor

4. Under the Ports tab, add the two final pin location in the Pad Loc
column. Scroll to the right to see this column. RESET must be
assigned to P28, and STRTSTOP must be assigned to P18. To
reassign, click the box and enter the pin number (including the
P).
Note: The remaining I/Os have pin assignments. This information is
contained in the .exc file. which you imported in Step 1.
5. Click OK to continue synthesis. Express now optimizes the
design.

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Viewing Synthesis Results (Foundation Express

Only)
With the View Estimated Performance after Optimization box
checked, the Express Constraints Editor opens after the optimization
phase of synthesis with preliminary performance results. The delay
values are based on wireload models and, therefore, must be
considered preliminary. Consult the post-route timing reports for the
most accurate delay information.
1. Under the Clocks tab, examine the estimated delay value of the
clock. Delays greater than the specification appear in red.
2. Under the Paths tab, examine the estimated delays for the paths
and subpath. Click the source or destination of a path to see the
members of the path, and click a specific path to see the
individual segments of that path.

Figure 2-16 Estimated Timing Data Under Paths Tab

3. Examine the Ports tab to see that all of the settings and delays
have been assigned and met.

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4. Under the Modules tab, you can examine the elements used to
synthesize this design. Click the box in the second row under
Area and select Details. This section summarizes all the design
elements used in the Stopwatch design that Express knows
about.
Since the Tenths module is a LogiBLOX component and has not
been synthesized by Express, it is UNLINKED and no summary
information is available.
Note: Black boxes (modules not read into the Express design
environment) are always noted as UNLINKED in the Express reports.
As long as the underlying netlist (.xnf, .ngo, .ngc or EDIF) for a black
box exists in the project directory, the Implementation tools merge the
netlist in during the Translate phase. Since the Tenths module was
built using LogiBLOX called from the project, the tenths NGC file will
be found.
5. Click OK to complete the Synthesis phase.
At this point, an XNF file exists for the Stopwatch design. See the “In-
Depth Tutorial — Functional Simulation” chapter to perform a post-
synthesis simulation of this design or refer to the “In-Depth Tutorial
— Design Implementation” chapter to place and route the design.

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