L T P C

EC 3561 VLSI LABORATORY

0 0 4 2
COURSE OBJECTIVES:
The student should be made:
 To learn Hardware Descriptive Language(Verilog/VHDL)
 To learn the fundamental principles of Digital System Desing using HDL and FPGA
 To learn the fundamental principles of VLSI circuit design in digital domain
 To learn the fundamental principles of VLSI circuit design in analog domain
 To provide hands on design experience with EDA platforms.
LIST OF EXPERIMENTS:
Part I: Digital System Design using HDL & FPGA (24 Periods)
1. Design of basic combinational and sequential (Flip-flops) circuits using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
2. Design an Adder (Min 8 Bit) using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
3. Design and implement Universal Shift Register using HDL. Simulate it using Xilinx/Altera Software

4. Design Memories using HDL. Simulate it using Xilinx/Altera Software and implement by
Xilinx/Altera FPGA
5. Design Finite State Machine (Moore/Mealy) using HDL. Simulate it using Xilinx/Altera
Software and implement by Xilinx/Altera FPGA
6. Design 3-bit synchronous up/down counter using HDL. Simulate it using Xilinx/Altera Software and
implement by Xilinx/Altera FPGA
7. Design 4-bit Asynchronous up/down counter using HDL. Simulate it using
Xilinx/Altera Software and implement by Xilinx/Altera FPGA
8. Design and simulate a CMOS Basic Gates & Flip-Flops. Generate
Manual/Automatic Layout .
9. Design and simulate a 4-bit synchronous counter using a Flip-Flops
Generate Manual/Automatic Layout
10. Design and simulate a CMOS Inverting Amplifier.

11. Design and Simulate basic Common Source, Common Gate and Common Drain Amplifiers.

12. Design and simulate simple 5 transistor differential amplifier.

 Index

Exp. Name of the Experiment Page. No.

No.
1 Design of basic combinational and
sequential (Flip-flops) circuits using
HDL. Simulate it using Xilinx/Altera
Software and implement by
Xilinx/Altera FPGA

2 Design an Adder (Min 8 Bit) using

HDL. Simulate it using
Xilinx/Altera Software and
implement by Xilinx/Altera FPGA

3 Design and implement Universal

Shift Register using HDL. Simulate it
using Xilinx/Altera Software

4 Design Memories using HDL.

Simulate it using Xilinx/Altera
Software and implement by
Xilinx/Altera FPGA

5 Design 3-bit synchronous up/down

counter using HDL. Simulate it using
Xilinx/Altera Software and implement
by Xilinx/Altera FPGA
Design 4-bit Asynchronous up/down
6 counter using HDL. Simulate it using
Xilinx/Altera Software and implement
by Xilinx/Altera FPGA

Design and simulate a CMOS

7 Basic Gates & Flip-Flops

Design and simulate a 4-bit

8 synchronous counter using a Flip-
Flops
Design and simulate a CMOS
9 Inverting Amplifier
Design and simulate basic
10 Common Source and Common
Drain Amplifier

Design and simulate simple 5

11 transistor differential amplifier.
 Exp. No:1
Basic Experiments on Digital Circuits
Date

Aim:

To Simulate and synthesis Adder and subtractor using Verilog HDL

Software tools required:

Synthesis tool: Xilinx ISE 14.1

Simulation tool: Project Navigator

a) Half Adder and Half subtractor

Procedure:

Step1: Define the specifications and initialize the design.

Step2: Write the source code in VERILOG.
Step3: Check the syntax and debug the errors
Step4: Verify the output by simulating the source code.
Step5: Write all possible combinations of input using the test bench.
Step6: Obtain the place and route report.
Half Adder:

Logic Diagram: Truth Table:

A B SUM CARRY

0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Equation:

s = a b
c=ab

Verilog Coding:
Structural:

module half_adder_s(a, b, sum, carry);

input a, b;
output sum, carry;
xor u1(sum, a, b);
and u2(carry, a, b);
endmodule

Dataflow:

module half_adder_d (a, b, sum, carry);

input a, b;
output sum, carry;

assign sum = a ^ b;
assign carry = a & b;

endmodule

Behavioral :

module half_adder_b(a, b, sum, carry);

input a, b;
output reg sum, carry;

always@(a or b)
begin

sum = a ^ b;
carry = a & b;

end
endmodule
Model Simulation output:
Test Bench for dataflow modelling:
module half_adder_dtb();

reg a;
reg b;

wire sum;
wire carry;

half_adder_d uut (a, b, sum, carry);

initial
begin

a = 0;
b = 0;

#50 a = 1; b = 1;

#50 a = 1; b = 0;

#50 a = 0; b = 1;

end

endmodule

Half Substractor:

LOGIC DIAGRAM: TRUTH TABLE:

A B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Verilog Coding:

Structural

module half_sub_s(a, b, diff, borr);

input a, b;
output diff, borr;

xor u1(diff, a, b);

not u2 (bbar, b);
and u3(borr, a, bbar);

endmodule

Dataflow

module half_sub_d(a, b, diff, borr);

input a, b;
output reg diff, borr;

assign diff = a ^ b;
assign borr = ~a & b;

endmodule

Behavioral:

module half_sub_b(a, b, diff, borr);

input a, b;
output reg diff, borr;

always@(a or b)
begin

diff = a ^ b;
borr = ~a & b;
end
endmodule
Model Simulation output:
Test Bench
module half_sub_btb;

reg a, b;
wire diff, borr;

half_sub_d uut(a, b, diff, borr);

initial
begin
a = 0; b = 0;
#50; a = 1; b = 0;
#50; a = 1; b = 1;
#50; a = 0; b = 1;

end
endmodule

b) Full Adder and Full Subtractor

Aim:

To Simulate and synthesis Full Adders and Full subtractor using Verilog HDL.

Software tools required:

Synthesis tool: Xilinx ISE 14.1

Simulation tool: Project Navigator

Procedure:

Step1: Define the specifications and initialize the design.

Step2: Write the source code in VERILOG.
Step3: Check the syntax and debug the errors
Step4: Verify the output by simulating the source code.
Step5: Write all possible combinations of input using the test bench.
Step6: Obtain the place and route report.
Full Adder:

LOGICDIAGRAM: TRUTH TABLE:

A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1

1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

sum = x XOR y XOR cin

carry out = xy + xcin + ycin
Full Adder
Structural:

module full_adder_s(a, b, cin, sum, carry );

input a, b, cin;
output sum, carry;
wire ;

xor u1(s1, a, b);

xor u5(sum, s1, cin);

and u2(d1, a, b);

and u3(d2, s1, cin);
or u4(carry, d1, d2);

endmodule

Dataflow:

module full_adder_d(a, b, cin, sum, carry );

input a, b, cin;
output sum, carry;

assign sum = a ^ b ^ cin;

assign carry = (a & b) | (b & cin) | (cin & a);

endmodule

Behavioral

module full_adder_b(a, b, cin, sum, carry );

input a, b, cin;
output reg sum, carry;

always@(a or b or cin)
begin

sum = a ^ b ^ cin;
carry = (a & b) | (b & cin) | (cin & a);

end
endmodule
Model Simulation output:
 Testbench:
module full_adder_stb;

reg a, b, cin;
wire sum, carry;

full_adder_s uut(a, b, cin, sum, carry);

initial
begin

a = 0; b = 0; cin = 0;

#50; a = 0; b = 0; cin = 1;
#50; a = 1; b = 0; cin = 1;
#50; a = 1; b = 1; cin = 1;
#50; a = 1; b = 0; cin = 0;
#50; a = 1; b = 1; cin = 0;

end

endmodule

Full Subtractor:

Logic Diagram: Truth Table:

X Y Z B(Borrow) D (Difference)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
Structural:

module full_sub_s(diff, borr, x, y, z );

input x, y, z;
output diff, borr;
wire d1, b1, b2;

xor u1(d1, x, y);

xor u2(diff, d1, z);

not u3(xbar, x);

not u4(d1bar, d1);
and u5(b1, xbar, y);
and u6(b2, d1bar, z);
or u7(borr, b1, b2);

endmodule

Dataflow:

module full_sub_d(diff, borr, x, y, z );

input x, y, z;
output diff, borr;

assign diff = x^y^z;

assign borr = ((~x)&y) | (~(x^y)&z);

endmodule

Behavioral:
module full_sub_b(diff, borr, x, y, z );
input x, y, z;
output reg diff, borr;

always@(x or y or z)

begin
diff = x^y^z;
assign borr = ((~x)&y) | (~(x^y) & z);

end
endmodule
Model Simulation output:
Test Bench:

module full_sub_dtb;

reg x, y, z;
wire diff, borr;

full_sub_d uut(diff, borr, x, y, z );

initial
begin

x = 0; y = 0; z = 0;

#50; x = 1; y = 1; z = 0;
#50; x = 1; y = 1; z = 1;
#50; x = 1; y = 0; z = 0;
#50; x = 0; y = 1; z = 0;
#50; x = 0; y = 1; z = 1;

end
endmodule

c) Multiplexer And Demultiplexer:

Aim:
To develop the source code for Multiplexer and Demultiplexer by using VERILOG
and obtain the simulation, synthesis, place and route and implement into FPGA.

Procedure:

Step1: Define the specifications and initialize the design.

Step2: Write the source code in VERILOG.
Step3: Check the syntax and debug the errors
Step4: Verify the output by simulating the source code.
Step5: Write all possible combinations of input using the test bench.
Step6: Obtain the place and route report.
Mulutiplexer:
Logic diagram:
Truth table:

INPUT OUTPUT

s[1] s[0] y

0 0 D[0]

0 1 D[1]

1 0 D[2]

1 1 D[3]

Structural:

module mux_s(d0, d1, d2, d3, s0, s1, y);

input d0, d1, d2, d3, s0, s1;
output y;

not u1(a, s1);

not u2(b, s0);
and u3(c, d0, a, b);
and u4(e, d1, s0, a);
and u5(f, d2, b, s1);
and u6(g, d3, s0, s1);
or u7(h, c, e);
or u8(i, f, g);
or u9(y, h, i);

endmodule
Model Simulation output:
Dataflow:

module mux_d(d0, d1, d2, d3, s0, s1, y);

input d0, d1, d2, d3, s0, s1;
output y;

assign y = s1 ? (s0 ? d3 : d2) : (s0 ? d1 : d0);

endmodule

Behavioral:
module mux_b(din, s0, s1, y);

input [0:3] din;

input s0;
input s1;
output y;
reg y;
wire s0,s1;

always@(s0 or s1)
begin
case({s0,s1})
2'b00:y=din[0];
2'b01:y=din[1];
2'b10:y=din[2];
2'b11:y=din[3];
default:y=1'b1;
endcase
end
endmodule

Test Bench:
module mux_dtb;

reg d0, d1, d2, d3, s0, s1;

wire y;
mux_d uut(d0, d1, d2, d3, s0, s1, y);
initial begin
d0 = 0; d1 = 0; d2 = 0; d3 = 0; s0 = 0; s1 = 0;
#50; d0 = 1; d1 = 0; d2 = 0; d3 = 0; s0 = 0; s1 = 0;
#50; d0 = 1; d1 = 0; d2 = 0; d3 = 0; s0 = 0; s1 = 1;
#50; d0 = 1; d1 = 0; d2 = 0; d3 = 1; s0 = 1; s1 = 1;
end
endmodule
Demultiplexer:

Logic Diagram:
Truth table:

INPUT OUTPUT

I S0 S1 Y0 Y1 Y2 Y3

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1

Verilog Source Code:

Structural

module demux_s(i, s0, s1, y0, y1, y2, y3);

input i, s1, s0;

output y0, y1, y2, y3;

not u1(s0bar, s0);

not u2(s1bar, s1);
and u3(y0, i, s1bar, s0bar);
and u4(y1, i, s0bar, s1);
and u5(y2, i, s0, s1bar);
and u6(y3, i, s0, s1);

endmodule
Model Simulation output:
 Dataflow:

module demux_d(din, s0, s1, y0, y1, y2, y3);

input i, s1, s0;
output y0, y1, y2, y3;

assign y0 = (din & (~s0) & (~s1));

assign y1 = (din & (~s0) & s1);
assign y2 = (din & s0 & (~s1));
assign y3 = (din & s0 & s1);
endmodule

Behavioral:
module demux_b( s, din, y);

input [1:0] s;
input din;
output reg [3:0] y;

always @(s, din) begin

case (s)
2'b00 : begin
y[0] = din; y[3:1] = 0;
end
2'b01 : begin
y[1] = din; y[0] = 0; y[3:2] = 0;
end
2'b10 : begin
y[2] = din; y[1:0] = 0; y[3] = 0
end
2'b11 : begin
y[3] = din; y[2:0] = 0;
end
endcase
end
endmodule

Testbench:

module demux_stb;

reg i, s0, s1;

wire y0, y1, y2, y3;

demux_s uut(i, s0, s1, y0, y1, y2, y3);

initial
begin
i = 0; s0 = 0; s1 = 0;
 #50; i = 1; s0 = 1; s1 = 0;
#50; i = 1; s0 = 1; s1 = 1;
#50; i = 0; s0 = 0; s1 = 0;
#50; i = 1; s0 = 0; s1 = 1;

end
endmodule

d) Encoder and Decoder

Aim
To design an encoder and decoder using Verilog HDL, verify their
function, by simulating in Xilinx

Apparatus Required:
Synthesis tool: Xilinx ISE 14.1
Simulation tool: Project Navigator

Procedure
1. Write and draw the Digital logic system.
2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or
Xilinx) and
5. Verify the output waveform as obtained.
Encoder – Truth Table

INPUT OUTPUT
d7 d6 d5 d4 d3 d2 d1 d0 a b c

0 0 0 0 0 0 0 1 0 0 0

0 0 0 0 0 0 1 0 0 0 1

0 0 0 0 0 1 0 0 0 1 0

0 0 0 0 1 0 0 0 0 1 1

0 0 0 1 0 0 0 0 1 0 0

0 0 1 0 0 0 0 0 1 0 1

0 1 0 0 0 0 0 0 1 1 0

1 0 0 0 0 0 0 0 1 1 1
Verilog Code:

Structural

module encoder_s (d0, d1, d2, d3, d4, d5, d6, d7, a, b, c);

input d0,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;

or u1(a,d4,d5,d6,d7);
or u2(b,d2,d3,d6,d7);
or u3(c,d1,d3,d5,d7);

endmodule

Dataflow:
module encoder_d (d0, d1, d2, d3, d4, d5, d6, d7, a, b, c);
input d0,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;
assign a = d4 & d5 & d6 & d7;
assign b = d2 & d3 & d6 & d7;
assign c = d1 & d3 & d5 & d7;
endmodule

Behavioral:
module encoder_b(din,a,b,c);
input [0:7]din;
output a,b,c; reg a,b,c;

always@(din)
begin
case(din)
8'b10000000:
begin
a=1'b0; b=1'b0; c=1'b0;
end
8'b01000000:
begin
a=1'b0; b=1'b0; c=1'b1;
end
8'b00100000:
begin
a=1'b0; b=1'b1; c=1'b0;
end
8'b00010000:
begin
a=1'b0; b=1'b1; c=1'b1;
Model Simulation Output:
 end
8'b10001000:
begin
a=1'b1; b=1'b0; c=1'b0;
end
8'b10000100:
begin
a=1'b1; b=1'b0; c=1'b1;
end
8'b10000010:
begin
a=1'b1; b=1'b1; c=1'b0;
end
8'b10000001:
begin
a=1'b1; b=1'b1; c=1'b1;
end
default :
begin
a=1'bz; b=1'bz; c= 1'b1;
end
endcase
end
endmodule

Testbench:
module encoder_stb;

reg d0, d1, d2, d3, d4, d5, d6, d7;

wire a, b, c;

encoder_s uut(d0, d1, d2, d3, d4, d5, d6, d7, a, b, c);

initial
begin

d0 = 0; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = 0;

#50; d0 = 0; d1 = 0; d2 = 1; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = 0;
#50; d0 = 0; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = 0;
#50; d0 = 0; d1 = 0; d2 = 0; d3 = 0; d4 = 1; d5 = 0; d6 = 0; d7 = 0;
#50; d0 = 0; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 1; d7 = 0;
#50; d0 = 1; d1 = 0; d2 = 0; d3 = 0; d4 = 0; d5 = 0; d6 = 0; d7 = 0;

end
endmodule
Decoder – Truth Table

INPUTS OUTPUTS

d7 d6 d5 d4 d3 d2 d1 d0
a b c

0 0 0 0 0 0 0 1
0 0 0

0 0 0 0 0 0 1 0
0 0 1

0 0 0 0 0 1 0 0
0 1 0

0 0 0 0 1 0 0 0
0 1 1

0 0 0 1 0 0 0 0
1 0 0

0 0 1 0 0 0 0 0
1 0 1

0 1 0 0 0 0 0 0
1 1 0

1 0 0 0 0 0 0 0
1 1 1

:Verilog code Structural:

module decoder_d (a, b ,c, d0, d1, d2, d3, d4, d5, d6, d7);

input a, b, c;
output d0, d1, d2, d3, d4, d5, d6, d7;

not u1(abar, a);

not u2(bbar, b);
not u3(cbar, c);
and u4(d0, abar, bbar, cbar);
and u5(d1, abar, bbar, c);
and u6(d2, abar, b, cbar);
and u7(d3, abar, b, c);
and u8(d4, a, bbar, cbar);
and u9(d5, a, bbar, c);
Model Simulation Output:
and u10(d6, a, b, cbar);
and u11(d7, a, b, c);

endmodule

Dataflow:

module decoder_d (a, b ,c, d0, d1, d2, d3, d4, d5, d6, d7);
input a, b, c;
output d0, d1, d2, d3, d4, d5, d6, d7;
assign d0 = (~a & ~b & ~c);
assign d1 = (~a & ~b & c);
assign d2 = (~a & b & ~c);
assign d3 = (~a & b & c);
assign d4 = (a & ~b & ~c);
assign d5 = (a & ~b & c);
assign d6 = (a & b & ~c);
assign d7 = (a & b & c);
endmodule
Behavioral:
module decoder_b( Data_in, Data_out);
input [2:0] Data_in;
output [7:0] Data_out;
reg [7:0] Data_out;
always @(Data_in)
begin
case (Data_in)
3'b000 : Data_out = 8'b00000001;
3'b001 : Data_out = 8'b00000010;
3'b010 : Data_out = 8'b00000100;
3'b011 : Data_out = 8'b00001000;
3'b100 : Data_out = 8'b00010000;
3'b101 : Data_out = 8'b00100000;
3'b110 : Data_out = 8'b01000000;
3'b111 : Data_out = 8'b10000000;
default : Data_out = 8'b00000000;
endcase
end
endmodule
Testbench:
module decoder_dtb;
reg a, b, c;
wire d0, d1, d2, d3, d4, d5, d6, d7;
decoder_d uut(a,b,c,d0,d1,d2,d3,d4,d5,d6,d7);
initial
begin
a = 0; b = 0; c = 0;
#50; a = 0; b = 0; c = 1;#50; a = 1; b = 0; c = 0;
#50; a = 0; b = 1; c = 1;#50; a = 0; b = 1; c = 0;
#50; a = 1; b = 0; c = 1;
end
endmodule
e) FLIP-FLOP

Aim:
To design the basic sequential element flip-flop using Verilog HDL, verify its function, by
simulating in Xilinx

Apparatus Required:
Synthesis tool: Xilinx ISE 14.1
Simulation tool: Project Navigator

Procedure

1. Write and draw the Digital logic system.

2. Write the Verilog code for above system.
3. Enter the Verilog code in Xilinx software.
4. Check the syntax and simulate the above Verilog code (using ModelSim or Xilinx) and
5. verify the output waveform as obtained.

Circuit Diagram

D-Flip Flop

Excitation Table

SET RESET D CLK Q Qbar

0 1 - - 1 0

1 0 - - 0 1

0 0 - - 1 0

1 1 1 rising 1 0

1 1 0 rising 0 1
Jk-Flip Flop

Excitation Table:

J K Q(t+1)

Q(t) no
0 0
change
0 1 0(reset to 0)

1 0 1(set to 1)

1 1 Qbar(t)

Verilog Code for D flip flop:

module dff_tb;

reg d, clk, clear;

wire q, qbar;

dff uut(d,clk,clear,q,qbar);

initial
begin
clk = 0;
forever #10 clk = ~clk;
end

initial
begin
clear = 1;
d = 0;

#10 clear = 0; d = 1;
#20 d = 0;
#20 d = 1;
Model D Flip Flop Simulation Output:
 #20 d = 0;
#20 d = 1;
#20 d = 0;

end
endmodule

Test Bench:
module dff_tb;

reg d, clk, clear;

wire q, qbar;

dff uut(d,clk,clear,q,qbar);

initial
begin
clk = 0;
forever #10 clk = ~clk;
end

initial
begin
clear = 1;
d = 0;

#10 clear = 0; d = 1;
#20 d = 0;
#20 d = 1;
#20 d = 0;
#20 d = 1;
#20 d = 0;

end
endmodule

Verilog for JK Flipflop:

module jkff(j, k, clk, q, qbar);

input clk,j,k;
output reg q,qbar;

initial
begin
q <= 0;
qbar <= 1;
end
Model Simulation Output:
always@(posedge clk )
begin
case({j,k})
2'b00:
begin
q <=q;
qbar <= qbar;
end
2'b01:
begin
q <=1'b0;
qbar <= 1'b1;
end
2'b10:
begin
q <=1'b1;
qbar <= 1'b0;
end
2'b11:
begin
q <= qbar;
qbar <= q;
end
endcase

end
endmodule

Test Bench:

module jkff_tb( );

reg clk,j,k;
wire q,qbar;

jkf uut(j, k, clk, q, qbar);

initial
begin
clk = 0;
forever #10 clk = ~ clk;
end

initial
begin
j = 0; k = 0;

#10 j = 1; k = 0;
 #20 j = 0; k = 1;
#20 j = 0; k = 0;
#20 j = 1; k = 1;
#20 j = 0; k = 1;
#30
$finish;

end
endmodule

Result:
Thus the output of basic circuits are verified by synthesizing and simulating the
Verilog code. By doing this experiment,
 Exp. No: 2
8 Bit Adder
Date

Aim
To design 8- Bit Adders using Verilog HDL.

Software tools required:

Synthesis tool: Xilinx ISE 14.1

Simulation tool: Project navigator Simulator

Theory:

The n-bit adder built from n one –bit full adders is known as ripple carry adder
because of the carry is computed. The addition is not complete until n-1th adder has
computed its Sn-1 output; that results depends upon ci input, n and so on down the line, so the
critical delay path goes from the 0-bit inputs up through ci’s to the n-1 bit.(We can find the
critical path through the n-bit adder without knowing the exact logic in the full adder because
the delay through the n-bit adder without knowing the exact logic in the full adder because
the delay through the n- bit carry chain is so much longer than the delay from a and b to s).
The ripple-carry adder is area efficient and easy to design but it is when n is large. It can also
be called as cascaded full adder.
The simplified Boolean functions of the two outputs can be obtained as below:
Sum si = ai xor bi xor ci
Carry ci+1 = aibi +bi ci +ai ci
Where x, y & z are the two input variables.

Ripple Carry Adder:

Block diagram:
Model Simulation output:
Verilog Source Code:

1 bit Full Adder:

module fulladd(a, b, cin, sum, cout);

input a, b, cin;
output sum, cout;

assign sum=(a ^ b ^ cin);

assign cout=((a & b)|(b & cin)|(a & cin));

endmodule

8 Bit Adder:

module ripplemod(a, b, cin, sum, cout);

input [7:0] a, b;
input cin;
output [7:0]sum;
output cout;

wire[6:0] c;

fulladd u1(a[0],b[0],cin,sum[0],c[0]);
fulladd u2(a[1],b[1],c[0],sum[1],c[1]);
fulladd u3(a[2],b[2],c[1],sum[2],c[2]);
fulladd u4(a[3],b[3],c[2],sum[3],c[3]);
fulladd u5(a[4],b[4],c[3],sum[4],c[4]);
fulladd u6(a[5],b[5],c[4],sum[5],c[5]);
fulladd u7(a[6],b[6],c[5],sum[6],c[6]);
fulladd u8(a[7],b[7],c[6],sum[7],cout);

endmodule

Test Bench:

module ripplemod_tb;

reg [7:0] a, b;
reg cin;
wire [7:0] sum;
wire cout;

ripplemod uut(a, b, cin, sum, cout);

 initial
begin
a = 4'b0000; b = 4'b0000; cin = 4'b0000;

#50; a = 4'b0110; b = 4'b1100; cin = 0;

#50; a = 4'b0010; b = 4'b0100; cin = 0;
#50; a = 4'b1000; b = 4'b1010; cin = 1;
#50; a = 4'b0010; b = 4'b0010; cin = 0;
#50; a = 4'b1000; b = 4'b0110; cin = 1;

end
endmodule

Carry Lookahead Adder:

Logic Diagram:

Verilog Source Code:

module cla_adder(a,b,cin,sum,cout);

input[3:0] a,b;
input cin;
output [3:0] sum;
output cout;
wire p0,p1,p2,p3,g0,g1,g2,g3,c1,c2,c3,c4;

assign p0=(a[0] ^ b[0]);

assign p1=(a[1] ^ b[1]);
assign p2=(a[2] ^ b[2]);
assign p3=(a[3] ^ b[3]);
Model Simulation output:
assign g0=(a[0] & b[0]);
assign g1=(a[1] & b[1]);
assign g2=(a[2] & b[2]);
assign g3=(a[3] & b[3]);
assign c0=cin;
assign c1=g0 | (p0 & cin);
assign c2=g1 | (p1 & g0) | (p1 & p0 & cin);
assign c3=g2 | (p2 & g1) | (p 2& p1 & g0)|(p1 & p1 & p0 & cin);
assign c4=g3 | (p3 & g2)|(p3 & p2 & g1) | (p3 & p2 & p1 & g0) | (p3 & p2 & p1 & p0 & cin);
assign sum[0]=p0 ^ c0;
assign sum[1]=p1 ^ c1;
assign sum[1]=p1 ^ c1;
assign sum[2]=p2 ^ c2;
assign sum[3]=p3 ^ c3;
assign cout=c4;
endmodule

Test Bench:
module cla_adder_tb;
reg [3:0] a, b;
reg cin;

wire [3:0] sum;

wire cout;

cla_adder uut(a,b,cin,sum,cout);

initial
begin
a = 4'b0000; b = 4'b0000; cin = 4'b0000;

#50; a = 4'b0110; b = 4'b1100; cin = 0;

#50; a = 4'b0010; b = 4'b0100; cin = 0;
#50; a = 4'b1000; b = 4'b1010; cin = 1;
#50; a = 4'b0010; b = 4'b0010; cin = 0;
#50; a = 4'b1000; b = 4'b0110; cin = 1;

end
endmodule

Result:
Thus the output of 8-bit adder are verified by synthesizing and simulating the Verilog
code.
 Exp. No: 5 Design of Universal Shift Register

Date

AIM:
To develop the source code for the design of universal shift register using VERILOG
and obtain the simulation, synthesis, place and route and implement into FPGA.

ALGORITM:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using Verilog source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

LOGIC DIAGRAM:
 Mode of Operation

S0 S1 Mode of Operation
0
0 Locked state (No change)
0
1 Shift-Left
Shift-Right
1 0
Parallel Loading
1 1

Verilog Code:

module usr(clk, clear, sel, p1, p2, p3, p4, seri, sele, q1, q2, q3, q4);

input clk, clear, p1, p2, p3, p4, seri, sele;

input [1:0]sel;
output q1, q2, q3, q4;

mux u1(p4, q3, seri, q4, sel, y4);

mux u2(p3, q2, q4, q3, sel, y3);
mux u3(p2, q1, q3, q2, sel, y2);
mux u4(p1, sele, q2, q1, sel, y1);

dff u5(y4, clk, clear, q4);

dff u6(y3, clk, clear, q3);
dff u7(y2, clk, clear, q2);
dff u8(y1, clk, clear, q1);

endmodule

******************************************************************

module dff(d,clk,clear,q);

input d, clk, clear;

output reg q;

initial
begin
q = 0;
end
always@(posedge clk)
begin
if(clear== 1)
q <= 0;

else
end q <= d;
endmodule

******************************************************************

module mux (a, b, c, d, sel, y);

input a, b, c, d;
input [1:0] sel;
output reg y;

always@(a, b, c, d, sel)
begin
case(sel)
2'b11 : y = a;
2'b10 : y = b;
2'b01 : y = c;
2'b00 : y = d;
endcase
end
endmodule

Test Bench:

module usr_tb;

reg clk, clear, p1, p2, p3, p4, seri, sele;

reg [1:0] sel;
wire q1, q2, q3, q4;

usr uut(clk, clear, sel, p1, p2, p3, p4, seri, sele, q1, q2, q3, q4);

initial
begin
clk = 0;
forever #10 clk = ~clk;
end

initial
begin
clear = 1;
sel = 2'b00;
p1 = 0;
p2 = 0;
Model Simulation output:
 p3 = 0;
p4 = 0;
seri = 0;
sele = 0;

#10
clear = 0;
sel = 2'b11; //pipo
p1 = 1;
p2 = 0;
p3 = 1;
p4 = 0;

#20
sel = 2'b10; //shift left
sele = 1;
#20
sele = 0;
#20
sele = 1;
#20
sele = 0;

#80
sel = 2'b01; //shift right
seri = 1;
#20
seri = 0;
#20
seri = 1;
#20
seri = 0;

end
endmodule

Result:
Thus the output for the design of Universal Shift Register was verified by synthesizing
and simulating the Verilog code.
 Exp. No: 6 Design of Finite State Machine

Date

Aim:
To develop the source code for Finite State Machine by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.

Algorithm:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using Verilog source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

Logic Diagram:

Verilog Source Code:

module seq_det(sin,clk,reset,y);

input sin,clk,reset;
output y;
reg y;
reg [1:0] r_reg, n_reg;

parameter s0 = 2'b00, s1 = 2'b01, s2 = 2'b10;

always @(posedge clk or posedge reset)

if (reset)
r_reg <= s0;
else
r_reg <= n_reg;

always @(r_reg or sin)

if (r_reg==s0 && sin==0) n_reg=s0;
else if (r_reg==s0 && sin==1) n_reg=s1;
else if (r_reg==s1 && sin==0) n_reg=s0;
Model Simulation Output:
 else if (r_reg==s1 && sin==1) n_reg=s2;
else if (r_reg==s2 && sin==0) n_reg=s0;
else if (r_reg==s2 && sin==1) n_reg=s2;

always @(r_reg or sin)

if (r_reg==s2 && sin==0) y=1;
else y=0;

endmodule

Test Bench:

module seq_det_tb;

reg sin,clk,reset;
wire y;
seq_det d1(sin,clk,reset,y);

initial
begin
clk = 1'b0;
repeat (41)
#5 clk = ~clk;
end

initial
begin
$monitor($time,"sin=%b,clk=%b,reset=%b,y=%b", sin, clk, reset, y);
reset = 1;sin=0;
#10 reset =0;
#10 sin = 1;
#10 sin = 0;
#10 sin = 1;
#10 sin = 1;
#10 sin = 0;
#10 sin = 0;
#10 sin = 1;
#10 sin = 1;
#10 sin = 0;
#10 sin = 1;
end
endmodule
Verilog Source Code:

module seq_det_moore(sequence_in,clock,reset,detector_out );

input clock;
input reset;
input sequence_in;
output reg detector_out;
parameter Zero=3'b000, One=3'b001, OneZero=3'b011, OneZeroOne=3'b010,
OneZeroOneOne=3'b110;

reg [2:0] current_state, next_state;

always @(posedge clock, posedge reset)

begin
if(reset==1)
current_state <= Zero;
else
current_state <= next_state;
end

always @(current_state,sequence_in)
begin
case(current_state)
Zero:begin
if(sequence_in==1)
next_state = One;
else
next_state = Zero;
end

One:begin
if(sequence_in==0)
next_state = OneZero;

else
end next_state = One;

OneZero:begin
if(sequence_in==0)
next_state = Zero;
else
next_state = OneZeroOne;
end

OneZeroOne:begin
if(sequence_in==0)
next_state = OneZero;

else
end next_state = OneZeroOneOne;
 OneZeroOneOne:begin
if(sequence_in==0)
next_state = OneZero;
else
next_state = One;
end

default:next_state = Zero;
endcase
end

always @(current_state)
begin
case(current_state)
Zero: detector_out = 0;
One: detector_out = 0;
OneZero: detector_out = 0;
OneZeroOne: detector_out = 0;
OneZeroOneOne: detector_out = 1;
default: detector_out = 0;
endcase
end

endmodule

Test Bench:
module seq_det_moore_tb;

reg sequence_in;
reg clock;
reg reset;

wire detector_out;

seq_det_moore uut(sequence_in,clock,reset,detector_out );

initial
begin
clock = 0;
forever #5 clock = ~clock;
end

initial
begin
sequence_in = 0;
reset = 1;

#30; reset = 0;
#20; sequence_in = 1;
Model Simulation Output:
 #20; sequence_in = 1;
#10; sequence_in = 0;
#10; sequence_in = 1;
#20; sequence_in = 0;
#20; sequence_in = 1;
#20; sequence_in = 0;

end

endmodule

Result:
Thus the output of finite state machine are verified by synthesizing and simulating the
Verilog code.
 Exp. No: 7 Design of Memories

Date

Aim:
To develop the source code for the design memories by using VERILOG and obtain the
simulation, synthesis, place and route and implement into FPGA.

Algorithm:
Step1: Define the specifications and initialize the design.
Step2: Declare the name of the entity and architecture by using Verilog source code.
Step3: Write the source code in VERILOG.
Step4: Check the syntax and debug the errors if found, obtain the synthesis report.
Step5: Verify the output by simulating the source code.
Step6: Write all possible combinations of input using the test bench.
Step7: Obtain the place and route report.

Verilog Source Code:

module memory_read_write(clk, address, datain, rd_wr, cs, dataout);

input [7:0] datain;

input [9:0]address;
input rd_wr, cs, clk;

output reg [7:0] dataout;

reg [7:0] memory [1:1023];

always@(posedge clk)
begin

if (cs == 1 && rd_wr == 1)

end memory[address] <= datain;

always@(posedge clk)
begin

if(cs == 1 && rd_wr == 0)

end dataout <= memory[address];

endmodule
Model Simulation:
Test Bench:
module memory_read_write_tb;

reg clk, rd_wr, cs;

reg [9:0] address;
reg [7:0] datain;
wire [7:0] dataout;

memory_read_write uut(clk, address, datain, rd_wr, cs, dataout);

initial begin
clk = 0;
forever #10 clk = ~clk;
end

initial
begin
address =
10'b00_0000_0000; datain =
8'b0000_0000; rd_wr = 0;
cs = 0;

#10 cs = 1; rd_wr = 1; address = 10'b1100_0101; datain = 8'b1010_0011;

#20 address = 10'b1010_0111; datain = 8'b1110_0111;

#20 rd_wr = 0; address = 10'b1100_0101;

#20 address = 10'b1010_0111;
#20 $finish;

end
endmodule

Result:
Thus the output for the design of memories are verified by synthesizing and simulating
the VERILOG code.
 Exp. No: 8 CMOS Inverter using Digital Flow

Date

Aim:
To develop the layout design for CMOS inverter layout by using MICROWIND and
obtain the simulation results.

Microwind:

The Microwind program allows designing and simulating an integrated circuit at physical
description level. The package contains a library of common logic and analog ICs to view and
simulate.

Purpose of Design Rules:

1. As all the layouts are prepared with minimum ë design rules .With minimum ë , layout
will require less amount of area on chip, so larger circuits can be implemented with in
less area.
2. Makes the circuit to consumes less amount power i.e. as area and polysilicon usage can
also reduced, resulting less resistance ,which in turn causes to dissipate less amount of
power.
3. Design rules will give optimized layout.

CMOS Design Rules:

PMOS Transistor
1. The complete window can be considered as P-well.
2. The N-well is placed over the p-well in a rectangular box.
3. Next we need to place the P-diffusion over the N-well.
4. Width of the P-diffusion should be 4ë.
5. The metal contacts can be drawn by selecting a (4ë*4ë) square.

NMOS Transistor
1. There should be minimum 6ë space between N-well and N-diffusion.
2. The same steps can be followed for nmos as in pmos.
3. The grid itself is P-well, we can start directly with n-diffusion layer.
4. The pmos and nmos should be connected by using poly silicon layer of width 2ë.
5. The poly silicon layer should be extended up to 3ë length above and below
P and N diffusion layers.
6. Leave minimum 1ë space on both sides of poly silicon between the contacts.
7. The source to drain connection is made using a metal of width 3ë.

Logic Diagram:
Layout Design:

1. Add poly silicon

2. Add N+ diffusion
3. Add P+ diffusion

4. Add Nwell
5. Add metal 1

6. Add metal 1
7. Add metal1/metal2 contact

8. Add P+diff/metal contact

9. Add N+ diff/metal1

10. Add Metal1/poly

11. Add VDD and ground

12. Add Input and output

 13. Compile with Polarize Nwell to VDD (safe)

Simulation Output:

Voltage vs Time:
Voltage vs Voltage:

Result:
Thus the layout of CMOS inverter are designed and the output is verified by using
Microwind tool.
 Exp. No: 9
CMOS basic gates and Flip flops
Date

Aim:
To develop the layout design for basic logic gates by using microwind and obtain the
simulation results.

NAND Gate:
Logic Diagram:

Layout Design:
SIMULATION OUTPUT:

Model Voltage vs Time:

NOR Gate:

Logic Diagram:
Layout Design:

Model Simulation Output:

Voltage vs Time:
D Flip Flop:

Logic Diagram:

Layout Diagram:
Model Simulation Output:

Voltage vs Time:

RESULT:
Thus the layouts of Basic Logic Gates and D flipflop are designed and output is
verified by using Microwind tools.
 Exp. No: 10
4 Bit synchronous counter using flip flops
Date

Aim:
To develop the layout design for 4 bit synchronous counter using D flip flop by
Microwind and obtain the simulation results.

Logic Diagram:
Layout Design:
Model Simulation Output:

Voltage vs Time:

RESULT:

Thus the layout of 4 bit synchronous counter using flip flop are designed and outputs
are verified by using Microwind tools.
 Exp. No: 11
CMOS Inverting Amplifier
Date

Aim:
To design a CMOS Inverting Amplifier by using microwind DSCH tool and obtain
the simulation results.

CMOS Inverting Amplifier:

Layout Diagram:
Model Simulation Output:

RESULT:
Thus the CMOS Inverting Amplifier was designed and output were verified by using
Microwind DSCH tool.
 Exp. No: 12 a
Basic Common Source Amplifiers
Date

Aim:
To simulate the schematic of the common source amplifier, and then to perform the
physical verification for the layout of the same.

Tool Required:

Microwind DCSH

Theory:
In electronics, a common-source amplifier is one of three basic single-stage field-
effect transistor (FET) amplifier topologies, typically used as a voltage or transconductance
amplifier. The easiest way to tell if a FET is common source, common drain, orcommon gate
is to examine where the signal enters and leaves. The remaining terminal is what is known as
"common". In this example, the signal enters the gate, and exits the drain. The only terminal
remaining is the source. This is a common-source FET circuit. The analogous bipolar junction
transistor circuit is the common-emitter amplifier.
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as a
voltage amplifier. (See classification of amplifiers). As a transconductance amplifier, the
input voltage is seen as modulating the current going to the load. As a voltage amplifier, input
voltage modulates the amount of current flowing through the FET, changing the voltage
across the output resistance according to Ohm's law. However, the FET device's output
resistance typically is not high enough for a reasonable transconductance amplifier (ideally
infinite), nor low enough for a decent voltage amplifier (ideally zero). Another major
drawback is the amplifier's limited high-frequency response.

Circuit Diagram:
Output – Transient Response: Output – DC Analysis:
Layout Diagram:

Result:

Thus the schematic for the common source amplifier is drawn and verified DC
Analysis and Transient Analysis.
 Exp. No: 12 b
Basic Common Drain Amplifiers
Date

Aim:
To simulate the schematic of the common drain amplifier, and then to perform the
physical verification for the layout of the same.

Tool Required:

Microwind DCSH

Theory:
Common drain amplifier is a source follower or buffer amplifier circuit using a
MOSFET. The output is simply equal to the input minus about 2.2V. The advantage of this
circuit is that the MOSFET can provide current and power gain; the MOSFET draws no
current from the input. It provides low output impedance to any circuit using the output of the
follower, meaning that the output will not drop under load.
Its output impedance is not as low as that of an emitter follower using a bipolar transistor (as
you can verify by connecting a resistor from the output to -15V), but it has the advantage that
the input impedance is infinite. The MOSFET is in saturation, so the current across it is
determined by the gate-source voltage. Since a current source keeps the current constant, the
gate-source voltage is also constant.

Layout Diagram:
Output: AC and DC Analysis:
Result:
Thus the schematic for the common drain amplifier is drawn and verified DC Analysis
and AC Analysis.
 Exp. No: 13
Simple 5 transistor Differential Amplifier
Date

Aim:

To design the simple 5 transistor Differential Amplifier by using microwind DSCH

and obtain the simulation result.

Theory: Differential amplifier: Differential Amplifier amplifies the current with very little
voltage gain. It consists of two FETs connected so that the FET sources are connected together.
The common source is connected to a large voltage source through a large resistor Re, forming
the "long tail" of the name, the long tail providing an approximate constant current source. The
higher the resistance of the current source Re, the lower Ac is, and the better the CMRR. In
more sophisticated designs, a true (active) constant current source may be substituted for the
long tail. The output from a differential amplifier is itself often differential.

Algorithm:
 Open the DSCH2
 Drag the components like PMOS, NMOS, voltage source, ground, and LED from the symbol
library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & run the simulation
 Make verilog file go to Microwind and compile the Verilog file saved in DSCH2
 Compile it and obtain the layout diagram & draw the waveform.

Circuit Diagram:
Model Simulation Output:

Voltage vs Time:
Result:
Thus the schematic for the simple 5 transistor Differential Amplifier is drawn and
verified by using the microwind DCSH tool.