ASSERTIONS

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WHAT IS ASSERTION?

 An Assertion in the context of a programming language is a statement that

validates assumptions or checks conditions in a program.

 A piece of verification code to validate behaviour and constraints of a design.

EXAMPLES:

• Write will follow read after 6 clock cycles.

• Read and Write should not happen at same clock cycle.
 Benefits of Assertions?

 In traditional verification approach we will

inject random stimulus into the DUT and checks
result at output.
 For complex designs coverage and debugging is
harder.
 Assertions comes here to improve the
verification process.
Types of Assertions
 Two types of assertions defined in the SVA.

• Immediate Assertions
• Concurrent Assertions

 Immediate Assertions:
• These are event driven and procedural in nature
• Mainly used in simulation block
• Based on clock cycles
• Evaluated in Observed region
Immediate Assertions
 An assertion is basically a statement that something must be true,
similar to if statement. Expression is non temporal.

 If assert evaluates to X, Z or 0, then the assertion fails and the simulator

writes an error message.

 If an expression is not true and it does not have an associated else part,
verification tools automatically register that as an error.
Concurrent Assertions
 Immediate assertion describes a logic behaviour at an instant of time, where a
concurrent assertion detects a behaviour over time to be specified.

 The variables used in a concurrent assertion are sampled in the Preponed region of
a time slot and the assertions are evaluated during the Observe region. Both these
regions occur immediately before a clock edge.

 Concurrent assertions are checked throughout simulation. They usually appear

inside procedural block or with in a module.

 Concurrent assertions may also be used as statements in initial or always blocks. A

concurrent assertion in an initial block is only tested on the first clock tick.
Concurrent Assertions cont...
 The first assertion example shown below does not contain a clock. Therefore
it is checked at every point in the simulation. The second assertion is only
checked when a rising clock edge has occurred, the values of Req and Ack are
sampled on the rising edge of Clock.

 In concurrent assertion there are three main components.

• Sequence
• Property
• Assert - property
Concurrent Assertions cont...
Sequence :
 In any design, functionality is represented by the combination of
multiple logical events.
 These events could be simple Boolean expressions that get evaluated
on the same clock edge or could be events that evaluate over a
period of time involving multiple clock cycles.
 SVA provides a key word to represent these events called
"sequence."
 The basic syntax of a sequence is as follows.
Concurrent Assertions cont...
Sequences (cont..):
 Sequence s1 checks that the data signal is high on every positive edge of the clock.
If data signal is not high on any positive clock edge, the assertion will fail.
 Concurrent assertions use the values sampled in the "preponed" region of the
scheduler. For example , 5th clock cycle positive edge data goes low here, 6th clock
cycle positive edge captures this as shown below.
Concurrent Assertions cont...
Sequence with edge :
 Sequence s2 checks that the data signal transitions to a value of 1 on every
positive edge of the clock. If the transition does not occur, the assertion will fail.
 At clock cycle 2, the sampled value of data signal within the sequence is 1. A
transition of value from 0 to 1 is a rising edge and hence, the sequence s2
succeeds in clock cycle 2. Another succeed is shown at 7th clock cycle.
 cont...
Concurrent Assertions (Cont..)
Sequencewith
Sequence with logical
logical relationship
relationship
 Sequence seq checks that on every positive edge of the clock, either signal
“sig1" or signal “sig2" is high. If both are low, the assertion will fail.

Sequence Expressions
 Define formal arguments in a sequence definition and re-use the same sequence
for other signals in design that have similar behavior.
• For example,
Concurrent Assertions cont...
Sequence Expressions (Cont..)
 Sequences of Boolean expressions can be described with a specified time step in-
between.
 Consider the following example at pose edge of clock ‘a’ should be high, after
two clock cycles ‘b’ should be high, after four clock cycles ‘c’ should be high and
‘z’ should be high with in one to five clock cycles.
Concurrent
Concurrent Assertions
Assertions cont...
(Cont..)
Sequence
Sequence Replication operators:
with logical relationship
 Consecutive Repetition Operator [* ]
• To specify that a signal or a sequence will match continuously for the
number of specified clocks.
• A hidden delay of one clock cycle is assumed between each match of the
signal.
• Syntax: signal or sequence [* n]
• "n" is the number of times the expression should match repeatedly.
a ##2 b [*5] ##6 c a ##2 b ##1 b ##1 b ##1 b ##1 b ##6 c
s1 [*4] s1##1 s1##1 s1 ## 1 s1
(s1 ##1 s2) [*3] (s1 ##1 s2) ##1 (s1 ##1 s2) ##1 (s1 ##1 s2)
a [*3] a ##1 a ##1 a
s1[*2:$] means s1 occurs at least 2 times
Concurrent Assertions cont...
Sequence Replication operators Cont..
 Goto Repetition Operator [-> ]
• This operator specify that an expression will match the number of times
specified not necessarily on continuous clock cycles.
• Syntax: signal [->]

y [->4] The Boolean expression y has been true 4 times, but not
necessarily on successive clocks
x [->4:7] x has been true 4, 5, 6 or 7 times, not necessarily on
consecutive clocks
x ##3 y [->3] ##6 z The Boolean expression y has been true thrice, not
necessarily on consecutive clocks, 1st occurrence of y
happens after 3 clocks cycles of x. The last one occurs 6
clock cycles before z.
Concurrent Assertions cont...
Sequence Match Operators
 The "and" construct
• The binary operator "and" can be used to combine two sequences logically.
The final property succeeds when both the sequences succeed.
• The result of and operation is a match, if
• Both sequences must start at the same time.
• Sequences may end at different times.
• The end time of the match i.e. when the match is recognized is the end
time of the longer sequence.

A t1 t7
A,B Match at t7

B t1 t5

CLK
Concurrent Assertions cont...
Sequence Match Operators (Cont..)
 The OR operator
• The binary operator "or" can be used to combine two sequences logically.
• The final property succeeds when any one of the sequence succeeds.
• The sequence B matches (or, it ends) at time t7. The sequence A matches
at time t5. So the sequence A or B has a match at times t5 and t7.

B t1 t7

A A,B Matches at t5,t7

t1 t5

CLK
Concurrent Assertions cont...
Property:
 Number of sequences can be combined logically or sequentially to
create more complex sequences. SVA provides a key word to
represent these complex sequential behaviors called "property."
 The basic syntax of a property is as follows.
Concurrent Assertions cont...
Assert Property:
 The property is the one that is verified during a simulation. It has
to be asserted to take effect during a simulation.
 SVA provides a key word called "assert" to check the property.
 Assert statements produce results that are visible externally.
 The basic syntax of an assert is as follows.
Concurrent Assertions cont...
Assert property (cont..)
 An assert either succeeds, fails or remain incomplete.
 A property can also be forbidden from happening. We expect the property
to be false always. If the property is true, the assertion fails.

Assertion used as check Assertion used as forbid

Concurrent Assertions cont...
Assertion Clocking
 Concurrent assertions (assert property and cover property statements) use a
generalized model of a clock and are only evaluated when a clock tick occurs.
 Everything in between clock ticks is ignored. This model of execution corresponds
to the way a RTL description of a design is interpreted after synthesis.

 The clock for a property can be specified in several ways:

 Explicitly specified in a sequence:
Concurrent Assertions cont...
Assertion Clocking (Cont..)
 Explicitly specified in the property:

 Explicitly specified in the concurrent assertion:

 Inferred from a procedural block:

Concurrent Assertions cont...
Example :
 At any positive edge of clock, If ‘enable’ is High, ‘write’ is high and ‘read’ is
High 2 clocks later.
Concurrent Assertions cont...
Example :
 With formal arguments:
Delays
 Fixed time window
• ## n - n clock cycles delay
• n can be zero (no delay)
• Must be a positive integer
• a ## 1 b - This means b starts one clock after a ends.
 Fixed Time interval
• ## [m : n] – With in m to n clock cycles delay
• ## [1:3] – With in 1 to 3 clock cycles delay
• n must be greater than m
 Indefinite timing window
• ## [1 : $] – Between one clock cycle and end of the simulation
• This is called the "eventuality" operator.
Implication operators
 Implication operators only used inside the property.
 Two types of operators
• Overlapping ( )
• Non overlapping ( )
• The left-hand operand is called the antecedent, while the right-hand operand is called
the consequent.

 Overlapping:
• If enable is high at posedge of clock write should be high at same
positive edge of clock and read must be high 2 clock cycles later.
Implication operators (Cont..)
 Non-Overlapping :

• For non-overlapped implication, the first element of the consequent

sequence expression is evaluated on the next clock tick.
• If enable is high at posedge of clock write should be high at next positive
edge of clock and read must be high 2 clock cycles later.
Implication operators (Cont..)
Implication with a sequence as an antecedent

 Property prp1 has a signal in the antecedent position. If signal "a" and signal "b" are
detected to be high, then two clock cycle later, signal "c" should be high. Sequence seqb
checks that, After 1 clock cycles from the current positive edge of the clock, signal "d”
should be low.
 The final property checks that, if sequence seqa succeeds, then a check for sequence
seqb is performed.
Clock definitions in SVA
 A clock can be specified in a sequence, in a property or even in an assert statement.

Clock in Sequence Clock in Property

Clock definitions in SVA (Cont..)
 The assert statement calls a property, Separate property definition is not
needed to assert a sequence. Since the expression to be checked can be
called from the assert statement directly.

Clock in Assert
Assertion System Functions
 SystemVerilog provides a number of system functions, which can be used in
assertions.
 $rose, $fell and $stable indicate whether or not the value of an expression has
changed between two adjacent clock ticks.
 For example,
• Asserts that if in changes from 0 to 1 between one rising clock and the next,
detect must be 1 on the following clock.

• States that data shouldn’t change while enable is 0.

Assertion System Functions cont..
 The system function $past returns the value of an expression in a previous
clock cycle. States that q increments, provided reset is low and enable is high.

 The system functions $onehot and $onehot0 are used for checking one-hot
encoded signals. $onehot(expr) returns true if exactly one bit of expr is high;
$onehot0(expr) returns true if at most one bit of expr is high.
Summary

 Assertions are great way to verify complex designs . Assertions

only can be used to completely authenticate a design as robust
 By creating testbench with functional coverage we can
understand which all functionalities of the design are covered in
test
 Creation of testbench with functional coverage requires detailed
verification plan