Dept.

of ECE, RIT, Hassan VLSI Lab Manual

Introduction
An HDL is a programming language used to describe electronic circuit essentially
digital logic circuits. It can be used to describe the operation, design and organization of a
digital circuit. It can also be used to verify the behaviour by means of simulations. The
principle difference between HDL and other programming languages is that HDL is a
concurrent language whereas the others are procedural i.e. single threaded. HDL has the
ability to model multiple parallel processes like adders, flip-flops execute automatically and
independently of each other. It is like building many circuits that can operate independently
of each other. It is a computer aided design (CAD) tool for the modern design and synthesis
of digital systems. The recent, steady advances in semiconductor technology continue to
increase the power and complexity of digital systems. Due to their complexity, such systems
cannot be realized using discrete integrated circuits. They are usually realized using high
density, programmable chips, such as application specific Integrated circuits (ASICs) and
Field programmable gate arrays (FPGAs) and require sophisticated CAD tools. HDL is an
integral part of such tools. HDL offers the designer a very efficient tool for implementing and
synthesizing designs on chips.
The two widely used HDLs are:
VHDL: Very High-Speed Integrated Circuits HDL
Verilog HDL
VHDL (VHSIC Hardware Description Language) is a hardware description language
used in electronic design automation to describe digital and mixed-signal systems such as
field-programmable gate arrays and integrated circuits. VHDL can also be used as a general-
purpose parallel programming language.
Verilog, standardized as IEEE 13.64, is a hardware description language (HDL) used
to model electronic systems. It is most commonly used in the design and verification of
digital circuits at the register-transfer level of abstraction. It is also used in the verification of
analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.

ABOUT XILINX ISE SOTWARE

Xilinx ISE (Integrated Synthesis Environment) is a software tool produced by Xilinx
for synthesis and analysis of HDL designs, enabling the developer to synthesize ("compile")
their designs, perform timing analysis, examine RTL diagrams, simulate a design's reaction to

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different stimuli, and configure the target device with the programmer. Xilinx ISE is a design
environment for FPGA (Field programmable gate arrays) products from Xilinx, and is
tightly-coupled to the architecture of such chips, and cannot be used with FPGA products
from other vendors. The Xilinx ISE is primarily used for circuit synthesis and design, while
ISIM or the ModelSim logic simulator is used for system-level testing

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1. A 4-Bit Adder
AIM: To write Verilog code for 4-bit adder and its test bench for verification and observe
the waveform and synthesize the code.

OBJECTIVE: The objective of this program is to design, implement, verify, and analyse a
4-bit adder to ensure:

 Correct functionality through simulation

 Efficient synthesis in terms of speed, power, and area
 Understanding of timing constraints and optimization techniques in digital design

THEORY:
A full adder is a combinational circuit that performs the arithmetic sum of three input
bits Ai, addend Bi and carry in C in from the previous adder. Its results contain the sum Si
and the carry out, C out to the next stage. So to design a 4-bit adder circuit we start by
designing the 1 bit full adder then connecting the four 1-bit full adders to get the 4-bit adder
as shown in the diagram below. For the 1-bit full adder, the design begins by drawing the
Truth Table for the three input and the corresponding output SUM and CARRY.

PROGRAM:

module paralleladder(a,b,cin,sum,cout); //Declares a Verilog module named

paralleladder
input[3:0]a; // Declares ‘a’ as a 4-bit input.
input[3:0]b; // Declares ‘b’ as a 4-bit input
input cin; // Declares ‘cin’ as a single-bit carry-in input.
output[3:0]sum; // Declares ‘sum’ as a 4-bit output.
output cout; // Declares ‘cout’ as the final carry-out.
wire[2:0]cint; // Declares a 3-bit wire ‘cint’ to hold intermediate carry outputs
from each full adder stage
fa fa1(a[0],b[0],cin,sum[0],cint[0]); // First full adder instance
fa fa2(a[1],b[1],cint[0],sum[1],cint[1]); // Second full adder instance
fa fa3(a[2],b[2],cint[1],sum[2],cint[2]); // Third full adder instance
fa fa4(a[3],b[3],cint[2],sum[3],cout); // Fourth full adder instance
endmodule //End the program

module fa(x,y,z,s,co);
input x,y,z; // Three 1-bit inputs.
output s,co; // Two 1-bit outputs.
assign {co,s}=x+y+z; // The addition of three 1-bit inputs
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endmodule //End the program

TESTBENCH:

module paralleladder_tb; // Defines the testbench module

reg[3:0]a; // 4-bit register to hold input a
reg[3:0]b;// 4-bit register to hold input b
reg cin; // 1-bit register to hold carry-in (cin)
wire[3:0]sum; // 4-bit wire to capture the sum output
wire cout; // 1-bit wire to capture the carry-out.

paralleladder fbpa1(a,b,cin,sum,cout); // Instantiation of the 4-bit Parallel Adder

initial // Stimulus Generation using initial Block
begin
a=4'b0000; // Test cases:
b=4'b1001;
cin=1'b0;
#200; // Each test case waits for 200 time units (#200) before applying the
next set of values.

a=4'b0110; // Test cases:

b=4'b1001;
cin=1'b0;
#200;
a=4'b0100; // Test cases:
b=4'b1001;
cin=1'b0;
#200;
end
endmodule //End the program

BLOCK DIAGRAM:
The block diagram of adder as shown in below figure.

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RTL SCHEMATIC DIAGRAM:

DESIGN UTILIZATION SUMMARY:

SYNTHESIS REPORT:

MAX CLOCK FREQUENCY CALCULATION

Using delay = ns,
the max frequency is:
1
fmax= … … … … .. ns =……….. MHz

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This means the Adder can operate at a maximum clock speed of ~……………….Hz

WAVEFORM:

PROCEDURE:
 Select new project and type the project name.
 Enter the device properties and click next.
 Click new source and select the Verilog module and then give the file name.
 Type the Verilog program and save it.
 Click new source and select the Verilog test fixture and then give the file name.
 Type the Verilog test bench program and save it.
 Double click the synthesize XST and check syntax.
 Double click the implement design.
 Simulate the waveform by behavioural simulation.
 Note down RTL schematic and analyse the design summary.

RESULT: Verilog code for 4-bit adder and its test-bench for verification are written, the
waveform is observed and the code is synthesized.

OUTCOME: Students are able to

 The functionality of the adder is verified through simulation, ensuring that it
correctly adds the input values 'a' and 'b' to produce the sum output.
 Analysis the waveform generated during simulation is analysed to confirm that
the counter behaves as expected.
 The synthesized netlist is analysed for timing performance, area utilization,
and any other relevant metrics.

VIVA QUESTIONS
1. What is a 4-bit adder?
2. What is the difference between a half adder and a full adder?
3. What type of adder is used in a 4-bit adder?
4. What are the inputs and outputs of a 4-bit adder?
5. What is the role of carry propagation in a 4-bit adder?
6. What is a ripple-carry adder?
7. What is the main disadvantage of a ripple-carry adder?

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8. How can we improve the speed of a 4-bit adder?

9. What is the purpose of a testbench in Verilog?
10. How do you check for overflow in a 4-bit adder?
11. What are the synthesis constraints for a 4-bit adder?
12. What factors affect the delay of a 4-bit adder?
13. How do you identify the critical path in a synthesized design?
14. What is the power consumption consideration in a 4-bit adder?

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2.4-Bit Shift and add Multiplier

AIM: To write Verilog code for 4-Bit Shift and add Multiplier and its test bench for
verification and observe the waveform and synthesize the code.

OBJECTIVES:
The objective of this program is to design, implement, and analyze a 4-bit shift-and-add
multiplier using Verilog. The program follows a structured approach, including:
1. Designing a 4-bit Shift-and-Add Multiplier using Verilog.
2. Verifying its functionality using a testbench.
3. Synthesizing the design to generate a gate-level netlist.
4. Analyzing critical parameters such as delay, power, area, and total number of cells.

THEORY:
Binary multipliers are used for multiplication of 2 binary numbers and are used
mainly in signal processing and also in other computationally intensive applications. Shift
and add binary multiplier is a type of sequential multiplier. Sequential multipliers generate
the partial products sequentially and add each newly generated partial product to the
previously accumulated sum. Shift and add binary multiplier is a type of sequential
multiplier.

PROGRAM:

// Module Declaration

module shift_add_multiplier (
input [3:0] A, // 4-bit multiplicand
input [3:0] B, // 4-bit multiplier
output [7:0] product // 8-bit product ); // The final multiplication result (since
multiplying two 4-bit numbers can produce an 8-bit result).

reg [7:0] product_reg; // Stores the intermediate and final product result.
reg [7:0] A_reg; // Stores an extended version of A (with 4 extra bits for
shifting).
reg [7:0] B_reg; // Stores an extended version of B (same as A_reg).

integer i; // Loop variable used for iteration in the multiplication process.

// Perform multiplication using shift and add

always @(A, B) // executes whenever A or B changes.
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begin // Implements the shift-and-add multiplication algorithm.

A_reg = {4'b0000, A}; // Extend A to 8 bits (padding with zeros)

B_reg = {4'b0000, B}; // Extend B to 8 bits (padding with zeros)
product_reg = 8'b00000000; // Loop for 4 times for shift and add
for (i = 0; i < 4; i = i + 1) // The loop runs 4 times since we are multiplying
two 4-bit numbers.

begin if (B_reg[i]) begin // Checks each bit of B reg (multiplier).

product_reg = product_reg + A_reg;
end

A_reg = A_reg << 1; // The multiplicand (A_reg) is shifted left by 1 bit at

each iteration.
end
end

assign product = product_reg; // The computed product is assigned to the

output product

endmodule

TESTBENCH:
module test_shift_add_multiplier; // Declares the testbench module
// Testbench signals
reg [3:0] A; // Stores the multiplicand for testing
reg [3:0] B; // Stores the multiplier for testing
wire [7:0] product; // Captures the multiplication result from the DUT (Design
Under Test).
// Instantiate the shift-and-add multiplier
shift_add_multiplier uut ( .A(A), .B(B), .product(product) );
initial begin // start of the simulation.
// Test Case 1: 3 * 2
A = 4'b0011; // A = 3
B = 4'b0010; // B = 2
#10;

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$display("Test Case 1: A = %b, B = %b, product = %b", A, B, product);

// Test Case 2: 4 * 5
A = 4'b0100; // A = 4
B = 4'b0101; // B = 5
#10; // Waits 10 time units for the multiplication to complete
$display("Test Case 2: A = %b, B = %b, product = %b", A, B, product);
// Prints the inputs and the computed product in binary format.
// Test Case 3: 8 * 3
A = 4'b1000; // A = 8
B = 4'b0011; // B = 3
#10;
$display("Test Case 3: A = %b, B = %b, product = %b", A, B, product);
// Test Case 4: 7 * 6
A = 4'b0111; // A = 7
B = 4'b0110; // B = 6
#10;
$display("Test Case 4: A = %b, B = %b, product = %b", A, B, product);
$finish; //terminates the simulation after all test cases are executed
end
endmodule

BLOCK DIAGRAM:

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RTL SCHEMATIC DIAGRAM:

DESIGN UTILIZATION SUMMARY:

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SYNTHESIS REPORT:
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 18.627ns

MAX CLOCK FREQUENCY CALCULATION

Using delay = ns,
the max frequency is:
1
fmax= … … … … .. ns =……….. MHz
This means the Adder can operate at a maximum clock speed of ~……………….Hz

WAVEFORM:

PROCEDURE:
 Select new project and type the project name.
 Enter the device properties and click next.
 Click new source and select the Verilog module and then give the file name.
 Type the Verilog program and save it.
 Click new source and select the Verilog test fixture and then give the file name.
 Type the Verilog test bench program and save it.
 Double click the synthesize XST and check syntax.
 Double click the implement design.
 Simulate the waveform by behavioural simulation.
 Note down RTL schematic and analyse the design summary.

RESULT: Verilog code for 4-Bit Shift and add Multiplier and its test-bench for
verification are written, the waveform is observed and the code is synthesized.

OUTCOME: Students are able to

 Successful implementation and simulation of the 4-bit Shift and Add Multiplier in
Verilog code is verified using the testbench.
 Obtained the gate-level netlist and analyse the performance, power, and area
characteristics of the design.

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VIVA QUESTION:

1. What is the objective of the shift-and-add multiplier?

2. How does the shift-and-add multiplication algorithm work?
3. Why do we extend the multiplicand and multiplier to 8 bits?
4. What are the advantages of the shift-and-add multiplier?
5. What are the disadvantages of the shift-and-add multiplier?
6. What hardware components are required for this implementation?
7. Can this multiplier handle signed numbers? Why or why not?
8. How can you optimize this multiplier for speed?
9. What is the role of shift operations in this multiplier?
10. How would you modify this design to support 8-bit multiplication?

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32-Bit ALU
AIM: To write Verilog code for 32-bit ALU and its test bench for verification and observe
the waveform and synthesize the code.

OBJECTIVE: The main objective of this program is to

 Design, implement, and analyse a 32 bit ALU supporting four logical and four
arithmetic operations, use case statement and if statement for ALU behavioral
modelling
 To analyses the area and timing constraints to optimize design. Analyzing power
consumption, area utilization, and delay.

THEORY:
The ALU will take in two 32-bit values, and control line. An Arithmetic unit does the
following task like addition subtraction, multi-fiction and logical operations. As the input is
given in 32 bit we get 32 bit output. The arithmetic will show only one output at a time so a
selector is necessary to select one of the operator.

PROGRAM:

//Module Declaration

module ALU_32bit (
input [31:0] A, B, //32-bit input operands
input [2:0] ALU_Sel, // 3-bit selection signal that determines which
operation the ALU performs.
output reg [31:0] ALU_Result, //A 32-bit register that holds the result of the
selected operation.
output reg Zero //A flag that is set when the result is zero.
);
always @(*) begin //it executes whenever any of its input
case (ALU_Sel) //Case Statement for ALU Operations
3'b000: ALU_Result = A + B; // Addition If ALU_Sel is 000,
perform addition: A + B
3'b001: ALU_Result = A - B; // Subtraction
3'b010: ALU_Result = A * B; // Multiplication
3'b011: ALU_Result = A +1 ; // increment
3'b100: ALU_Result = A & B; // AND
3'b101: ALU_Result = A | B; // OR

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3'b110: ALU_Result = A ^ B; // XOR

3'b111: ALU_Result = ~A; // NOT (on A)
default: ALU_Result = 32'b0;
endcase

if (ALU_Result == 32'b0)
Zero = 1; //If ALU_Result is zero, set Zero = 1 (indicating a zero
result).
else
Zero = 0; //Otherwise, set Zero = 0
end
endmodule //Marks the end of the module definition.

TESTBENCH:

module ALU_32bit_tb; //Defines the testbench module

reg [31:0] A, B; //32-bit registers to hold the input values.
reg [2:0] ALU_Sel; //3-bit register used to select the ALU operation.
wire [31:0] ALU_Result; //32-bit wire to capture the ALU output.
wire Zero; //Wire for the zero flag

ALU_32bit uut (
.A(A),
.B(B),
.ALU_Sel(ALU_Sel),
.ALU_Result(ALU_Result),
.Zero(Zero)
); //Instantiates the ALU module

initial begin //The initial block runs once when the simulation starts.
$monitor("A = %d, B = %d, ALU_Sel = %b, ALU_Result = %d, Zero =
%b", A, B, ALU_Sel, ALU_Result, Zero); //$monitor continuously displays
signal values whenever they change.
//Test Cases
A = 32'hA5A5A5A5; B = 32'h5A5A5A5A; //Assigns initial values to A
and B.
ALU_Sel = 3'b000; #10;
ALU_Sel = 3'b001; #10;

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ALU_Sel = 3'b010; #10;

ALU_Sel = 3'b011; #10;
ALU_Sel = 3'b100; #10;
ALU_Sel = 3'b101; #10;
ALU_Sel = 3'b110; #10;
ALU_Sel = 3'b111; #10;

$finish; //Stops the simulation once all test cases run

end
endmodule

BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

Device Utilization summary:

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Synthesis Report:

MAX CLOCK FREQUENCY CALCULATION

Using delay = 23.208 ns,
the max frequency is:
1
fmax= 23.208 ns =……….. MHz
This means the ALU can operate at a maximum clock speed of ~……………….Hz

Wave form:

Procedure:
 Select new project and type the project name.
 Enter the device properties and click next.
 Click new source and select the Verilog module and then give the file name.
 Type the Verilog program and save it.
 Click new source and select the Verilog test fixture and then give the file name.
 Type the Verilog test bench program and save it.
 Double click the synthesize XST and check syntax.
 Double click the implement design.
 Simulate the waveform by behavioural simulation.
 Note down RTL schematic and analyse the design summary.

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Result: Verilog code for 32-bit ALU and its test-bench for verification are written, the
waveform is observed and the code is synthesized.

OUTCOME: Students are able to

Functional Verification (Testbench Results)
Synthesis Metrics: Area, power, and delay estimated.

VIVA QUESTION

1. What is an ALU?
2. What are the arithmetic and logical operations implemented in your ALU?
3. Why do we use always @(*) in Verilog?
4. What is the role of the case statement in your ALU?
5. What does $monitor do in your testbench?
6. What does synthesis do in Verilog?
7. What factors affect area and power in an ALU?
8. Which operation has the highest delay in your ALU and why?
9. How do you optimize power consumption in your ALU?
10. What is the critical path in your ALU?
11. How is the maximum operating frequency calculated?

12. What is the difference between behavioral and structural modeling in Verilog?

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Flip-Flop
AIM: To write Verilog code for flip-flop and its test bench for verification and observe the
waveform and synthesize the code.

OBJECTIVE: The objective of this program is to design, implement, and analyze D, SR,
and JK flip-flops using Verilog. The design will be tested at both the Register Transfer Level
(RTL) and Gate Level, ensuring correctness, performance, and optimization for synthesis.

THEORY:

Latches and flip-flops are the basic elements for storing information. One latch or flip
flop can store one bit of information. The main difference between latches and flip-flops is
that for latches, their outputs are constantly affected by their inputs as long as the enable
signal is asserted. In other words, when they are enabled, their content changes immediately
when their inputs change. Flip-flops, on the other hand, have their content change only either
at the rising or falling edge of the enable signal. This enable signal is usually the controlling
clock signal. After the rising or falling edge of the clock, the flip-flop content remains
constant even if the input changes. There are basically four main types of latches and flip-
flops: SR, D, and JK. The major differences in these flip-flop types are the number of inputs
they have and how they change state. For each type, there are also different variations that
enhance their operations.

D-Flip-flop
Program:

module d_ff(d,clk,q,q1); // Module definition

input d,clk; // the data input and clock input.
output q,q1; // the outputs
reg q,q1; //reg because they will hold values between clock cycles.
initial begin
q=1'b0;q1=1'b1; // q is initially set to 0. // q1 is initially set to 1.
end
always @(posedge clk) //The block will execute when the clock signal
transitions from 0 to 1.
begin

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q=d; //q will be updated to match the value of d

q1=~d; // The output q1 will be the inverse of d
end
endmodule

TESTBENCH:

module test; // Declaration Module

reg d,clk; // The data input and clock signal for the D flip-flop
wire q,q1; // The outputs of the D flip-flop
d_ff uut(.d(d),.clk(clk),.q(q),.q1(q1)); // the instantiates the d_ff module within
the testbench
initial
clk = 1'b0; // This block initializes the clock signal clk to 0 at the
start of the simulation
always
#100 clk = ~clk; // the clock signal (clk) will alternate between 0 and
1 every 100 time units
initial begin
d=1'b0;#200; // The signal d is set to 0 for 200 time units.
d=1'b1;#200; // The signal d is set to 1 for 200 time units.
d=1'b0;#300; // d is set to 0 for 300 time units.
d=1'b1;#400; // d is set to 1 for 400 time units.
end
initial
#2000 $finish; // This initial block ends the simulation after 2000 time unit
endmodule
BLOCK DIAGRAM:

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RTL SCHEMATIC DIAGRAM:

CLOCK REPORT:

DEVICE UTILIZATION SUMMARY:

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SYNTHESIS REPORT:

WAVEFORM:

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SR- Flip-flop
PROGRAM:

SR FLIP - FLOP

module srff(s,r,en,q,qn); // Declaration of Module

input s,r,en; // Set, reset and enable input
output q,qn; // the outputs
reg q,qn; // Declares q and qn as reg types because their values are assigned in
an always block.
initial begin // initial values of q and qn
q=1'b0; //q is initialized to 0.
qn=1'b1; // qn is initialized to 1
end
always @(posedge en) // This is triggered on the positive edge of the enable
signal
begin
case({s,r}) // case statement that checks the values of the Set and Reset inputs
{1'b0,1'b0}:begin q=q;qn=qn;end
{1'b0,1'b1}:begin q=1'b0;qn=1'b1;end
{1'b1,1'b1}:begin q=1'b1;qn=1'b0;end
{1'b1,1'b1}:begin q=1'bx;qn=1'bx;end
endcase
end
endmodule //ending the module

TESTBENCH:

module test; // defines the test module

reg s,r,clk; // inputs to the SR Flip-Flop
wire q,qn; // output of the SR Flip-Flop
srff uut(.s(s),.r(r),.clk(clk),.q(q),.qn(qn)); // This instantiates the srff module
and connects the testbench signals to the SR Flip-Flop's inputs and outputs.
initial // Clock Generation
clk=1'b1; // sets the clk signal to 1
always #100 clk=~clk; // This always block toggles the clk signal every 100
time units
initial begin // Test Stimuli for s and r
s=0;r=0;#200;
s=0;r=1;#200;

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s=1;r=0;#200;
s=1;r=1;#200;
end
initial
#2000 $finish; // This initial block ensures that the simulation finishes after
2000 time units
endmodule

BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

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CLOCK REPORT:

DEVICE UTILIZATION SUMMARY:

SYNTHESIS REPORT:

WAVEFORM:

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JK- Flip-flop
PROGRAM:

module jkff(j,k,clk,q,qn); //defines the module jkff with inputs and outputs
input j,k,clk; // input signals
output q,qn; // output signals
reg q,qn; //q and qn will store values, they are declared as register type
initial begin
q=1'b0; // It initializes q to 0.
qn=1'b1; // It initializes qn to 1
end
always @(posedge clk) // execute on the rising edge of the clock
begin
case({j,k}) // Case Statement (Defining JK Flip-Flop Behavior)
{1'b0,1'b0}:begin q=q;qn=qn;end // Case Conditions
{1'b0,1'b1}:begin q=1'b0;qn=1'b1;end
{1'b1,1'b0}:begin q=1'b1;qn=1'b0;end
{1'b1,1'b1}:begin q=~q;qn=~qn;end
endcase
end
endmodule //module ends

TESTBENCH:

module test; //defines the test module

reg j,k,clk; //Registers store values for inputs
wire q,qn; //Wires are used to receive output signals
jkff uut(.j(j),.k(k),.clk(clk),.q(q),.qn(qn)); //Instantiating the JK Flip-Flop (Unit
Under Test)
initial //Initializing Clock Signal
clk=1'b0; //Sets the initial clock value to 0.
always #100clk=~clk; //Generating Clock Signal (Toggling Every 100 Time
Units)
initial //Applying Test Inputs
begin
j=0;k=0;#200; // Apply J=0, K=0 for 200 time units (No change)
j=1;k=0;#400; //Apply J=1, K=0 for 400 time units (Set Q=1)
j=0;k=1;#600; //Apply J=0, K=1 for 600 time units (Reset Q=0)
j=1;k=1;#800; //Apply J=1, K=1 for 800 time units (Toggle Q)

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end
initial

#2000 $finish; //The simulation stops after 2000 time units

endmodule

BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

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DEVICE UTILIZATION SUMMARY:

CLOCK REPORT:

SYNTHESIS REPORT:

WAVEFORM:

PROCEDURE:
 Select new project and type the project name.
 Enter the device properties and click next.

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 Click new source and select the Verilog module and then give the file name.
 Type the Verilog program and save it.
 Click new source and select the Verilog test fixture and then give the file name.
 Type the Verilog test bench program and save it.
 Double click the synthesize XST and check syntax.
 Double click the implement design.
 Simulate the waveform by behavioural simulation.
 Note down RTL schematic and analyse the design summary.
RESULT: Verilog code for flip-flop and its test-bench for verification are written, the
waveform is observed and the code is synthesized.

OUTCOME: Students are able to

 Successfully implemented D, SR, and JK Flip-Flops in Verilog.
 Verified functionality using a testbench.
 Synthesized the design and obtained a gate-level netlist.
 Analysed critical parameters like delay, power, and area.
 Compared RTL vs Gate-Level simulation results.

VIVA QUESTION
1. What is the difference between a latch and a flip-flop?
2. Explain the working of a D Flip-Flop.
3. Why is an SR Flip-Flop not used in practical circuits?
4. How does a JK Flip-Flop overcome the limitations of the SR Flip-Flop?
5. What is the race-around condition in a JK Flip-Flop, and how is it avoided?
6. What is the difference between synchronous and asynchronous reset?
7. How can you implement a T Flip-Flop using a JK Flip-Flop?
8. How do you implement a Toggle Flip-Flop using a D Flip-Flop?
9. What happens in a JK Flip-Flop when both J and K are 1?
10. Can you design a JK Flip-Flop using a D Flip-Flop? If yes, how?

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5.Four-Bit Synchronous Mod-N Counter with

Asynchronous Reset
AIM: To write Verilog code for Four-bit Synchronous MOD-N counter with Asynchronous
reset and its test bench for verification and observe the waveform and synthesize the code.

OBJECTIVES: The objective of the programis 4-bit Synchronous MOD-N counter with
Asynchrounous reset, verify the functionality using Test bench and Synthesize the design and
compare the synthesis report.

THEORY:

MOD-N Counter Counters are sequential logic devices that follow a predetermined sequence
of counting states triggered by an external clock (CLK) signal. The number of states or
counting sequences through which a particular counter advances before returning to its
original first state is called the modulus (MOD). In other words, the modulus (or modulo) is
the number of states the counter counts and is the dividing number of the counter.

Modulus Counters, or MOD counters, are defined based on the number of states that
the counter will sequence before returning to its original value.

For example, a 2-bit counter that counts from 002 to 112 in binary, 0 to 3 in decimal,
has a modulus value of 4 ( 00 → 1 → 10 → 11, and return to 00 ); therefore, be called a
modulo-4, or mod-4, counter. Note also that it has taken four clock pulses to get from 00 to
11. In this example, there are only two bits ( n = 2 ) then the maximum number of possible
output states (maximum modulus) for the counter is 2n = 22 or 4.

However, counters can be designed to count to any 2n states in their sequence by

cascading together multiple counting stages to produce a single modulus or MOD-N counter.
Therefore, a "Mod-N" counter will require the "N" number of flip-flops connected to count a
single data bit while providing 2n different output states (n is the number of bits).

Note that N is always a whole integer value. Then we can see that MOD counters
have a modulus value that is an integral power of 2, that is, 2, 4, 8, 16 and so on to produce
an n-bit counter depending on the number o

PROGRAM:

// The module is a parameterized design, where the parameter N can be

specified at instantiation to define the counter's maximum value

module modN_counter #(parameter N = 10) (

input clk, rst, // Declares the input signals clk (clock) and rst (reset)
clk is used for counting, and rst is used for asynchronous reset.

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output reg [3:0] count); // Declares a 4-bit output register

always @(posedge clk or posedge rst) begin // this means the block
will execute whenever there is a clock edge (for counting) or a reset signal (to
reset the counter).
if (rst) // rst signal is high
count <= 0; // Asynchronously resets the count to 0
else if (count == N - 1) //
count <= 0; // the counter will be reset to 0 in the next clock
cycle.
else
count <= count + 1; // counter is incremented.
end
endmodule

TESTBENCH

module modN_counter_tb; // Defines the testbench module

reg clk, rst; // Declares clk and rst as registers
wire [3:0] count; // Declares count as a 4-bit wire that will hold the output of
the counter.

// Instantiate counter with MOD-10

modN_counter #(.N(10)) uut (
.clk(clk),
.rst(rst),
.count(count)
);

// Generate Clock (10 ns period)

always #5 clk = ~clk; // This generates a clock signal with a period of 10 ns.
Every 5 ns, the value of clk is toggled

initial begin
$dumpfile("modN_counter_tb.vcd"); // This opens a file
modN_counter_tb.vcd where waveform data will be written

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$dumpvars(0, modN_counter_tb); // This tells the simulator to dump all

signals in the testbench to the .vcd file.

clk = 0; rst = 1; // Initial state

#10 rst = 0; // Release reset
#100; // Run simulation
rst = 1; // Apply reset
#10 rst = 0; // Release reset
#50; // Run for some more cycles
$stop;
end
endmodule
BLOCK DIAGRAM:

RTL SCHEMATIC DIAGRAM:

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DEVICE UTILIZATION SUMMARY:

CLOCK REPORT:

SYNTHESIS REPORT:

WAVEFORM:

PROCEDURE:
 Select new project and type the project name.
 Enter the device properties and click next.
 Click new source and select the Verilog module and then give the file name.
 Type the Verilog program and save it.
 Click new source and select the Verilog test fixture and then give the file name.
 Type the Verilog test bench program and save it.
 Double click the synthesize XST and check syntax.
 Double click the implement design.
 Simulate the waveform by behavioural simulation.
 Note down RTL schematic and analyse the design summary.

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RESULT: Verilog code for Four-bit Synchronous MOD-N counter with Asynchronous
reset and its test-bench are written and verified, the waveform is observed and the code is
synthesized.

OUTCOME: Students are able to

 Successfully implemented a 4-bit Synchronous MOD-N Counter with Asynchronous
Reset..
 Verified functionality using a testbench.
 Synthesized the design, obtained the netlist, and extracted area, power, and timing
parameters.

VIVA QUESTIONS
1. What is a MOD-N counter?
A MOD-N counter is a counter that counts from 0 to (N-1) and then resets to 0.

2. How does a synchronous counter differ from an asynchronous counter?

3. Why do we use an asynchronous reset in a synchronous counter?
4. How do you determine the number of flip-flops required for a MOD-N counter?
5. How do you declare a 4-bit counter in Verilog?
6. What is the sensitivity list in an always block?
7. Why do we use posedge clk instead of negedge clk?
8. What is the critical path in a counter design?
The longest delay path in the circuit that determines the maximum clock speed.
9. The longest delay path in the circuit that determines the maximum clock speed.
10. How do you verify a counter’s timing constraints in synthesis?
Perform static timing analysis (STA) to check setup and hold violations.

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INTRODUCTION
Very-large-scale integration (VLSI) is the process of creating an integrated circuit
(IC) by combining thousands of transistors into a single chip. VLSI began in the 1970s when
complex semiconductor and communication technologies were being developed. The
microprocessor is a VLSI device. Before the introduction of VLSI technology most ICs had a
limited set of functions they could perform. An electronic circuit might consist of a CPU,
ROM, RAM and other glue logic. VLSI lets IC designers add all of these into one chip.

During the mid-1920s, several inventors attempted devices that were intended to
control current in solid-state diodes and convert them into triodes. Success did not come until
after World War II, during which the attempt to improve silicon and germanium crystals for
use as radar detectors led to improvements in fabrication and in the understanding of quantum
mechanical states of carriers in semiconductors.

Then scientists who had been diverted to radar development returned to solid-state
device development. With the invention of transistors at Bell Labs in 1947, the field of
electronics shifted from vacuum tubes to solid-state devices. With the small transistor at their
hands, electrical engineers of the 1950s saw the possibilities of constructing far more
advanced circuits. As the complexity of circuits grew, problems arose.

One problem was the size of the circuit. A complex circuit, like a computer, was
dependent on speed. If the components of the computer were too large or the wires
interconnecting them too long, the electric signals couldn't travel fast enough through the
circuit, thus making the computer too slow to be effective.

Jack Kilby at Texas Instruments found a solution to this problem in 1958. Kilby's idea
was to make all the components and the chip out of the same block (monolith) of
semiconductor material. Kilby presented his idea to his superiors, and was allowed to build a
test version of his circuit.

In September 1958, he had his first integrated circuit ready. Although the first
integrated circuit was crude and had some problems, the idea was ground breaking. By
making all the parts out of the same block of material and adding the metal needed to connect
them as a layer on top of it, there was no need for discrete components. No more wires and
components had to be assembling manually.

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The circuits could be made smaller, and the manufacturing process could be
automated From here, the idea of integrating all components on a single silicon wafer came
into existence, which led to development in small-scale integration (SSI) in the early 1960s,
medium-scale integration (MSI) in the late 1960s, and then large-scale integration (LSI) as
well as VLSI in the 1970s and 1980s, with tens of thousands of transistors on a single chip
(later hundreds of thousands, then millions, and now billions (109 ).

What is CMOS Technology?

CMOS technology is a predominant technology for manufacturing integrated circuits.

CMOS stands for “Complementary Metal Oxide Semiconductor”. Microprocessors, batteries,
and digital sensors among other electronic components make use of this technology due to
several key advantages. This technology uses both NMOS and PMOS to realize various logic
functions. Both N and P MOSFET channels are designed to have matching characteristics.

NMOS

N-channel MOSFET consists of an N-type source and drain diffused on a P-type

substrate. The majority carriers are electrons. When the applied voltage to the gate is high
enough, the NMOS will conduct; otherwise, it will not. Since the majority carriers (electrons)
travel faster than holes, NMOS are considered to be faster than PMOS.

PMOS

P-channel MOSFET also has a Source and Drain diffused on a substrate. The Source
is P-type while the substrate is N-type. The majority carriers are holes. PMOS will conduct
when a low voltage is applied. When a high voltage is applied to the gate, the PMOS will not
conduct.

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CMOS

Since CMOS technology uses both N-type and P-type transistors to design logic
functions, a signal which turns ON a transistor type is used to turn OFF the other transistor
type. This eliminates the need for pull-up resistors in favour of simple switches. In CMOS
logic gates N-type MOSFETs are arranged in a pull-down network between the output and
the low voltage supply rail (VSS or ground) while P-type MOSFETs are in a pull-up network
between the output and the higher-voltage rail (often V DD). Thus, the N-type MOSFET will
be ON when the P-type MOSFET is OFF, and vice-versa. For any input pattern, one of the
networks is ON and the other is OFF.

Stick Diagram:

(Write the theory related that)

Layout design rules

(Refer the text book to write theory)

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INVERTER
AIM: To simulate the schematic of the CMOS inverter, and then to perform the physical
verification for the layout of a CMOS inverter.

OBJECTIVES: The objective of this schematic designs are

 Capture the Schematic of a CMOS Inverter with Load Capacitance of 0.1 pF and set
the Widths of Inverter with different constraints.
 Set the Input Signal to a pulse with Rise Time, Fall Time of 1 ps and Pulse Width of
10 ns, Time Period of 20 ns and plot the input voltage and output voltage of the
designed Inverter.
 From the Simulation Results, compute tpHL, tpLH and tPD for all the three
geometrical settings of Width
 Tabulate the results of delay and find the best geometry for minimum delay for

Draw the layout of NOR with 𝑊𝑃/ 𝑊𝑁 = 40 20, use optimum layout methods
CMOS Inverter.

 Verify DRC and extract the parasitics

TOOLS REQUIRED:

SOFTWARE USED:
 DSCH
 Micro wind

DESCRIPTION:

The inverter is universally accepted as the most basic logic gate doing a Boolean
operation on a single input variable.

CMOS is also referred to as complementary-symmetry metal–oxide–semiconductor.

The words "complementary-symmetry" refer to the fact that the typical digital design style
with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide
semiconductor field effect transistors (MOSFETs) for logic functions. Two important
characteristics of CMOS devices are high noise immunity and low static power consumption.
Significant power is only drawn in the transistors in the CMOS device are switching between
on and off states.

The NMOS transistor and the PMOS transistor form a typical complementary MOS
(CMOS) device. When a low voltage (0 V) is applied at the input, the top transistor (P-type)

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is conducting (switch closed) while the bottom transistor behaves like an open circuit.
Therefore, the supply voltage (5 V) appears at the output. Conversely, when a high voltage (5
V) is applied at the input, the bottom transistor (N-type) is conducting (switch closed) while
the top transistor behaves like an open circuit. Hence, the output voltage is low (0 V)

PROCEDURE:

i) Schematic (DSCH)
 Open the DSCH software.
 Click on Select foundry and select CMOS45nm technology.
 Drag the components like pmos, nmos, voltage source, ground, and LED from
the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & run the simulation.
 Select generate spice file and run win spice
ii) Layout(Micro wind)
 Double click on micro wind icon and go to file new.
 Click on Select foundry and select CMOS45nm technology.
 Draw the layout by using components from palette.
 Go to the file, save as and type the file name
 Run simulation and analysis waveform.
OBSERVATION:

SPECIFICATIONS:

PMOS: W=1u, L=0.05u

NMOS: Case i) Wn=Wp; W=1u, L=0.05u

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Case ii) Wn=2Wp; W=2u, L=0.05u

Case iii) Wn=Wp/2; W=0.5u, L=0.05u

DC Parameters:
Values (V): 1.0
Pulse parameters: TD (ns) =1, TR (ns) =1, TF (ns) =1

PW (ns) =10, Period (ns) =20

Load Capacitance: 0.1pF

SCHEMATIC DIAGRAM:

Fig: schematic diagram of inverter gate

CALCULATIONS:
Case (i): Wn=Wp;

tPLH=………, tPHL=………,

TD= (tPLH+ tPHL)/ 2=………….

Case (ii): Wn=2Wp;

tPLH=………, tPHL=………,

TD= (tPLH+ tPHL)/ 2=………….

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Case (iii): Wn=Wp /2;

tPLH=………, tPHL=………,

TD= (tPLH+ tPHL)/ 2=………….

Width TPLH TtPHL TD

Case (i): Wn=Wp;

Case (ii): Wn=2Wp;

Case (iii): Wn=4Wp;

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LAYOUT:
PMOS: W=800nm, L=40nm
NMOS: W=400nm, L=40nm

Fig: layout diagram of inverter gate

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LAYOUT OUTPUT WAVEFORM:

VOLTAGE VERSUS VOLTAGE OUTPUT WAVEFORM:

SPECIFICATIONS:

Clock: time low=2 , rise time=0.010, time high=2, fall time=0.010

Load Capacitance: 0.1pF

RESULTS: The schematic and layout for the inverter is drawn and verified.

OUTCOME: Students are able to

 Analysis of pre-layout and post-layout simulations.
 Highlighting the effectiveness of design and layout methodologies in
optimizing the performance of CMOS inverters.

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VIVA QUESTIONS:
1. Why do we use Wp > Wn in inverter design?
2. What causes delay in CMOS inverter?
3. Why do post-layout simulations differ from pre-layout?
4. How does increasing W affect performance?
5. What is the impact of load capacitance?
6. What is a CMOS inverter?
7. Explain the operation of a CMOS inverter.
8. Why is CMOS preferred over NMOS or PMOS logic?
9. What happens when input is at VDD? What about 0V?
10. Define tpHL and tpLH.
11. What is propagation delay and how is it measured?
12. What is logical effort?
13. How does transistor sizing affect delay and power?
14. How do you generate an input pulse in simulation?
15. How do you calculate delay from the simulation waveform?
16. What tools did you use for schematic and simulation?
17. Why is transient analysis important in CMOS simulation?
18. What is stick diagram and why is it useful?
19. What is the significance of λ in layout design?
20. What are design rules and why are they important?
21. What are DRC and LVS? Why are they done?
22. How do you design an inverter to drive large capacitive loads?

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CMOS NOR GATE

AIM: To simulate the schematic of the CMOS 2 input NOR gate, and then to perform the
physical verification for the layout of an the CMOS 2 input NOR gate.

OBJECTIVES: The objective of this schematic designs are

 Design a 2-input CMOS NOR gate.

 Match its delay to the CMOS inverter from previous experiments.
 Verify logic functionality for all 4 input combinations.
 Measure and tabulate propagation delay td.

Draw the layout of NOR with 𝑊𝑃/ 𝑊𝑁 = 40 20, use optimum layout methods
 Increase drive strength to 2× and 4×, and compare delays

 Verify DRC and extract the parasitics


TOOLS REQUIRED:
SOFTWARE USED:
 DSCH
 Micro wind

DESCRIPTION:
In digital electronics, NAND and NOR gates are two universal logic gates that are
used to perform Boolean operations on multiple input variables. These gates produce an
output based on the combination of inputs applied.

NAND and NOR gates are used as the fundamental building blocks in the digital
circuits and systems. We can design and implement the NAND and NOR gates in different
technologies such as DTL, RTL, TTL, and CMOS. This chapter deals with implementation of
NAND and NOR gates using CMOS technology.

The block diagram of a 2-input NOR logic gate in CMOS technology is shown in the
following figure. It consists of two parallel NMOS transistors between Y(output) and Ground
and two series PMOS transistors between Y (output) and VDD.
The NOR gate is a universal logic gate in digital electronics. It is a combination of
two basic logic gates namely, NOT gate and OR gate, where it is realized by connecting a
NOT gate to the output of the OR gate. Therefore,

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The output of the NOR gate is high or logic 1, when all its inputs are low or logic 0.
For all other input combinations, the output of the NOR gate is low or logic 0.

PROCEDURE:

i) Schematic (DSCH)
 Open the DSCH software.
 Click file tab then open select foundry and select CMOS 45nm technology.
 Construct the schematic circuit by dragging the components from like pmos,
nmos, voltage source, ground, and LED from the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & go to file ,Select generate spice file and run winspice
 The waveform window will open now calculate the delay for 3 constraints.
ii) Layout(Micro wind)
 Double click on micro wind icon and go to file new.
 Click on Select foundry and select CMOS45nm technology.
 Draw the layout by using components from palette.
 Go to the file, save as and type the file name
 Run simulation and analysis waveform.

CMOS NAND GATE:

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Figure: Circuit diagram, symbol and truth table of 2-input NOR gate

SCHEMATIC DIAGRAM:

Fig: schematic diagram of 2-input NOR gate

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SPECIFICATIONS:

PMOS: Wp=0.4u, L=0.05u

NMOS: Case i) Wn=Wp; Wn=0.4u, L=0.05u

Case ii) Wn=2Wp; Wn=0.8u, L=0.05u

Case iii) Wn=4Wp; Wn=1.6u, L=0.05u

DC Parameters:
Values (V): 1.0
Pulse parameters: TD (ns) =1, TR (ns) =1, TF (ns) =1

PW (ns) =10, Period (ns) =20

Load Capacitance: 0.1pF

CALCULATIONS:
Case (i): Wn=Wp; 0.4u

tPLH=………, tPHL=………,

TD= (tPLH+ tPHL)/ 2=………….

Case (ii): Wn=2Wp; 0.8u

tPLH=………, tPHL=………,

TD= (tPLH+ tPHL)/ 2=………….

Case (iii): Wn=4Wp; 1.6u

tPLH=………, tPHL=………,

TD= (tPLH+ tPHL)/ 2=………….

Width TPLH TtPHL TD

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Case (i): Wn=Wp;

Case (ii): Wn=2Wp;

Case (iii): Wn=4Wp;

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LAYOUT:
PMOS: W=800nm, L=40nm
NMOS: W=400nm, L=40nm
Number of Fingers: 2

Fig: layout diagram of 2-input NOR gate

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Layout output waveform:

SPECIFICATIONS:

Clock 1: time low=1 , rise time=0.010, time high=12, fall time=0.010

Clock 2: time low=2 , rise time=0.010, time high=2, fall time=0.010

Load Capacitance: 0.1pF

RESULTS: The schematic and layout for the CMOS 2-input NOR gate is drawn and
verified.

Outcome: Students are able to

 Analysis of pre-layout and post-layout simulations.
 Highlighting the effectiveness of design and layout methodologies in
optimizing the performance of CMOS NOR gate.

VIVA QUESTIONS:

1. Why does NOR gate have higher delay than an inverter?

2. Why do we increase PMOS width in NOR gate?
3. How does drive strength affect delay?
4. Why are PMOS transistors in series and NMOS transistors in parallel in a NOR gate?
5. What is the impact of fan-in on the delay of a NOR gate?
6. How is the NOR gate different from the NAND gate in terms of structure and speed?
7. What logic levels at A and B will result in a transition from low to high at the output?
8. Define tpHL and tpLH for a NOR gate.
9. What types of power dissipation occur in a NOR gate?

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10. Which factors contribute to dynamic power in NOR gate switching?

11. How is the layout of a 2-input NOR gate different from that of an inverter?
12. Can you implement an XOR gate using only NOR gates? How?
13. Which factors contribute to dynamic power in NOR gate switching?
14. Which transition (0 → 1 or 1 → 0) is typically slower in a NOR gate? Why?

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COMMON SOURCE AMPLIFIER

AIM: To simulate the schematic and to draw the layout of the common source amplifier.

OBJECTIVES: The objective of this schematic designs are

 Design a CS amplifier with a PMOS current mirror as active load.
 Measure transient response to a step or small signal input.
 Analyze AC response to find:
 Gain (Amplification Factor)
 3dB bandwidth
 Unit Gain Bandwidth (UGB)
 Vary transistor widths (W) and study impact on gain and UGB.
 Understand trade-offs between speed (bandwidth) and gain
 Draw the layout of CS amplifier use optimum layout methods.
 Verify DRC and extract the parasitics
TOOLS REQUIRED:
SOFTWARE USED:
 DSCH
 Micro wind

DESCRIPTION:

When the input signal is applied at the gate terminal and source terminal, then the
output voltage is amplified and obtained across the resistor at the load in the drain terminal.
This is called a common source amplifier. Here source acts as a common terminal between
the input and output. It produces current gain and voltage gain according to the input
impedance and output Impedance. To produce voltage gain along with high input impedances
FET’s are used in these circuits.

In electronics, a common-source amplifier is one of three basic single-stage field-

effect transistor (FET) amplifier topologies,. The easiest way to tell if a FET is common
source, common drain, or common gate is to examine where the signal enters and leaves. The
remaining terminal is what is known as "common". In this example, the signal enters the gate,
and exits the drain. The only terminal remaining is the source. This is a common-source FET
circuit. The analogous bipolar junction transistor circuit may be viewed as a transconductance
amplifier or as a voltage amplifier.. As a transconductance amplifier, the input voltage is seen
as modulating the current going to the load.

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As a voltage amplifier, input voltage modulates the current flowing through the FET,
changing the voltage across the output resistance according to Ohm's law. However, the FET
device's output resistance typically is not high enough for a reasonable transconductance
amplifier (ideally infinite), nor low enough for a decent voltage amplifier (ideally zero).
Another major drawback is the amplifier's limited high-frequency response. Therefore, in
practice the output often is routed through either a voltage follower (common-drain or CD
stage), or a current follower (common-gate or CG stage), to obtain more favorable output and
frequency characteristics. The CS–CG combination is called a cascode amplifier.

PROCEDURE:

i) Schematic (DSCH)
 Open the DSCH software.
 Click file tab then open select foundry and select CMOS 90nm technology.
 Construct the schematic circuit by dragging the components from like pmos,
nmos, voltage source, ground, and LED from the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & go to file ,Select generate spice file and run winspice
 The waveform window will open now calculate the gain.
iii) Layout(Micro wind)
 Double click on micro wind icon and go to file new.
 Click on Select foundry and select CMOS 90nm technology.
 Draw the layout by using components from palette.
 Go to the file, save as and type the file name
 Run simulation and analysis the waveform.

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SCHEMATIC DIAGRAM:

Fig: schematic diagram of common source amplifier

SPECIFICATIONS:

PMOS: Wp=5.0u, L=0.10u

NMOS: Wn=5.0u, L=0.10u

i) Voltage source: Simple

DC Parameters:
Values (V): 0.6
ii)Voltage source:
DC Parameters:
Values (V): 1.2
Sinus parameters: VO (V) =0.6 Va (V) =0.1
TD (ns) =0.0 Theta=0.0
Case i) frequency (MHz) =500
Case ii) frequency (MHz) =4000

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Case iii) frequency (MHz) =10000

Load Capacitance: 0.05 pF

Output waveform Observation
i) Transient Response: ii) AC Response:
Analysis: Transient Analysis: AC
Frequency/Time: Frequency/Time:
From 1ns to 100ns From 200MHz to 10GHz
Plot: Linear ` Plot: dB

Gain Calculation
i) Transient Analysis: ii) AC Analysis:
Input: …………… (GHz)
Output:
Output
Gain: =
Input

i) Transient Analysis waveform:

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AC Response:

LAYOUT DIAGRAM:
PMOS: W=1000nm, L=40nm
NMOS: W=1000nm, L=40nm
Number of Fingers: 5

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Fig: layout diagram of common source amplifier

SPECIFICATIONS:
i)Add a Sinus ii) Add VDD supply

Label name: Vin label name: Vbias

Amplitude (V): 0.1 Dc voltage level (V): 0.600
Frequency (MHz): 500.000 Select VDD2/2= 0.600V
Offset (V): 0.542
Increase frequency: Case i): 0.000
Case ii): 2
Layout output waveform:

Voltage versus voltage output waveform:

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RESULTS:

 The schematic and layout for the common source amplifier is drawn and verified.
 The gain of the common source amplifier is……….

OUTCOME: Students are able to

 Analysis of pre-layout and post-layout simulations.
 Highlighting the effectiveness of design and layout methodologies in
optimizing the performance of common source amplifier.

VIVA QUESTION
1. What is a common source amplifier?
2. Why do we use a PMOS current mirror as load?
3. What is the role of the bias current source?
4. How does the gain of the CS amplifier depend on gm and ro?
5. What is the small-signal gain expression?
6. What is unit gain bandwidth (UGB)?
7. How do you find UGB from AC plot?
8. Why does gain increase but UGB decrease with higher width?
9. How does a PMOS current mirror work?
10. What is the advantage of active load over resistive load?
11. What layout techniques help minimize mismatch in analog circuits?
12. What are parasitics, and how do they affect frequency response?
13. What are the effects of layout parasitics on UGB?
14. What checks do you perform in layout?
15. Why does gain reduce in post-layout simulation?
16. What trade-offs exist between gain and bandwidth?
17. How does increasing transistor width affect UGB and gain?

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8. Construct the schematic using Boolean Expression using

CMOS-Logic (Y = AB+CD+E)’
AIM: To simplify and analyse the Boolean function (Y = AB+CD+E)’and verify the
functionality of the expression.

Objective: The main objective of this

 To simplify and analyze the Boolean function

 To measure and tabulate the propagation delay for selected input transitions.
 To understand the working principles of static CMOS logic and its delay behavior
with logic gates.

TOOLS REQUIRED:
SOFTWARE USED:
 DSCH

DESCRIPTION:

The pull up and pull down network consist of combination of transistor,where two or
more transistors in series are ON only if all of the series transistors are ON. Two or more
transistors in parallel are ON if any of the parallel transistors are ON. By using combinations
of these constructions, CMOS combinational gates can be constructed.When both pull-up and
pull-down are OFF, the high impedance or floating Z output state results. This is of
importance in multiplexers, memory elements, and tristate bus drivers. The crowbarred (or
contention) X level exists when both pull-up and pull-down are simultaneously turned ON.
Contention between the two networks results in an indeterminate output level and dissipates
static power. It is usually an unwanted condition

PROCEDURE:

Schematic (DSCH)
 Open the DSCH software.
 Click file tab then open select foundry and select CMOS 90nm technology.
 Construct the schematic circuit by dragging the components from like pmos,
nmos, voltage source, ground, and LED from the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & go to file ,Select generate spice file and run winspice

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 The waveform window will open now calculate the gain.

SCHEMATIC DIAGRAM:

OBSERVATIONS:

SPECIFICATIONS:

i) Voltage source: Simple

DC Parameters:
Values (V): 0.6

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WAVEFORMS:

RESULTS: The schematic for Boolean expression is drawn and verified.

OUTCOMES: Students are able to

 Learned how to implement a multi-input logic function using CMOS
gates.
 Understood series vs parallel transistor effects on delay.
 Gained practical experience in simulation and waveform analysis.

VIVA QUESTIONS
1. How do you implement SOP expressions in CMOS?
2. Why do we use DeMorgan’s law in CMOS logic design?
3. Why can't we implement SOP directly in CMOS?
4. What is the advantage of using NAND or NOR logic in CMOS?
5. What’s the difference between pull-up and pull-down networks?
6. Why are PMOS used in the pull-up and NMOS in pull-down?
7. How does logic gate depth affect delay?
8. What is the worst-case delay scenario in this circuit?
9. What is propagation delay (td)?
10. How do tpHL and tpLH differ in multi-level CMOS logic?
11. How does series connection of NMOS or PMOS affect delay?
12. How do you reduce delay in CMOS circuits?
13. Would increasing transistor widths always reduce delay? What are the trade-offs?
14. What is logical effort and how does it apply here?
15. What layout factors affect delay in such CMOS circuits?
16. What are parasitic capacitances, and how do they arise in layout?

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OPERATIONAL AMPLIFER
AIM: To simulate the schematic of the two stage Operational Amplifier.

OBJECTIVES: The objective of this schematic designs are

 Design a two-stage CMOS op-amp.
 Measure:Unity Gain Bandwidth (UGB)
 Simulate in inverting and non-inverting configurations to verify amplification.

TOOLS REQUIRED:
SOFTWARE USED:
 DSCH

DESCRIPTION:

An operational amplifier (op-amp) is a direct coupled, high gain, differential

amplifier. It is an integral part of many analog and mixed-signal systems. The input stage
consists of a differential amplifier which provides high CMRR, high input impedance and
high voltage gain. The second stage is a gain stage which further increases the gain. Gain
stage is a common source amplifier. It consists of inverting input and non-inverting input
with an output which is amplified version of difference in the inputs. It is a single supply op-
amp, whose main advantage is reduced power. However the output voltage swing reduces
compared to dual supply op-amp and lies between positive supply and ground. Op-amp
characteristics are high open loop gain (ideally infinity), high Bandwidth (ideally infinity),
high input impedance (ideally infinity), low output impedance (ideally zero), high CMRR
(ideally infinity) and high PSRR (ideally infinity). Op-amp has wide range of applications
ranging from filtering, dc bias generation, and amplification and data conversion. General
purpose applications include addition, subtraction, integration, differentiation, buffering and
inversion.

With the advancement in VLSI technology Digital Signal Processing has become
more reliable and popular in almost all electronic applications. Digital systems have
enormous advantages over analog systems like accuracy, speed, immunity to noise etc. Since
all natural signals are Analog, we need an Analog to Digital Converter (ADC) to convert
analog data into digital form. Then the digital data is processed using Digital Signal

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Processor and finally the processed data is converted back to analog, using Digital to Analog
Converter (DAC). DAC is an integral part of Digital Communication Systems for Data
Conversion. DAC converts digital data into analog signal (usually current, voltage or electric
charge). CSDAC is the preferred data converter, considering High Speed applications and
High Power efficiency, over other DAC architectures. The CSDAC is designed ensuring that
it provides acceptable accuracy and moderate power consumption. DACs are used in wide
range of applications like Calibration Systems, Display Electronics, Data Acquisition
Systems, Software radio, Data Distribution Systems, audio applications, communication and
information systems etc. The suitability of various DAC in an application is decided based on
various measurements including speed, area, power, resolution, output range, power supply
requirement etc.

PROCEDURE:

i) Schematic (DSCH)
 Open the DSCH software.
 Click file tab then open select foundry and select CMOS 90nm technology.
 Construct the schematic circuit by dragging the components from like pmos,
nmos, voltage source, ground, and LED from the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & go to file ,Select generate spice file and run winspice
 The waveform window will open now calculate the gain.

OBSERVATION:

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SCHEMATIC DIAGRAM:

SPECIFICATIONS:

i) Voltage source: Simple

DC Parameters:
Values (V): 0.6
ii)Voltage source:
DC Parameters:
Values (V): 0.6
Sinus parameters: VO (V) =0.6 Va (V) =0.05
TD (ns) =0.0 Theta=0.0
Case i) frequency (MHz) =400
Case ii) frequency (MHz) =4000
Case iii) frequency (MHz) =10000

Load Capacitance: 0.05 pF

Output waveform Observation
i) Transient Response: ii) AC Response:
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Analysis: Transient Analysis: AC

Frequency/Time: Frequency/Time:
From 1ns to 100ns From 1MHz to 5GHz
Plot: Linear ` Plot: dB

Gain Calculation
i) Transient Analysis: ii) AC Analysis:
Input: …………… (GHz)
Output:
Output
Gain: =
Input

Transient Analysis Waveform:

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AC Analysis Waveform:

RESULTS: The schematic for the operational amplifier is drawn and verified the
following transient analysis and AC analysis.
OUTCOME: Students are able to
 Analysis of pre-layout simulations.
 Highlighting the effectiveness of design methodologies in optimizing the
performance of operational amplifier.

VIVA QUESTIONS

1. What are the two stages in a two-stage op-amp?

2. Why is compensation needed in multi-stage op-amps?
3. What is Miller compensation? How does it work?
4. What causes instability in op-amps?
5. What are poles and zeros in op-amp frequency response?
6. How do you measure phase margin and gain margin?
7. What is Unity Gain Bandwidth (UGB)?
8. How does Cc affect the phase margin and UGB?
9. How is 3dB bandwidth measured?
10. Why does increasing transistor width reduce UGB?
11. What is the role of the differential pair in the op-amp?
12. Why is a current mirror used as load?
13. What’s the difference between inverting and non-inverting configurations?
14. What is the open-loop vs closed-loop configuration?
15. How do power and performance trade off in op-amp design?
16. How do you ensure matching in the input pair?
17. What happens to gain and phase margin in post-layout simulations?
18. How do layout parasitics affect UGB?
19. What is common-mode rejection ratio (CMRR)?
20. What is slew rate, and how is it related to compensation capacitor?

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UART
AIM: To write Verilog code for UART and its test bench for verification and observe the
waveform and synthesize the code.

OBJECTIVES: The objective of this program is to design, implement, verify, and analyse
UART to ensure
 Write a Verilog RTL code to implement a simple UART transmitter and/or receiver.
 Verify functionality using a testbench
 Synthesize the design targeting a suitable technology library
 Analyze post-synthesis reports for Area ,Timing and Power.

PROGRAM:

module uart (
reset ,
txclk ,
ld_tx_data ,
tx_data ,
tx_enable ,
tx_out ,
tx_empty ,
rxclk ,
uld_rx_data ,
rx_data ,
rx_enable ,
rx_in ,
rx_empty
);
// Port declarations
input reset ;
input txclk ;
input ld_tx_data ;
input [7:0] tx_data ;
input tx_enable ;
output tx_out ;
output tx_empty ;
input rxclk ;
input uld_rx_data ;

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output [7:0] rx_data ;

input rx_enable ;
input rx_in ;
output rx_empty ;

// Internal Variables
reg [7:0] tx_reg ;
reg tx_empty ;
reg tx_over_run ;
reg [3:0] tx_cnt ;
reg tx_out ;
reg [7:0] rx_reg ;
reg [7:0] rx_data ;
reg [3:0] rx_sample_cnt ;
reg [3:0] rx_cnt ;
reg rx_frame_err ;
reg rx_over_run ;
reg rx_empty ;
reg rx_d1 ;
reg rx_d2 ;
reg rx_busy ;

// UART RX Logic
always @ (posedge rxclk or posedge reset)
if (reset) begin
rx_reg <= 0;
rx_data <= 0;
rx_sample_cnt <= 0;
rx_cnt <= 0;
rx_frame_err <= 0;
rx_over_run <= 0;
rx_empty <= 1;
rx_d1 <= 1;
rx_d2 <= 1;
rx_busy <= 0;
end else begin
// Synchronize the asynch signal

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rx_d1 <= rx_in;

rx_d2 <= rx_d1;
// Uload the rx data
if (uld_rx_data) begin
rx_data <= rx_reg;
rx_empty <= 1;
end
// Receive data only when rx is enabled
if (rx_enable) begin
// Check if just received start of frame
if (!rx_busy && !rx_d2) begin
rx_busy <= 1;
rx_sample_cnt <= 1;
rx_cnt <= 0;
end
// Start of frame detected, Proceed with rest of data
if (rx_busy) begin
rx_sample_cnt <= rx_sample_cnt + 1;
// Logic to sample at middle of data
if (rx_sample_cnt == 7) begin
if ((rx_d2 == 1) && (rx_cnt == 0)) begin
rx_busy <= 0;
end else begin
rx_cnt <= rx_cnt + 1;
// Start storing the rx data
if (rx_cnt > 0 && rx_cnt < 9) begin
rx_reg[rx_cnt - 1] <= rx_d2;
end
if (rx_cnt == 9) begin
rx_busy <= 0;
// Check if End of frame received correctly
if (rx_d2 == 0) begin
rx_frame_err <= 1;
end else begin
rx_empty <= 0;
rx_frame_err <= 0;
// Check if last rx data was not unloaded,

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rx_over_run <= (rx_empty) ? 0 : 1;

end
end
end
end
end
end
if (!rx_enable) begin
rx_busy <= 0;
end
end

// UART TX Logic
always @ (posedge txclk or posedge reset)
if (reset) begin
tx_reg <= 0;
tx_empty <= 1;
tx_over_run <= 0;
tx_out <= 1;
tx_cnt <= 0;
end else begin
if (ld_tx_data) begin
if (!tx_empty) begin
tx_over_run <= 0;
end else begin
tx_reg <= tx_data;
tx_empty <= 0;
end
end
if (tx_enable && !tx_empty) begin
tx_cnt <= tx_cnt + 1;
if (tx_cnt == 0) begin
tx_out <= 0;
end
if (tx_cnt > 0 && tx_cnt < 9) begin
tx_out <= tx_reg[tx_cnt -1];
end

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if (tx_cnt == 9) begin
tx_out <= 1;
tx_cnt <= 0;
tx_empty <= 1;
end
end
if (!tx_enable) begin
tx_cnt <= 0;
end
end
endmodule

Testbench:
module UART_testbench();
reg txclk, reset,tx_enable,ld_tx_data,rxclk,rx_enable;
wire tx_out,tx_empty,rx_in,rx_empty;
reg[7:0] tx_data;
wire[7:0] rx_data;
wire uld_rx_data;
uart U1 (
.reset(reset),
.txclk(txclk),
.ld_tx_data(ld_tx_data),
.tx_data(tx_data),
.tx_enable(tx_enable),
.tx_out(tx_out),
.tx_empty(tx_empty),
.rxclk(rxclk),
.uld_rx_data(uld_rx_data),
.rx_data(rx_data),
.rx_enable(rx_enable),
.rx_in(rx_in),
.rx_empty(rx_empty)
);

assign rx_in=tx_out;

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assign uld_rx_data=~rx_empty;

always@(reset,tx_empty)
begin
if(reset) begin
tx_data=170;
end
else if (tx_empty) begin
tx_data=tx_data+10;
end

end

initial begin
txclk=0;
forever #32 txclk=~txclk;
end

initial begin
rxclk=0;
forever #2 rxclk=~rxclk;
end

initial begin
reset=0;
ld_tx_data=0;
tx_enable=0;
rx_enable=0;
tx_data=170;
#10;
reset=1;
#20;
reset=0;

#50;
tx_enable=1;
rx_enable=1;

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#50;
ld_tx_data=1;
#400;
end
endmodule
Block Diagram:

DEVICE UTILIZATION SUMMARY:

TIMING CONSTRAINTS:
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CLOCK REPORT:

SYNTHESIS REPORT:

WAVE FORM:

PROCEDURE:

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 Select new project and type the project name.

 Enter the device properties and click next.
 Click new source and select the Verilog module and then give the file name.
 Type the Verilog program and save it.
 Click new source and select the Verilog test fixture and then give the file name.
 Type the Verilog test bench program and save it.
 Double click the synthesize XST and check syntax.
 Double click the implement design.
 Simulate the waveform by behavioural simulation.
 Note down RTL schematic and analyse the design summary.

RESULT: Verilog code for UART and its test-bench for verification are written, the
waveform is observed and the code is synthesized.

OUTCOME: Students are able to

 Analysis the functionality of the counter is verified through simulation,
ensuring that it increments or decrements correctly based on the up/down
control signal and resets appropriately.
 Analysis the waveform generated during simulation is analysed to confirm that
the counter behaves as expected.
 The synthesized netlist is analysed for timing performance, area utilization,
and any other relevant metrics.

VIVA QUESTIONS:
1. What is UART and where is it used?
2. What is the format of a UART frame?
3. How does UART differ from SPI or I2C?
4. Why is a state machine used in UART?
5. How do you generate baud rate in Verilog?
6. What is the role of CLK_PER_BIT in your design?
7. Why do we need a start and stop bit?
8. What are the key components of a testbench?
9. How do you verify correctness of UART using simulation?
10. How do you check if the transmitted data matches the expected sequence?
11. What is logic synthesis?
12. What does setting a clock constraint do?
13. What is area constraint, and why do we apply it?
14. What is slack in timing analysis?
15. What happens if your design violates timing constraints?

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Implementation of 6T-SRAM
AIM: To simulate the Schematic Capture of 1-bit 6T -SRAM and Creating Layout of Bit-
Cell Using microwind 3.8

OBJECTIVES: the students are able to

 Design and simulate a 6T SRAM cell using CMOS technology.
 Measure critical performance parameters: Read time, Write time, Static Noise Margin
(SNM), Power consumption

TOOLS REQUIRED:
SOFTWARE USED:
 DSCH
 Micro wind

DESCRIPTION:

6T static random-access memory is a type of semiconductor memory that uses

bistable latching circuitry to store each bit. The term static differentiates it from dynamic
RAM which must be periodically refreshed. SRAM exhibits data remembrance, but is still
volatile in conventional sense, that data is eventually lost when memory is not powered.

The nMOS access transistors (5 and 6) located at the ends of circuit and a pair of
cross-coupled inverters constitute memory cell. The nMOS elements (1and 2) of the latch are
the driver transistors, while pMOS (3 and 4) are the pull-up transistors. The access transistors
operate when the word line is raised, for read or write operation, connecting the cell to the bit
lines.

PROCEDURE:

i) Schematic (DSCH)
 Open the DSCH software.
 Click file tab then open select foundry and select CMOS 90nm technology.
 Construct the schematic circuit by dragging the components from like pmos,
nmos, voltage source, ground, and LED from the symbol library.
 Connect the circuit as in the circuit diagram.
 Save the circuit & go to file ,Select generate spice file and run winspice
 The waveform window will open now calculate the gain.

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SCHEMATIC DIAGRAM:

Fig: schematic diagram of 1-bit 6T -SRAM

SPECIFICATIONS:

PMOS: Wp=2.0u, L=0.12u

NMOS: Wn=1.0u, L=0.12u

WAVEFORM FOR WRITE AND READ OPERATIONS:

Fig:Read Operations

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Fig: Write Operations

RESULTS: The schematic of 1bit 6T SRAM is drawn and verified.

OUTCOME: Students are able to

Read time , write time and SNM are evaluated

VIVA QUESTIONS

1. What is the significance of SNM in SRAM design?

2. Why are access transistors important in an SRAM cell?
3. What is the role of the two cross-coupled inverters in a 6T SRAM cell?
4. Why are access transistors (M3 and M4) required in the 6T SRAM cell?
5. What is the advantage of using a 6T SRAM cell over a 4T SRAM cell?
6. How does the supply voltage (Vdd) impact the performance of an SRAM cell?
7. What is the concept of bit-line swing in SRAM?
8. What is the relationship between the transistor sizing and the read/write time in SRAM?
9. What is the significance of static power consumption in SRAM cells?
10. How do you calculate dynamic power consumption in SRAM?

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