EEE411

Finite State Machine

1
Time flows continuously

time

2
We cut time into slices

time

3
Time slices are strictly ordered

i—2 i—1 i i+1 i+2

time

4
 Clock signal

i—2 i—1 i i+1 i+2

time

1
0

We use the clock signal (“clk”) in order to advance

time from slice to slice.
5
 Rising clock edge

i—2 i—1 i i+1 i+2

time

1
0

With rising clock edges we define the transition

between neighboring time slices.
The negative clock edges have no importance.
6
 Clock period

i—2 i—1 i i+1 i+2

time

1
0

clock
period
We call the time between two rising clock
edges also “clock period”.
Most often, clock periods have the same
length. But this is not necessarily the case. 10
Synchronous
finite state machine FSM
(= automaton)
clk

A synchronous FSM is clocked by a clock signal (“clk”).

In each clock period, the machine is in a defined (current)
state. With each rising edge of the clock signal, the machine
advances to a defined next state.

We are interested in “finite state machines” (FSMs).

FSMs have only a finite number of states.

8
The sequence of
states can be
defined in a
state diagram.

9
State diagram:
A

We denote the C
states with B
circles and give
them symbolic
names,
e.g. A, B, and C. 10
State diagram:
A

C
B
We define one of
the states as the
initial state.
11
 In the beginning…

A
time

1
0

initial period

Initially, i.e. shortly after switching on the FSM and before the
first rising edge of clock, there is the initial period. In this period,
15
State diagram: A

B
With arrows we
define the sequence
of states.
13
The sequence of
A
states can also
be defined in a
state transition
table. C

current next B
state state
A B
B C
C A
14
 Timing diagram
time

1
clk
0
state A B C A B C

Initially, the FSM is in the initial state A.

With every positive clock edge, the next

state becomes the current state.

An FSM has always a next state.

18
 A
In order to technically realize
(“implement”) a state
C
diagram,
we start by giving B

each state
a unique number.
 A
Popular
state-encoding schemes C

• Binary encoding
– needs minimum amount of flip-flops.

• One-hot encoding
– Tends to have a simpler next-state logic.

20
 00

10

Binary encoding 01

state number
A 00
B 01
C 10
21
 00

10
Binary encoding: 01
The state transition table
has also only binary numbers.
current next
state state
00 01
01 10
10 00
 00
We also enter the unused
combination “11”. 10

This state does not exist. 01

“x” stands for “Don’t

care”.
current next
state state
00 01
01 10
10 00
11 xx
 00

We define names for 10

the two state bits, e.g. 01
s1, s0.

current next
s1 s0 s1 s0
0 0 0 1
0 1 1 0
1 0 0 0
1 1 x x
Each state bit is stored in a flipflop

flipflop stored value

22
A flipflop stores a new value, when a
rising edge occurs on the clock input

flipflop stored value

clock

23
The flipflop stores the value, which it
sees on its input.

input flipflop stored value

clock

24
Summary: A D-flip-flop samples its input
value D and stores this value when
a rising edge of clk occurs

input D Q stored value

clk

Thus, a D-type flipflop can be seen as a 1-bit photo came2r9

 In our example, we need 2 flip-flops
for storing the state bits.

next s0 Q0 s0
D0
next s1 D1 Q1 s1

clk
Flipflops which can store several bits
are also called “registers”. 30
We use the state transition table as a
“lookup table”…

current next next s0

s1 s0 s1 Q0 s0
next s1 D0
s1
0 0 0 s0
1 D1 Q1
0 1 1 0
1 0 0 0
1 1 x x clk

27
…and thus find out the next
state
current next
s1 s0 s1 D0 Q0 s0
s1
0 0 0 s0
1 D1 Q1
0 1 1 0
1 0 0 0
1 1 x x clk

28
At each positive edge of clk, the next
state gets stored as the current
state.
current next
s1 s0 s1 D0 Q0 s0
s1
0 0 0 s0
1 D1 Q1
0 1 1 0
1 0 0 0
1 1 x x clk

29
In order to get the initial state “00”, we use flipflops
with an “asynchronous reset input”. Shortly after
switching on the circuit, we apply “areset”.

current next
s1 s0 s1 D0 Q0 s0
s1
0 0 0 s0
1 D1 Q1
0 1 1 0
1 0 0 0
1 1 x x clk

areset
30
The state transition function in this example can be
derived from the truth table:
next s0 = (~s1) & (~s0)

current next
s1 s0 s1 D0 Q0 s0
s1
0 0 0 s0
1 D1 Q1
0 1 1 0
1 0 0 0
1 1 x 0 clk

We set the don’t care to 0.

areset 35
 The state transition function:
next s0 = (~s1) & (~s0)
next s1 = (~s1) & s0

current next
s1 s0 s1 D0 Q0 s0
s1
0 0 0 s0
1 D1 Q1
0 1 1 0
1 0 0 0
1 1 0 0 clk

areset
We set this don’t care value also to 0. 36
 Structural diagram of the FSM:
State-transition function,
storage elements, and feedback of
state.

next s0
next s0 = (~s1) & (~s0) s0
D0
next s1 Q0
next s1 = (~s1) & s0 s1
D1 Q1

areset clk
33
 Essence so far
State diagram:
“next state” is a function of (current) “state”

State transitions:
the “next state” becomes (the current)
“state” on the rising edge of the clock

34
The FSM modeled and
simulated with
Logisim

35
Inputs

36
 FSMs can also have inputs influencing
the transition to the next state

next state = f(state, input) A

In this example we see in == 0 C

that the one-bit input “in”
influences the choice of
the state after B. B in == 1

37
 FSMs can also have inputs influencing
the transition to the next state
next state = f(state, input)
A

in == 0

In this example we see in == 0 in == 1

that the one-bit input “in”
influences the choice of C
the state after B. B in == 1
The following state can also
be the same as the current state. 38
 The state transition table

A
current in next
state state in == 0

A 0 B in == 1
A 1 B in == 0
B 0 A
B 1 C C
C 0 A B in == 1
C 1 C

39
 Timing diagram. Example 1
time

1
clk
0
1
in
0

state A B A B C C

For a timing diagram, we need to choose values for the input

signal “in”. Only after some choice for “in” we can derive the
sequence of states from the state diagram.

40
 Timing diagram. Example 2
time

1
clk
0
1
in
0

state A B C C A B

For a timing diagram, we need to choose values for the input

signal “in”. Only after some choice for “in” we can derive the
sequence of states from the state diagram.

41
 Timing diagram. Example 3
1 time
clk
0
1
in
0

state A B C A B B

For a timing diagram, we need to choose values for the input

signal “in”. Only after some choice for “in” we can derive the
sequence of states from the state diagram.

42
 Binary state encoding: Instead of
symbolic state names we use numbers

00
current in next
state state in == 0

0 0 0 0 1 in == 1
0 0 1 0 1 in == 0
0 1 0 0 0
0 1 1 1 0 10
1 0 0 0 0 01 in == 1
1 0 1 1 0

43
 “11” does not exist: We use “Don’t
Care” as the following state

current in next 00
state state
in == 0
0 0 0 0 1
0 0 1 0 1 in == 1
0 1 0 0 0
0 1 1 1 0
in == 0
1 0 0 0 0 10
1 0 1 1 0 01 in == 1
1 1 0 x x
1 1 1 x x
44
 I have ordered the lines in the state
transition table from 0 to 7. This
makes it easier to “read” the table.
current next 00
in state state
in == 0
0 0 0 0 0 1
1 0 0 1 0 1 in == 1
2 0 1 0 0 0
in == 0
3 0 1 1 1 0
4 1 0 0 0 0 10
5 1 0 1 1 0 01 in == 1
6 1 1 0 x x
7 1 1 1 x x
45
 We call the state bits “s1” and “s0”

current in next 00
s1 s1
s0 s0 in == 0
0
0 0 0 0 1
1 in == 1
2 0 0 1 0 1
0 1 0 0 0 in == 0
3
4 0 1 1 1 0
1 0 0 0 0 10
5
1 0 1 1 0
01 in == 1
6
1 1 0 x x
7
1 1 1 x x
46
 next s0 = ( (~s1) & (~s0) & (~in))
| ( (~s1) & (~s0) & in )

current in next 00
s1 s1
s0 s0 in == 0
0
0 0 0 0 1
1 in == 1
2 0 0 1 0 1
0 1 0 0 0 in == 0
3
4 0 1 1 1 0
1 0 0 0 0 10
5
1 0 1 1 0
01 in == 1
6
1 1 0 x 0
7
1 1 1 x 0
47
 next s1 = ((~s1) &s0 & in)
| ( s1 & (~s0) & in)
current in next 00
s1 s1
s0 s0 in == 0
0
0 0 0 0 1
1 in == 1
2 0 0 1 0 1
0 1 0 0 0 in == 0
3
4 0 1 1 1 0
1 0 0 0 0 10
5
1 0 1 1 0
01 in == 1
6
1 1 0 0 0
7
1 1 1 0 0
48
 Structural diagram of the FSM

next s0 = ( (~s1) & (~s0) & (~in))

| ( (~s1) & next s0 s0
(~s0) & in ) D0
next s1 Q0
s1
next s1 = ((~s1) & s0 & in) D1 Q1
in | ( s1 & (~s0) & in)

areset clk
49
Implementation with Logisim

50
Outputs

51
 FSMs typically also have outputs
In this example we see
that the outputs are a function
of the state. We write the output A
values into the circles.
4 in == 0
We call such machines also
“Moore machines”: in == 1
in == 0
output = f(state) 3
2
B in == 1
C

52
 We define the outputs with the
“output function”
Moore machines:
A
output = f(state) 4 in == 0

in == 1
in == 0
3
state output 2
A 4 B C
in == 1
B 3
C 2
53
 Timing diagram. Example 3
1 time
clk
0
1
in
0

state A B C A B A

out 4 3 2
4
3 4

For a timing diagram, we need to choose values for the input

signal “in”. Only after some choice for “in” we can derive the
sequence of states from the state diagram. 59
 We define the outputs with binary
values
Moore machines:
A
output = f(state) 100
in == 0

in == 1
in == 0
state output 011
010
A 100 (=4) B C
(=3) in == 1
B 011
C 010 (=2)
55
 We define the outputs with binary
values
Moore machines:
A
output = f(state) 100
in == 0

in == 1
in == 0
state o2 o1 o0 011
010
A 1 0 0 B C
in == 1
B 0 1 1
C 0 1 0
56
Binary state encoding: We define the
outputs with binary values

A
100
in == 0

in == 1
in == 0
state o2 o1 o0 011
010
0 0 1 0 0 B C
in == 1
0 1 0 1 1
1 0 0 1 0
57
 We define the outputs with binary
values

o2 = ~s1 & ~s0 A

100
in == 0

in == 1
in == 0
s1 s0 o2 o1 o0 011
010
0 0 1 0 0 B C
in == 1
0 1 0 1 1
1 0 0 1 0
58
 We define the outputs with binary
values

o2 = ~s1 & ~s0 A

100
o1 = (~s1 & s0) | (s1 & ~s0) in == 0

in == 1
in == 0
s1 s0 o2 o1 o0 011
010
0 0 1 0 0 B C
in == 1
0 1 0 1 1
1 0 0 1 0
59
 We define the outputs with binary
values

o2 = ~s1 & ~s0 A

100
o1 = (~s1 & s0) | (s1 & ~s0) in == 0

o0 = ~s1 & s0 in == 1
in == 0
011
s1 s0 o2 o1 o0 010
0 0 1 0 0 B C
in == 1
0 1 0 1 1
1 0 0 1 0
60
 Structural diagram of the FSM

next s0 = (~s1 & ~s0 & ~in) o2 = ~s1 & ~s0 o2

s0
| (~s1 & ~s0 &
in) D0 o1 = (~s1 &
Q0 s1 s0)
o1
next s1 = (~s1 & s0 & in) D1 Q1 |( s1 & ~s0)
in | (s1 & ~s0 & in) o0 = ~s1 & s0 o0

areset clk
61
Implementation with Logisim

62
 Essence of Moore Machines
the state is
stored
in a
register

next s0 = (~s1 & ~s0 & ~in) o2 = ~s1 & ~s0 o2

s0
| (~s1 & ~s0 &
in) D0 o1 = (~s1 & s0)
Q0 s1 | (s1 & ~s0)
o1
next s1 = (~s1 & s0 & in) D1 Q1
in | (s1 & ~s0 & in) o0 = ~s1 & s0 o0

areset clk
63
 Essence of Moore Machines
the state is
stored
in a
register

next s0 = (~s1 & ~s0 & ~in) o2 = ~s1 & ~s0 o2

s0
| (~s1 & ~s0 &
in ) D0 o1 = (~s1 & s0)
Q0 s1 | (s1 & ~s0)
o1
next s1 = (~s1 & s0 & in) D1 Q1
in | (s1 & ~s0 & in) o0 = ~s1 & s0 o0

a state transition is
areset caused by the
clk 70
clock signal.
 Essence of Moore Machines
the state is
stored
in a
register

next s0 = (~s1 & ~s0 & ~in) o2 = ~s1 & ~s0 o2

s0
| (~s1 & ~s0 &
in ) D0 o1 = (~s1 & s0)
Q0 s1 | (s1 & ~s0)
o1
next s1 = (~s1 & s0 & in) D1 Q1
in | (s1 & ~s0 & in) o0 = ~s1 & s0 o0

With “areset” we can a state transition is

initialize the ASM areset caused by the
(“initial state”). clk 71
clock signal.
 Essence of Moore Machines
With the next-state function f
we compute the next state:
next state = f(state, input)

next s0 = (~s1 & ~s0 & ~in) o2 = ~s1 & ~s0 o2

s0
| (~s1 & ~s0 &
in ) D0 o1 = (~s1 & s0)
Q0 s1 | (s1 & ~s0)
o1
next s1 = (~s1 & s0 & in) D1 Q1
in | (s1 & ~s0 & in) o0 = ~s1 & s0 o0

areset clk
66
 Essence of Moore Machines
With the output function we compute the
output values:
output = g(state)

next s0 = (~s1 & ~s0 & ~in) o2 = ~s1 & ~s0 o2

s0
| (~s1 & ~s0 &
in ) D0 o1 = (~s1 & s0)
Q0 s1 | (s1 & ~s0)
o1
next s1 = (~s1 & s0 & in) D1 Q1
in | (s1 & ~s0 & in) o0 = ~s1 & s0 o0

areset clk
67
 Essence of Moore Machines

next- D Q out-
state next state put output
state state
input logic logic

areset clk
68
 There exist 2 types of machines:
check out the
LITTLE but IMPORTANT difference
• Moore Machines
– next state = function of state and input
– output = function of state

• Mealy Machines
– next state = function of state and input
– output = function of state and input

69
 Essence of Moore Machines

next- D Q out-
state next state put output
state state
input logic logic

areset clk
70
 Essence of Mealy Machines

output = g(state, input)

next- D Q out-
state next state put output
state state
input logic logic

areset clk 71
 Two Types of FSMs
Moore and Mealy FSMs : different output generation
• Moore FSM:
next
state
+
inputs S
D
Q outputs
Comb. n Comb.
x0...xn Logic Registers Logic yk = fk(S)
CLK
n

present state S

• Mealy FSM:
direct combinational
path!
outputs
yk = fk(S, x0...xn)
inputs + Comb.
Comb. S D Q
x0...xn n Registers Logic
Logic
CLK
n
S 72
An example for a Mealy Machine
We write the output values
next to the transition
arrows,
since the output depends not A
only on the state, but can also
depend on the input. in == 0
out = 4
out = 2
in == 0 in == 1
out = 3 out = 0

B C
in == 1
out = 1 73
The state transitions are the same as in the
previous example with the Moore Machine

A
current in next
state state in == 0
out = 4
out = 2
A 0 B in == 0 in == 1
A 1 B out = 3
B 0 A out = 0
B 1 C
C 0 A B C
C 1 C
in == 1
out = 1 74
 The output function
The output function can be derived from the state diagram.
output = g(state, input)
A
state in output
A 0 4 in == 0
out = 4
A 1 4 out = 2
B 0 3 in == 0 in == 1
B 1 1 out = 3 out = 0
C 0 2
C 1 0 B C
in == 1
out = 1 75
 Timing diagram
1 time
clk
0
1
in
0

state A B C A B A

out 4
2
3 1 3 0 4 3 4
1

For a timing diagram, we need to choose values for the input

signal “in”. Only after some choice for “in” we can derive the
sequence of states from the state diagram. We see here also, how
81
the value of “in” immediately influences the value of “out”.
Binary encoding: Re-writing the output
table with binary values.
And completing the table with the unused bit combinations.

s1 s0 in o2 o1 o0 A
0 0 0 1 0 0
in == 0
0 0 1 1 0 0 out = 4
out = 2
0 1 0 0 1 1
in == 0 in == 1
0 1 1 0 0 1
out = 3 out = 0
1 0 0 0 1 0
1 0 1 0 0 0
1 1 0 x x x B C
1 1 1 x x x in == 1
out = 1 83
We can derive the logic functions for
o2, o1, and o0

s1 s0 in o2 o1 o0 o2 = ~s1 & ~s0

0 0 0 1 0 0
0 0 1 1 0 0
0 1 0 0 1 1
0 1 1 0 0 1
1 0 0 0 1 0
1 0 1 0 0 0
1 1 0 x x x
1 1 1 x x x
78
We can derive the logic functions for
o2, o1, and o0

s1 s0 in o2 o1 o0 o2 = ~s1 & ~s0

0 0 0 1 0 0
o1 = (~s1 & s0 &
0 0 1 1 0 0
~in)
0 1 0 0 1 1 | (s1 & ~s0 & ~in)
0 1 1 0 0 1
1 0 0 0 1 0
1 0 1 0 0 0
1 1 0 x x x
1 1 1 x x x
79
We can derive the logic functions for
o2, o1, and o0

s1 s0 in o2 o1 o0 o2 = ~s1 & ~s0

0 0 0 1 0 0
o1 = (~s1 & s0 &
0 0 1 1 0 0
~in)
0 1 0 0 1 1 | (s1 & ~s0 & ~in)
0 1 1 0 0 1
1 0 0 0 1 0 o0 = ~s1 & s0
1 0 1 0 0 0
1 1 0 x x x
1 1 1 x x x
80
 The result

next s0 = (~s1 & ~s0 & ~in)

s0 o2 = ~s1 & ~s0 o2
| (~s1 & ~s0 &
in ) D0
Q0 s1 o1 = (~s1 & s0 & ~in) o1
next s1 = (~s1 & s0 & in) D1 Q1 | (s1 & ~s0 &
in | (s1 & ~s0 & in) ~in) o0
o0 = ~s1 & s0

aresetclk
• Mealy FSM:
direct combinational
path!
outputs
yk = fk(S, x0...xn)
inputs + Comb.
Comb. S D Q
x0...xn n Registers Logic
Logic
CLK
n
81
S
 Essence of Moore Machines
With the output function we compute the
output values: output = g(state)

next s0 = (~s1 & ~s0 & ~in) o2 = ~s1 & ~s0 o2

s0
| (~s1 & ~s0 &
in ) D0 o1 = (~s1 & s0)
Q0 s1 | (s1 & ~s0)
o1
next s1 = (~s1 & s0 & in) D1 Q1
in | (s1 & ~s0 & in) o0 = ~s1 & s0 o0

• Moore FSM:
next
areset clk
state
+
inputs S
D
Q outputs
Comb. n Comb.
x0...xn Logic Registers Logic yk = fk(S)
CLK
n
82
present state S
Modeling with Logisim

83