Experiment Number: Experiment 3

Experiment Name: Boolean Algebra

Date: Thursday, April 10th, 2025.

Name: Emmanuel Saviour

Student Number: 22120712851

Group Members: Emmanuel Saviour

Akinjaiyeju Tosin
Nasir Saleem
ABSTRACT
This experiment rigorously applies Boolean algebra to the design, simplification, and
analysis of digital logic circuits. A suite of logic configurations was implemented using
basic gates (AND, OR, NOT) and universal gates (NAND), with selected circuits constructed
to validate fundamental Boolean theorems such as identity, domination, idempotent,
involution, and complement laws. Logic levels were manipulated using controlled SPST
switch inputs, and outputs were monitored via LED indicators to generate empirical truth
tables. Circuit behaviour was analysed to determine logical equivalence and to verify
algebraic simplifications. Particular attention was given to the role of inverters and their
impact on signal propagation and logic state inversion within compound gate structures.
Furthermore, the experiment included the realization of complex operations such as XOR
using only NAND gates, reinforcing the universality of NAND-based logic synthesis. The
results underscore the efficiency and reliability of Boolean algebra as a foundational tool
for minimizing digital circuitry and optimizing logical operations in hardware design.

AIM
The aim of this experiment is to verify the fundamental laws of Boolean algebra through
practical implementation of logic circuits, and to demonstrate the simplification of logic
expressions using Boolean identities and universal logic gates.

THEORY
Boolean algebra, formulated by George Boole, is the mathematical foundation of digital
logic design and is critical for the operation of digital systems such as computers,
microcontrollers, and embedded circuits. In Boolean algebra, variables assume binary
values—1 (true/high) and 0 (false/low)—and are manipulated using logical operations.
The three primary Boolean operations are:
• AND (·): The output is 1 only when all inputs are 1.
• OR (+): The output is 1 if at least one input is 1.
• NOT (‾): The operation inverts the input; a 1 becomes 0, and a 0 becomes 1.
These operations are governed by a set of algebraic laws and theorems that allow for
systematic simplification of logic expressions. These include:
• Identity Law: A + 0 = A; A · 1 = A
• Null/Annulment Law: A + 1 = 1; A · 0 = 0
• Idempotent Law: A + A = A; A · A = A
• Complement Law: A + Ā = 1; A · Ā = 0
 • Involution Law: (Ā)' = A
• Commutative Law: A + B = B + A; A · B = B · A
• Associative Law: A + (B + C) = (A + B) + C; A · (B · C) = (A · B) · C
• Distributive Law: A · (B + C) = A·B + A·C; A + (B · C) = (A + B) · (A + C)
• Absorption Law: A + (A · B) = A; A · (A + B) = A
• ̄ ; (A · B)' = Ā + B
De Morgan’s Theorems: (A + B)' = Ā · B ̄

In this experiment, these laws are not only reviewed theoretically but verified through the
practical implementation of circuits using logic gate ICs such as the 7400 (NAND), 7432
(OR), and 7404 (NOT). Through various combinations of switches, inputs, and connections
on a breadboard, each logical operation is tested under controlled conditions.
The goal is to observe the behavior of outputs in relation to specific input combinations,
and to validate the logical equivalence between the simplified Boolean expression and its
corresponding hardware implementation. This verification process demonstrates the
usefulness of Boolean algebra in optimizing logic circuits for efficiency, cost, and
performance in real-world digital systems.

APPARATUS AND MATERIALS

• DC Power Supply (0-30V range)
• Multimeter
• IC 7400 (Quad 2-input NAND gates)
• IC 7432 (Quad 2-input OR gates)
• IC 7404 (Hex Inverters/NOT gates)
• 2 SPST Switches (Single Pole Single Throw)
• LED (Light Emitting Diode, for output indication)
• Jumper Wires
• Breadboard

PROCEDURE
The experiment involved the systematic construction and analysis of various logic circuits
on a solderless breadboard using standard TTL logic gate ICs. A regulated DC power supply
provided +5V (logic high) and 0V (logic low) for circuit operation. SPST switches were used
as digital input controls to simulate binary inputs (A, B, Input1, Input2), while a digital
multimeter was employed to monitor the voltage levels at intermediate and final output
points (X and Y), corresponding to logic levels of approximately 0V (LOW) and +5V (HIGH).
Each circuit was built incrementally and tested under controlled input conditions. Voltage
readings were recorded to fill corresponding truth tables (Tables 1–10). The specific steps
were as follows:
• A. Inverter Circuit (NOT Gate)
A basic inverter was implemented using a single NOT gate (e.g., IC 7404). Input A
was toggled between logic 0 and 1, and voltages at intermediate node X and output
Y were measured to populate Table 1.

• B. AND Gate Implementation Using NAND and NOT

An AND gate was constructed by cascading a NAND gate with a NOT gate. The
configuration followed Figure 2. Input1 was initially tied to 0V for Table 2 and then to
+5V for Table 3, while Input A was varied.

• C. OR Gate Circuit
Using the 7432 OR gate IC, a basic OR circuit was constructed as per Figure 3. Input
A was toggled, and the second input was inferred as per procedure. Output
measurements were recorded in Table 4.

• D. NAND Gate Circuit

A two-input NAND gate configuration (e.g., from the 7400 IC) was built as shown in
 Figure 4. Input1 was inferred and held constant while Input A was varied. Results
were logged in Table 5.

• E. Combined AND–OR Circuit

A multi-gate configuration combining AND and OR gates was assembled per Figure
5. With Input1 held at 0V and +5V respectively, and Input2 connected to Input A,
Tables 6 and 7 were completed by measuring the output voltages under different
input states.

• F. Combined OR–AND Circuit

Another complex logic structure combining OR and AND gates was implemented
following Figure 6. Input conditions were varied, and measurements were captured
in Table 8.

• G. NAND–NOR Combined Circuit

A compound circuit employing both NAND and NOR gates was assembled as shown
in Figure 7. Output Y was observed for different combinations of Input A, Input1, and
Input2. Results were recorded in Table 9.
 • H. XOR Function Using NAND Gates
A more intricate XOR logic circuit was designed exclusively using NAND gates,
following the schematic in Figure 8. Inputs A and B were varied through all possible
binary combinations. Voltages at node X (intermediate output) and node Y (final
output) were measured. The internal expression representing the Boolean term ĀB
was identified within the logic configuration. Table 10 was completed with all
corresponding measurements.

All circuits were verified for logical consistency, and outputs were cross-referenced with
theoretical truth tables to validate the implementation of fundamental Boolean laws.

RESULTS
This section explores the behaviour of eight digital logic circuits (Figures 1 through 8), each
analysed in relation to its corresponding truth table. The objective was to determine the
logical expressions of the outputs (X and/or Y) in terms of the inputs (A and/or B), and to
validate these expressions by comparing them to the observed truth table data.
DISCUSSION
Figure 1 (Circuit A) consists of a single input, A, passed through two cascaded NOT gates.
The output after the first inverter is X, and after the second, Y. The observed behavior shows
that X = Ā and Y = A. This confirms that applying two inverters sequentially reproduces the
original signal. Both outputs correctly reflected the identity principle: the signal was
returned unchanged, showing no modification by additional identity components. This
demonstrates the consistency of inversion logic and the behavior of the NOT gate.
Figure 2 (Circuit B) connects input A to a NOR gate, with the second input held LOW.
Functionally, this replicates the behavior of a NOT gate. The circuit inverts the input,
producing Y = Ā. The truth table confirms this behavior: when A = 0, Y = 1; and when A = 1, Y
= 0. This also highlights the null law for OR: the NOR gate outputs HIGH only when both
inputs are LOW. Thus, it effectively complements the signal.
Figure 3 (Circuit C) involves an OR gate where one input is A and the other is grounded (0).
The output of such a configuration mirrors the input signal, hence Y = A. The circuit
operates as an identity OR gate, confirming that ORing any signal with 0 yields the signal
itself. This affirms the identity law for the OR operation, as the output matched the input
exactly across all input states.
Figure 4 (Circuit D) features a NAND gate with one input as A and the other as its
complement, Ā. Since the AND of a variable and its complement is always 0, the NAND
gate consistently outputs 1. Thus, Y = 1 in all cases, confirming the dominance law in
NAND logic. The truth table corroborates this result, and it illustrates the behavior of
complement-based annihilation, where A · Ā = 0 and the NAND inverts this to 1.
Figure 6 (Circuit F) uses a NAND gate with both inputs connected to A. The result is
equivalent to a NOT gate, with X = Ā. A subsequent inverter yields Y = A. This arrangement
confirms the behavior of nested logic gates and reinforces the identity principle by
returning to the original input after double inversion. It also validates the utility of NAND
gates in constructing basic NOT functionality.
Overall, these circuits exemplify fundamental principles of digital logic. Each
configuration—through combinations of AND, OR, NOT, and NAND gates—demonstrated
key Boolean identities such as the identity law, null law, dominance, and idempotent
properties. The function of the inverter across several procedures was essential: it enabled
the creation of complemented signals, facilitated logical transitions between HIGH and
LOW, and allowed validation of identities involving annihilation (A · Ā = 0) and dominance (A
+ Ā = 1).
Function of the Inverter (Procedures e–h):
1. Converts logic level A to Ā, enabling validation of complement-based identities.
2. Ensures logical transitions between HIGH and LOW states to test behavior under
inverse logic conditions.
3. Enables pairing of original and complemented signals to study behaviors like
annihilation (𝐴∙Ā) and dominance (𝐴 + Ā).

CONCLUSION
This experiment provided a comprehensive investigation into the behavior of fundamental
digital logic gates and their implementation in simple circuits. Through systematic analysis
of various configurations using AND, OR, NOT, and NAND gates, the theoretical Boolean
identities were validated against actual circuit outputs. The findings reinforced core logic
principles such as identity, null, dominance, and complementarity, as well as
demonstrated how gate combinations like NAND and NOT can simulate more complex
behaviors.
Furthermore, the results showcased the critical role of the inverter in altering logic states
and enabling the validation of properties like annihilation (A·Ā = 0) and dominance (A + Ā =
1). Each circuit functioned as a microcosm of broader digital logic systems, offering
practical insights into how binary operations underpin computing and electronic systems.
By directly comparing circuit behavior to truth tables, the experiment bridged theoretical
logic with hands-on verification, a key skill for engineers and computer scientists involved
in hardware design, embedded systems, and automation. These foundational concepts
form the bedrock for more complex digital designs such as multiplexers, decoders, and
arithmetic logic units.

REFERENCES
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[4] Laboratory Manual for EEE 312 – Digital Electronics Experiments, Department of
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