signal that the quency the shownsignal.

thermore, converted responding sampled

analog bits ment equivalent
the The the the filler
original
the spectra o
Introduction
Figure ADCs to
that
the The
conversion-is-accomplished of bya input ADC the
samplingto and When in the ADCjOften, is
be Fig. assumefrequency to reference analogitself!necessary10.5-I
recovered signal. each begin digital
bits igital output
10.5-2(6) the analog an
input.
this The shows
Figure frequency to ofanalog that equivalentKnowing
This
overlap its response output into digitalsignal
antialiasing the to
fron harmonics. the input avoid a
results. within subranges, antialiasing block
-1 concept frequency,f input Thus,the code. code.This to
the,
10.ple/Hold
5Prefilter
the must as signal .digital of the
samples. shown Thesignal the ADC diagram
he tilier aliasing
General formalized
be is If has ADCoutputquantizationTypically, period tilter
at spectrum inthe subrange
allows
least is the quantizationconstani is
block Fig .
Consequently, bandwidthsanpled the is conversion code.)
of followed is of of
frequency Fig. implemented
of higher a
twice10.5-2(c). of highest there time
during
general
iagram in the at 10.5-I step
the the are by
frequency
input a finds step. is
bandwidth Nyquist th e
of response sampled
frequency
frequency time, a
dig1tal
the 2" called the u ADC.
for it At is subranges, the "The sample-and-hold by
Quantizer
an is thissignal,signal important time the A
ADC. necessaty subrange nature the signals
frequency point shown bandlimiting
this prefilier
fa, is ofof processor comversion
of aliased interest
the it is fs to where ofsignal back
Encoder Processor to increased is the understand. in analog
inpur that a circuit called
Digital applythesignal impossible or frequency at ofFig. corresponds to quantizer N time is into
rate, the the characteristics
isconverted
Furi encode
the that an
in sampling 10.5-2(2). the
orderwhich above analog number
of antialiasing
prefilte, torespons Let signalis the
ismaintains baseband
the to
forstaterecover 0.3s inpu, us to seg ADC. to
th fr as cor: the of an of
 0 fs
(a)

(b)

-fe
(c)
Antialiasing
Filter
fs
(d)
Figure 10.5-2 (a) Continuous time frequency response of the analog input signal.
(b) Sampled-data equivalent frequency response. (c) Case where fa is larger than 0.5/s,
causing aliasing. (d) Use of an antialiasing filter to avoid aliasing.

Fig. 10.5-l to eliminate signals in the incoming analog input that are
shown in Fig. 10.5-2(d). The overlapping of the folded spectra also willabove 0.5fs. This is
occur if the band
width of the analog input signal remains fixed but the sampling
2fg. Even iff,is less than 0.5f as in Fig. 10.5-2(6), as we have frequency decreases below
the antialiasing filter is necessary to eliminate the seen in the previous chaoter
into the baseband which is from 0 tof. aliasing of signals in the upper passbands
In order to maximize the input bandwidth of the
ADC, one
0.5f; aspossible. Unfortunately, this requires a very sharp cutoffdesires to make fa as close to
for the prefilter or antialias
ing filter, which make this filter difficult and complex to
operate in this manner are called Nyquist analog-to-digitalimplement. The types of ADCs that
ADCS that have fa much less than 0.5fs. These ADCs areconverters. Later we will examine
digitalconverters. Table 10.5-1l gives the classification of cal<ed oversampling analog-to
discussed in this chapter. various types of ADCs that willbe

TABLE 10.5-1 Classification of ADC Architectures

Conversion Rate Nyquist ADCs Oversampled ADCs
Slow Integrating (serial) Very high resolution > 14 bits
Medium Successive approximation Moderale resolution > 10 bits
1-bit Pipeline
Algorthmic
Fast Flash Low resolution >6 bis
Multiple-bit pipeline
Folding and interpolating
Static Characterization of ADCs
(The input of an ADC is an analog signal, typically an analog voltage, and the output is a
digital codeNhe analog input can have any value between 0and VREF WHIle the digitatcode
is restricted to fixed or discrete amplitudes. Popular digital codes used for ADCS are shown in
TabBe 10.5-2and include binary, thermometer, Gray, and two'scomplement. The most widely
used digitalcode is the binary code. Some codes have advantages over others that make them
attractive. For example, the Gray and thermometer codes only change 1-bit from one code to
the next.
The static characterization of ADCs is based on the input-output characteristic shown in.
Fig. T0.5-3 for a3-bit ADC. In this particular characteristic, the input has been shífted sothat
the ideal step changes òccur at analog input values of 0.$LSB(2i - 1), where i váries from1:
to N for an N-bit ADC.
Beneath the input-output characteristic of Fig. 10.5-3 is a plot of the quantization noise
as a function of the input/The quantization noise is a plot of the differecE berween the thfi
nite resolution characteristic and the ideal.3-bit characterístic as a function of the input vott
age. The ideal ADC characteristic will have a quantization noise that lies between 0.5LSB
The definitions for dynamic range, the signal-io-noise ratio (SNR), and the effective num
ber ofbits (ENOB) of the ADC are the same as those given in Section 10.1 for the DAC. These
quantities were referenced to the analog variable and in the case of the ADCare referenced o
the digital output word.
The resolution of the ADC isthe smallest analog changethat can be distinguished by an
ADCResoluion may be expressed in percent of full scale(F5)but is typically given in the
number of bits. N, where the converter has 2 possibleoutput states.
The primary characteristics th¥t define-the-statie-performance-of converters are ofse
error,gain error, integra< nonlinearity (INL), and diferential nonlinearity (DNL). For an ADE
with offset, let us shifr the infinite resolution characteristic line horizontally until the quanti.
ration noise is symmetrical when referenced to thisline (here we are assuming that other e
rors such as gain and nonlinearity are not dominant or have been removed from the character
istic). The horizontal difference between this line and the infinite resolution characteristic th
passes through the origin is offset eror Offset error is illustrated in Fig. 10.5-4a).
Gainerror is a diference between the actual characteristic, and the infinite resolutio
characternistic, which ispropotional 1o the magnitude oftheinput voltage.The gain error ch
be thought of as achange in the slope of the infinite resolution line above or below avalue of t

TABLE 10.5-2 Digital Output Codes Used for ADCs

Decmal Binary. Thermometer .Gray Two's Complement
000 0000000 000 000
001 0000001 001
2 O10 000001|
000011| O10 101
I00 0001||1 |10 100
001|000 011
6 O10
I00 001
 Figure 10.5-3 ldeal input
Infinite Resolninh oUtput characteristics of a 3-bit
Digital
Output
Code --Char:eteristie ADC.

LSB
100
ldeal 3-bit
Chat:wteristic

010

001

of..-.*....*... ........
0.5
00
-0.5

Analog input Valuc Normalized o V'RE:

Gain error is illustrated in Fig. 10.5-4(b). Similar to the DAC, gain error cán be measured as
characteristics at
the horizontal difference in LSBs between actual and ideal finite resolution
highest digital code, ie., between 110 and I|lon Fig. 10.5-4(b). In this example. it is as
sumed that al! other erors such as offset and nonlinearity are not present.
The definition for integral nonlinearity (UNL) Ofthe ADC is the maximum difference be
characteristic
tween the actual finite resolution charateristic and theideal finite resolution
measuret vertically in percent or LSBs. With this definition, we find that only integer values
amplitudes. This is not a
art permiticd because the digital output codes correspond to discreteaddition,
probiem as the resolution increases and the LSB becomes small, ln when measuring
to resolve the INL to
the INL if the measurement equipment is sufficiently accurate, it isable
less than a LSB.

Gain ErOr = 1.5LSBs

10ea
Characleristic -
1o1 Charadierigic 4
100,--f. J00
Actuaj
01] Çhargcterjstic
O10 o10
001 oflet i5LSB
001
000
VREF
000 VRSP
(o) (b)
igure 10.4 Example of offseterror for a 3-bit.ADC. (b) Example of gainerror
for a 3-bit hD
 Differential nonlinearity (DNL) of the ADC is defined as a
between adjacent codes measured at each measure of the separation
nonlinearity of an ADC can be written as vertical step in percent or LSBs. The differential
DNL = (D, - 1) LSBs
(10.5-1)
where D.. is the size of the actual vertical step in LSBs.
differential nonlinearity for a 3-bit ADC referenced to theFigure 10.5-5 shows the integral and
digital output code. We see that the
largest and smallest values of INL are +1LSB and -1LSB,
respectively. The largest and
smallest values of DNL are +]LSB and 0LSB, respectively. As compared
of -LSB, which resulted from the case where a step to the DAC, a DNL
should have occurred, does not happen
for the ADC. For example, at an input voltage of on Fig. l0.5-5, the fact that a vertical jump
does not occur cannot be considered as a DNL of - 1LSB.
Nonmonotonicity in an ADC occurswhen a vertical jump is negative. Nonmonotonicity
can oniy be detected by DNL Because output is limited to digital codes, all jumps are inte
gers. Normally, the vertical jump is 12LSB. If the jump is 2LSBs or greater, missing output
codes may occur. If the vertical jump is less than 0LSB, then the ADC is ot monotonic. Fig
ure 10.56 shows a 3-bit ADCcharacteristic that is not monotonic. Nonmonotonicity gener
ally occurs when the MSB does not have sufficient accuracy. The change from 01 111. . to
10000. ...s he most difficult because the MSB must have the accuracy of t0.5LSB o
excessivc DNL will occur.

Flgure 10.5-6 Example of nonmonotonic

111
Code
Output
Digital AEwar 3-bit ADC.
110 -Characieristic.
101 - -
100
DNL=
011
ao010 --+
---2,LSBs
Rldeal
Characteristic
001
Vin
000
0 1 2 3 4 6 77 8 VREF
TROOUCTION AND CHARRCTEAIZATION OF DIGITAL-ANALOG CONYERTERS
This section examines the digital-to-analog conversion aspect of this important interface.
Figure I(0.1-1(lBustrates how DACS are used in data systems J.(The input to a DAC is a
digital word consisting of parallel binary signals ilat are generated from a digital signal
Processing system. jThese parallel binary Signals are converted to an equivalent analog signal
by scaling areterence, The analog output signal may be filtered and/oramplified before being
applied to an analog signal-processing system. While the output may be voltagc or current.
most DACs have a voltage output
A DAC with avoltage output can be characterized by the block diagram in Fig. i0.1-2(a).
We see thatitconsists of adigital word of N-bits (bo, b,. bg.. . .bN-, bw-) and a reference
voltage Va.by is calledthe most signjican bir. MSB. and bN- iS Called TheTest sIRniieut
D1. LSBne vokage ouput 'OuTcan be expressed as

l'ouT = KVRErD (10.1-)

where Kis ascaling factor and the digital word Dis given as

D= + (10.1-2)
2

Nis the total number of bitsof the digital word and b,- is the ith-bit coefficient and is either
0or 1.herefore, the output of a DAC can be expressed by combining Eqs. (10.I-1) and
(T0.1-2)to get

'our = KVREF +
b + (10.1-3)
2 2

or

NouT = KVEr [bo2+b,2 + b,2 + *" +by-2) (10.1-4)

Digital Signal
Processing
System
Microprocessors DIGITAL
Compac1 disks ANALOG Filter Amplifier Analog
Read only memory
Random access memory |CONVERTER Ouiput
Digital transmission
Disk outpuLs
Digital sensors

Reference
Figure 10.1-! Digital-analog converter in signal-processing applications.
 bo. Sample
b Digital bË-+ Digital and
b Analog roUT b-|Latch
Analog
Hold
-VouT
Converter
:Converter
bN-] bN-|+
Clock
(a) (b)
Figure 10.1-2 (a) Digital-analog converter in signal-processing applications.
(b) Clocked digital-analog converter for synchronous operation. (The asterisk rep
resents a signal that has been sampled und held.)

Gamany cascsthe digital word is synchronously clocked.ynthis case latches must be used
to holdthe word for conversion anda sample-and-hold circuit is needed atthe output, as shown
in Fig. 10.-26). We will examine sample-and-hold circuits in piore detail later in this chapter.
The basic form of a DAC providing an analog output voliage is shown in more detail in
Fig. 10.1-3. lt includes binary switches, a scaling network, and an output amplifier. The
scaling network and binary switches operate on the reference voltage to crcate a voltage that
has been scaled by the digital word. The scaling mechanism may be voltage, current, or
charge scaling. The output amplifier amplifies the scaled voltage signal to a desired level
and provides the ability to source or sink current into a load.

Static Charaçteristics of DACs

The characterization of DACS is yery important in understanding its designThe character
istics ofthe digital-analog converter can be divided into statiç. and dynamic propertes The
resolurion of the DACIS equat to the numberofbits in the applied digital input word he
resoluion of a DAC is expressed as N-bits, where Nis the number of bits. Figure 10.1-4
shows the input and output characteristics of an deal3-bir DACW= 3).)We see that each of
the eight possible digital words has its own unique analog output voltage. jThese eves are
separated by an LSB.The value ofthe LSB can be defined as

SB = VREF (10.1-5)

Asthe digital word increases by 1-bit,the output of the ideal DAC should iump.up by lLSB)
We note that the output is 0.0625 Vfor the digital input of 000. However, there is no reason

Voltage VREF Scaling DVREF Output VOUT =

Reference Network Amplifier KDVREF

Binary Switches

bobË b bN-1
Figure 10.1-3 Block diagram of a digital-analog converter.
 L.000 Figure 10.1-4 ldeal
VREE0.875
input-outpui
characteristics of i 3-bit DÁC
ilnfinite Resolution
to Characterisic
Normalized
0.750

0.625
Value
0.500
Output
ILSB

--
Vertica. Shilied
0.375 koCharacteristic
Analog
0.250

0.125

0.000
000 001 010 011 100 101 110
Digital Input Code

why the characteristic cannot be shifted downward by a half LSB as shown by the dashed
characteristic, which corresponds to 0Vfor the digital input of 000.
Because the resolution of the DAC is finite (3 in the case of Fig. 10.1-4), the maximum
analog output voltage does not equal VREF. This result is characterized by the full scale (FS),
value of the DAC.(The fullscale value is defined as the difference between the analog output
for the largest digital word (11T1.. )and the analog output for the sinallest digital word
(0000. . .). in general, the full scale of a DAC can be expressed as

Full scale (FS) = VREP - LSB = (10.1-6)

This definition of FS holds regardless of whether the characteristic h¡s been shifted verticYlly
by 0.5LSB. Inthe case of Fig. 10.1-4,FS is equalto 0.875 VRER Thefull scale range (ENSR)
is defined as

lim
FSR = (10.1-7)

Based on the above discussion, let us define several important quantities that are
porant for DACs. The first is called quantization noise. Quantization noise is the inherent"
imacele
uncertainty in digitizing an analog value with a finite sesolution convererTo understand
this definition, the characteristic for an infinite resolution DAC is plotted on Fig. 10.1-4.
This line represents the limit of the finite DAC characieristic as the number of bits, N,
approaches infsnity The quantization nöise (or error)is cqual to the analog output of the
/nfinite-bit DAC minus the analog outpur of the ftinte-btr DAC:)r We plot the quantization
noise of either of the 3-bit characteristics ín Fig. 10.14, we obtain the result shown n F
10.1-5. The solid and dashed lines correspond to the solid and dashed slaircases, respec
tively, in Fig, 10.1-4.
- iite
 Digial a FSRI2N+lThis
Ayincreasing
converter. that (10.1-8) (10.)-9'to found 1-10)
(10. (10.J-11) sinusoida.(10.1-12)
Input
Code having value desig
10.1-4.
Fig. z0.5LSB. difference
be noise
waveform the by scalecan
quantization a
of of reduced as
Within smallest
to accuracy fullnoise assuming
DAC DAC
equivalent thequantization FSR
sawtooth the
3-bit (O be of
the ratio the V2)
the of DAC only of as
is limitthecan FSR
to range LSB
expressed VRErl(2 V6
for a 0.5LSB the For
noise is noise theof that dynamic the
DR(dB)as of noise.
(PSR/2"V12) is
DAC 2
represents the
inaccuracies
(FSR/2") dB =6.02N
defined or
Quantization
10.1-5 a
that
quantization noise of
ratio FSR as value
quantization be MsVoUT for FSR/(2V2)
(FSRI2YV2 FSR/(
the expressed can
note is rms required
Noise
Quantization quantization
theexpress DAC
and DAC
00 to the is LSB The
useful
DACs DAC FSR be the the =
SNR is SNR
the reduce noise.
the Vour
can can of
ILSR 0.5LSB OLSB
-0.5LSB
Figure ihat
=
DR for of in ratio maximumKmu
is of the a We (10.1-8) results
quantization of SNR,
It property
to
of (SNR) square value
10.1-5
ILSB. by (DR) LSB). signal-to-noise
sufficient
masked
range Eq. ratio meanthis rmsthe
Fig.of fundamental an line, ms(quantization Therefore,
value (i.c., decibels, signal-to-noise
the possible
from is is dynamic rootsolid
it decneasc
the resolved
resolution. of the
see
peak-to-peàk
example, the
value the largest
of taking Therefore, waveform.
a
We is furherThe
be
terms rns by
noise
For can Thetheby ted The
In
 (10.1-13) (10.1-14) account
output
underdB. N-bits, op from An the in vertically
fullvoltage
617 resolution
include
6N a the andilusrated
monotonicity.
given For deviations
Converters in is resolve
DAC to rmsof errors characteristic
useful dB. noise characteristic
(2) a more60.2whatever
to is
infinite
logio N-bitto the Static-conversion
error
very referenced
dB Any 11 gain
Digital-AnaBog dB necessary is to and Characieristic
I
an
20 1.76 as are
an 1.76DR above due signal.nonlinearity, jumpThis
resolution and
Resolution
lafinite II0
:Characteristic: of
- for ResolutionCode
101luput
Digia) llustration
above include
the be result1ng 3-bit
ldeal
log,o(6)+ theynecessary when resolution
dB range dB could output
DAC. I00
the because 62
of
Characterization
10 6.02N from 1.76 However,
must
amplitude approximately
10-bit
amp.
voltage
erTors. finite
analog
vertical
differential
the Gain ErTor Characteristic
3-bit
Actual
01| (b)
+ defined -nctual6.02
range
required op actual shifüng
finite 010 DAC.
as (2") results static-conversion
unique any
(10.1-12)
o
dB
SNR, the dynamic
converter. voltage.a rmsthe
for at actual 001
3-bit
log 6.02
be above the range Thus, This
of
nonlinearity
the
nonlinearity, by
measured
eliminated 7/8| 6/8 4/8 3/8 000
20 as be a between S/8 a
- can =
ENOB be the VREF Normalized
to Valuc Output Analog in
Bq. o ) dB -(ENOB) The output noise. must DAC.
and the of thought dynamic should
between
error
rewrite 7.78 of DACS. signal of 1|
Introduction SNR summarize the the difference
characteristic iCharacteristic offset
quantization. category integral be Resolution Characieristic
2 4
bits of the of the there could
I10
3-bitResolution
Infinile ldeal
can dB actual of be amplitude the output
to difference 10) of
log1o perfornmance word, Code
Input
Digital Illustration
6.02N of can amplitude,
voltage,due
we
number the to range theerrors,
constanterror 100
10.! decibels 20 important the or digital
into resolution Characieristic
of switches This 3-bit
Actual 011
= is in gain the (a) DAC.
B) SNR#ctual the presence output
present fall a 10.1-6
Figure
(a)
effective dynamic 10.1-6(a). 010
of (d
mas the of signal each is
erors,
10.14
is
terms regardless rms and erroriinite error 6/8--- Offset
5/8-i- 4/8Error 001 3-bit
SNR is standing
where
I analog
the is For ain
error
The Scale amps offset 000
In The for ievel Fig. offset ideal Gain
Fig. 7/8 3/8 2/8 1/8
VREFNomalized
to Value Ouiput Analog
 TAL-ANALOG AND ANALOG-DIGITAL CONVERTEKS

error is proportional to the mag-.

Characteristic measured at the rightmost vertical iump. Gain the 3-bit DAC characteristic
error is illustrated on
dde oT the DAC output voltagea This
shown in Fig. 10.1-6(b). between the actual finite resolu
difference
Integral nonlineariry (INL)is the maximum characteristic measured vertically. (ntegral
t hcharactesie and the idea) tinite resolution
scale range or in terms of the least
ROnlinearity can be expressed as apercentage of the full
which include absolute, best
significant bit. Integral nonlinearity has several subcategories, charscteristic is illustrated in
-Straight-line, and end-point linearity (2].The INL of a3-bit DAC
positive INL anda negative INL.
Fig. 10.1-7. The INL of an N-bit DAC can be expressed as a INL is the maximum negative
negative
The positive INL is the maximum positive INL. The
and the maximum -INL is -1.0LSB.
NNL. In Fig. 10.1-7, the maximum +/NL is 1.5LSB
Diferential nonlinearity (DNL) is a measure of the easures separationbetween adjacent leveis
bit-to-bit deviations from
measured at each verticaljump) Differential nonlinearity
the actual voltage change on
ideal outputsteps, tather than along the entire output range,IfVe,is
nonlinearity can be expressed as
a bit-to-bit basis and Vis the ideal change, then the differential

Diferental nonlineariy (DNL) =(V,x i0% (10.1-15)

For an N-bit DAC and a full scale voltage range of VFSR

VeSR (10.1-16)
V, =

the
Figure 10.1-7 also illustrates differential nonlinearity. Note that DNL is a measure of
step size and is totally independent of how far the actual step change may be away from the
infinite resolution characteristic at the jump. The change from 101 to 110 results in a maxi
mum +DNL of 1.5LSBs (V/V, =2.5LSBs). The maximum negative DNL isfound when the
digital input code changes from 011 to 100. The change is -0.5LSB (V/V, = -0.5LSB),
which gives a DNL of - 1.5LSBs. It is of interest to note thae as the digital input code changes
from 100 to 101, no change occurs (point A). Because we know that a change should have
Occurred, we can say that the DNL at point Ais -1LSB.
Flgure 10.1-7 lhustration of INL,
Infinite Resolution Characteristic + DNL, and nonmonotonicity in a

oeu
i )SLSB DNL,
3-bit DAC.

---}.---,-.
Nonmonotonicity
-ILSB INL
INL
--.-1.5;SB DNL
k.ldeal 3-bi Characierisic,.
Acual 3-bitCharacierisic
8 000 001 100 101 I10
Digital Input Code
 codeof nonm
its andmonoto-
619 over mater
steD input
increases a
Converters conversion
a
in As
digital
negativeDNL.
be
converter thepooralway
Digital-Analog one
never
between as very
the is behavior will
has negati
to characteristic
decrease DAC
input
of
Characterizatior. nonmonotoni
digital nonmono
more
exhibitsa
transfer or
the is-1L
as
thatneverthe exhibited
and a
Obviously,
means of
Introductionoutput slope that
10.-7-DNL
DAC the
analog
words, 100.
a
in the Figure-
101 Monotonicity
a
to has
other 0l|that
range,
from
converter.
next.Jn DAC
Scate changed
a
fulltheaie fact.