DIGITAL SYSTEM DESIGN

LABORATORY MANUAL
 DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

CERTIFICATE

This is to certify that Ms./Mr. …………………...……………………………………

Reg.No.…..……………………Section: ……………… Roll No: ………………... has

satisfactorily completed the lab exercises prescribed by Manipal Academy of Higher

Education, Manipal for Digital System Design Laboratory [ELE 2141] of Second Year

B. Tech. Degree at MIT, Manipal, in the academic year 2024-2025.

Date: ……...................................

Signature Signature
Faculty in Charge Student
 ELE 2141: DIGITAL SYSTEM DESIGN LAB [ 0 0 3 1 ]
Total contact periods: 30 hours
Course Learning Outcomes: At the end of the course, the students will be able to:
CO1 Test the designed digital circuit using standard ICs
CO2 Demonstrate the functional verification of a digital circuit using HDL
CO3 Create FPGA based digital circuit for a given application
CO4 Function as a team member in lab project to adopt inclusive approach in
engineering practice

Module I: Design, Implement and Test Digital circuits using standard ICs
Module II: Digital System Design using Programmable ASICs
Module III: Group activity – Design and develop FPGA based digital circuit for a given
application (2 weeks)
References:
1. Givone, Digital Principles & Design, TMH 2011.
2. Charles H Roth, Lizy Kurian John, Byeong Kil Lee, Digital Systems Design using Verilog,
Global Engineering Publishers, 2015
3. Ronald J. Tocci, Digital Systems - Principles & Applications, Pearson, 2005.
4. Brown & Vranesic, Fundamentals of Digital Logic with Verilog HDL design, TMH,2012
5. Nexys4 DDR FPGA reference manual. https://digilent.com/reference/_media/nexys4-
ddr:nexys4ddr_rm.pdf

List of Experiments:
Introduction to Digital System Design Laboratory and Familiarization of the equipment’s
1. Familiarization to Verilog HDL and Vivado Design flow environment
2. Combinational circuit design using MSI devices/multiplexers and decoders
3. Combinational circuit design using Verilog HDL
4. Design, Implement and test Asynchronous counters using standard ICs
5. Sequential circuit design using Verilog HDL
6. Design, Implement and test Shift registers using standard ICs
7. Design, Implement and test Finite state machine using standard ICs
8. Finite State machine Modeling using Verilog HDL and Implementation of digital
circuit on FPGA using Vivado Design Suite 2020.1
9. Group activity – Design and develop FPGA based digital circuit for a given
application (2 weeks)
General lab guideline and safety instructions

• Carry out the experiments in such a way that nobody will be injured or hurt.

• Carry out the experiments in such a way that the equipment will not be damaged or destroyed/IC
pins must not be reversed.

• Follow all written and verbal instructions carefully. If you do not understand the instructions, the
handouts and the procedures, ask the instructor or teaching assistant.

• Report any injury (cut, burn etc.) to the teacher immediately, no matter how trivial it seems. First
aid kit is available in the lab
 DIGITAL SYSTEM DESIGN LAB
Introduction to Digital System Design Laboratory and Familiarization of the
equipment’s
1. Study of Digital ICs and IC trainer kit

Example: Get familiarized with two input AND gate IC, Troubleshooting with digital ICs

2. Design, Implement and test Half Adder on digital IC trainer kit using gates

Objective: Implement and design half adder and verify the truth table using logic gates.

Theory Overview: A half adder has two inputs for the two bits to be added and two outputs
one from the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position.

Equipment/Components required:

(1) AND Gate IC 7408

(2) X-OR Gate IC 7486

(3) IC Trainer Kit

(4) Patch cords

Logic Diagram of Half Adder:

Procedure:
1. Connections are given as per circuit diagram.
2. Connect +5V and GND pins of each chip to the +5V and ground points in IC trainer kit
respectively.
3. Logical inputs are given as per circuit diagram.
4. Observe the output and verify the truth table.
Truth Table:
A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0

2. Design a circuit which has two switches S1 and S2. The output of the circuit indicated by an
LED. The LED turns off when any one of the switches is closed. If both switches are closed or
both are open LED will be ON. Design the circuit, identify the components, pin numbers,
Implement and test the functionality of the circuit on digital IC trainer kit using NAND gates.

Truth table:

S1 S2 LED
0 0 1
0 1 0
1 0 0
1 1 1
 Tutorial-1
Date:

Familiarization to Verilog HDL and Vivado Design flow environment

Familiarisation to Verilog and design flow environment

The laboratory material is targeted for use in an introductory Digital Design course, where FPGA
technology is used to validate the learned principles through creating designs using Verilog HDL.
Vivado Design Suite is the software suite produced by Xilinx for synthesis and analysis of HDL designs,
superseding Xilinx ISE with additional features for system on a chip development and high-level
synthesis. The laboratory exercises include fundamental Verilog HDL modeling principles and problem
statements.

Introduction

Vivado Design Suite: This lab guides you through the design flow using Xilinx Vivado software to
create a simple digital circuit using Verilog HDL. A typical design flow consists of creating model(s),
creating user constraint file(s), creating a Vivado project, importing the created models, assigning
created constraint file(s), optionally running behavioral simulation, synthesizing the design,
implementing the design, generating the bit stream, and finally verifying the functionality in the
hardware by downloading the generated bit stream file. The typical design flow targeting the Nexys4
DDR FPGA board is introduced here. The typical design flow is shown below.

Digital System Design Flow

Typical FPGA design flow

Verilog HDL: Verilog HDL modeling language supports three kinds of modeling styles: gate-level,
dataflow, and behavioral. The gate-level and dataflow modeling are used to model combinatorial
circuits whereas the behavioral modeling is used for both combinatorial and sequential circuits. This
lab illustrates the use of all three types of modeling by creating combinatorial circuits and sequential
circuits targeting Nexys 4DDR FPGA board and using the Vivado 2014.2 software tool.

Vivado Supported Boards are given below:

• ZedBoard
• ZYBO
• Nexys 4 DDR
• Basys 3
Nexys4 DDR FPGA board: The Nexys4 DDR board is a complete, ready-to-use digital circuit
development platform based on the latest Artix-7™ Field Programmable Gate Array (FPGA) from
Xilinx®. With its large, high-capacity FPGA (Xilinx part number XC7A100T-1CSG324C), generous
external memories, and collection of USB, Ethernet, and other ports, the Nexys4 DDR can host designs
ranging from introductory combinational circuits to powerful embedded processors. Several built-in
peripherals, including an accelerometer, temperature sensor, MEMs digital microphone, a speaker
amplifier, and several I/O devices allow the Nexys4 DDR to be used for a wide range of designs without
needing any other components.

Nexys 4DDR board features

Tutorial Problems:

1. Write, simulate and synthesize the gate level Verilog HDL code for Full adder.

module fulladder_gatelevel(
input cin,
input x,
input y,
output s,
output cout,
inout z1,
inout z2,
inout z3
);
xor(s,x,y,cin);
and(z1,x,y);
and(z2,x,cin);
and(z3,y,cin);
or(cout,z1,z2,z3);
endmodule

2. Write, simulate and synthesize the Verilog HDL code for Full adder using data flow
modeling.

module fulladder_dataflow(
input cin,
input x,
input y,
output s,
output cout
);
assign s = x ^ y ^ cin;
assign cout = (x & y) | (x & cin) | (y & cin);
endmodule
 3. Write, simulate and synthesize the Verilog HDL code for Full adder using
behavioural modeling.

module fulladd_behavioral(
input cin,
input x,
input y,
output reg cout,
output reg s);
always@(cin,x,y)
{cout,s}=x+y+cin;

endmodule
4. Write, simulate and synthesize the Verilog HDL code for 4 bit adder. Use
fulladder_gatelevel code as the instances.

module adder4_structural (
input carryin,
input [3:0] X,
input [3:0] Y,
output [3:0] S,
output carryout, inout[3:1]C
);
fulladder_gatelevel stage0 (carryin, X[0], Y[0], S[0], C[1]);
fulladder_gatelevel stage1 (C[1], X[1], Y[1], S[1], C[2]);
fulladder_gatelevel stage2 (C[2], X[2], Y[2], S[2], C[3]);
fulladder_gatelevel stage3 (C[3], X[3], Y[3], S[3], carryout);
endmodule

[Note: The instance fulladder_gatelevel code must be there in the same project]

Write the Inference: Compare the RTL schematic generated for Qn1,2, 3,and 4 in all the
modelling styles and write the inference.

5. Simulate the Verilog HDL code to implement the function(x1,x2,x3) =∑m(0,1,3,4,5,6)

6. Obtain the Boolean function for f (W, X, Y, Z) = ∑m (1, 3, 5, 7, 8, 12, 14). Simulate
the developed logic function using NAND gate instances.
Assignments

1. Write and simulate the Verilog HDL code three bit full subtractor using gate level
modeling
2. Write and simulate the Verilog HDL code for three bit full subtractor using half
subtractors.
 Procedure: Getting started with VIVADO Design Suite
This lab comprises five primary steps:
1. Create a new Vivado project
2. Analyze the source files
3. Visualize the Design and Document it .
4. Simulate the Design using Vivado simulator

Note: Students are required to create the folder relevant to their section, and name in the D drive.
(eg: sectionnamestudent1namestudent2name)
Step 1: Create a Vivado project
1-1. Launch Vivado and create a project targeting the xc7a100tcsg324-1 (Nexys4 DDR) device
and using the Verilog HDL.

1. Open Vivado 2020.1 from desktop

2. Select Create Project from Quickstart wizard to start the new project. You will see
Create a New Vivado project wizard -> click next
3. In the Project name wizard-> enter the project name as tutorialone,
enter project location->D:/studentastudentb
4. In the Project type wizard -> check option RTL Project -> Next

5. In the Default Part wizard -> Boards -> select Nexys 4DDR -> Next → Finish
6. In the project manager window go to Add sources> select Add or create design
sources -> Next

7. Select create file option in the Add or create design sources wizard
8. In the create source file wizard select file type as Verilog, file name as
fulladder_gatelevel , file location as local to project, click ok
9. Click finish in the add or create design sources wizard
10. In the Define module wizard enter the input output declarations as shown below. Enter
the port names and direction.(If the port is multiple vector signal enter the bus width
also. For example in the case of 4 bit ripple carry adder, the inputs will have a bus width
of 4, hence assign MSB of input as 3 and LSB as 0). Click OK.
11. In the project Manager window go to design sources > double click on
fulladder_gatelevel

12. Type the Verilog source code as shown

Full adder- Gate level modeling code

1-2. RTL Analysis:

1. Go to Flow navigator window >Project Manager> RTL analysis > click open
elaborated design. Save project wizard > Save
2. You get the RTL schematic of the developed code as shown.
 3. Close elaborated design window after analyzing the circuit

1-3. Simulation: Launch the Vivado simulator ,simulate and verify the functionality of the design

1. In the Flow Navigator> Project Manager >Right click on Simulation> Select

Simulation settings> Under Project settings > Simulation > confirm the Simulation
topmodule name is Verilog file name( eg: fulladder_gatelevel) click Ok.
2. In the Flow navigator window go to simulation> run simulation> run behavioral
simulation.
3. In the behavioral simulation window under objects right click on cin, x and y : apply
force clock , set the leading edge value as 0 and trailing edge value as 1 for all the
inputs. Set the time period as 100ns, 200 ns and 400ns for cin, x, y respectively (Force
constant also is another option to force the values). Click apply and OK.
4. Click on run for 1 us.Observe the simulated waveform (Click Zoom fit option if
waveforms are not shown properly)and compare the result with fulladder truth table.
5.Observe the simulated waveform (Click Zoom fit option and then Zoom in, if waveforms are not
shown properly as shown above)and compare the result with fulladder truth table.

Conclusion:
In this demonstration, you completed the simulation stages of the FPGA based digital system design
flow using Vivado Design suite Design entry, simulating and synthesizing the design.

[Note: close the existing behavioral simulation strip. Simulate the next program in the same project,
select add sources-> add or create design sources and then continue the step which is mentioned from
step 6 in the procedure.
While simulating the new program, select the program from design sources right click and set as top
module. Then proceed with the simulation steps mentioned in the procedure.
Use same project for all the programs, don’t open new project for each program]
 Tutorial 2

Date:
COMBINATIONAL CIRCUIT DESIGN USING MSI DEVICES/MULTIPLEXERS
AND DECODERS
1. Realize the following logical function using two 4:1 multiplexer and residue gates.
F(A,B,C,D) = ∑ (2,3,5,7,11,13). Use D as data input variable.

2. Assume three voice channels A2, A1, A0 has to be decoded using a digital system. The
digital system has two outputs f and g. The output f will be indicated as high when any two or
more voice channels are activated simultaneously, else f is low. The output g will be high when
the signal at A0 is high. Design, implement and test digital system with the given logic using
single 3 to 8 decoder IC and residual gates. (consider A2 as MSB)- Use 74138 IC as 3 to 8
decoder IC.

3. A jet aircraft employs a system for monitoring the rpm, pressure and temperature values of
its engines using sensors that operates as follows:
RPM sensor output = 0 when speed <4800 rpm
Pressure sensor output = 0 when pressure <220 psi
Temperature sensor output = 0 when Temperature < 220oF
The digital circuit that controls a cockpit warning light (assume high output activates warning
light) when (pressure sensor output is 1 or RPM sensor output is 0) and temperature sensor
output is 1. Design the circuit using single 4 to 1 multiplexer (residual gates may be used).

Assignment:

4. Design and test the circuit given in Qn.3 using a)2 to 4 decoders (residual gates may be used
for the design) b) 8 to 1 multiplexer IC.

5. Implement and test a 4 -bit binary to gray code converter using dual 4 to 1 multiplexer ICs
(74153 IC) and residual gates.

6. Realize the following logical function using two 8:1 multiplexer and residue gates.
F(A,B,C,D,E) = ∑(2,3,5,7,11,13,17,19,23,29,31)
Self directed learning component:

7. A lawn sprinkling system has 4 inputs and two outputs sprinkler1 and sprinkler 2 . The sprinkling
system is controlled automatically by certain combinations of the following variables.

Season (S=1 , if summer ; 0 otherwise ); Moisture content of soil (M=1 , if high ; 0 if low) ;
Outside temperature (T=1 , if high ; 0 if low); Outside humidity (H=1, if high ; 0, if low)

S
Sprinkler 1
M Lawn sprinkling
system control
T
Sprinkler 2
H

The sprinkler 1 is turned on under any of the following conditions:-

1. The temperature is high and the moisture content is low in summer
OR
2. The temperature is high and the humidity is high in summer
Sprinkler 2 is turned on under the following condition:-
1. Moisture content is low in winter
Design and Implement the lawn sprinkling system controller using 4 to 16 decoder and residual gates.
(Consider S M T H inputs in the same order with S- MSB , H -LSB)
 Tutorial 3
Date:

Combinational circuit design using Verilog HDL

1. Write and simulate the Verilog HDL code for a 4 to 1 mux using dataflow statements..
a. Using logic equation
b. Using conditional operator

2. Write and simulate Verilog HDL code for 4 to 1 mux using behavioral statements.
a. Use if – else construct

3. Using 4 to 1 mux as the instances simulate a Verilog HDL code for 16 to 1 mux.

4. Write and simulate behavioral modeling of Verilog HDL code for 2 to 4 binary decoder
using case statement. Use the 2 to 4 decoder as the instance simulate a 4 to 16 decoder
circuit.

5. To protect the process environment of an industry, slider-1: vary the temperature

reading above or below a reference value and slider- 2: vary the pressure reading above
or below a reference value. Design a digital logic to turn ON the alarm when either
temperature or pressure or both the input signals exceed the set values with a view to
protect the process environment from possible damage. Simulate the logic using
Verilog HDL and obtain the RTL schematic.
a) Use behavioral modeling
b) Use 2 to 4 decoder and residual gate as the instances

6. Write a Verilog HDL code to control the rotation of a dc motor as shown in the table.
(Assume the circuit as combinational circuit)
Input Output- Shaft angle(degree)

1110 215

1101 180

1011 90

0111 45

default 0

7. Design a system for an automobile that illuminates a warning light. Warning light is
turned on whenever a person is actually sitting in the driver’s seat, the driver’s seatbelt
 is not fastened, and the key is in the ignition. Simulate and test the developed logic
function using data flow modeling of Verilog HDL.

Assignments

1. Suppose a factory has a vat with a sensor that outputs 1 when the vat is empty, a 0
otherwise. The vat also has a pump to empty it, and a control switch to activate the
pump. Devise a digital circuit that turns the pump on when the switch is set to activate
the pump and the vat is not empty. Write the Verilog code to implement the circuit and
simulate the same.
2. Simulate the Verilog HDL code of 4 bit prime number detection circuit using data flow
statement.
3. Write and simulate a Verilog HDL code for 4-bit magnitude comparator.
4. Write and simulate a Verilog HDL code for 4-to 2 encoder.
5. Design a 4- bit adder by using dataflow modeling of Verilog HDL code. Use Arithmetic
operators.
6. Simulate the Verilog HDL code for BCD adder using behavioral statement.
7. Simulate the Verilog HDL code for 4 bit adder/ subtractor using behavioral statement.
8. Implement and test 2- bit binary magnitude comparator and realize it using minimum
number of gates.
8. Write and simulate Verilog HDL code for configurable n to 1 mux.
9. Write and simulate Verilog HDL code for N-bit adder
a. using for loop statement
b. using generate statement
10. Design and simulate a priority encoder using for loop
 Tutorial 4
Asynchronous counters
1. Design and test a modulo-8 asynchronous(ripple) up counter using JKFF (Use 74112 IC
for the design).
2. Design and test 2- digit BCD counter in the range 00 - 99 using 74LS90.
3. Design and test 1- digit BCD counter in the range 0-9 using 74LS90 and test it using
seven segment display IC.

Assignment:
4. Implement and test 1-minute counter using decade counter IC (IC 7490)
5. Implement and test 1-minute counter using binary counter IC (IC 7493)
4. Design and test a modulo-5 asynchronous up-counter (count 000-001-010-011-100-000-
001….) using 74LS112 JK flip flop
 Tutorial 5
Sequential circuit design using Verilog HDL

1. Write and simulate the Verilog HDL code for the following using behavioral statement.
a. D latch
b. D flip- flop with asynchronous reset.
c. D flip-flop with asynchronous reset and synchronous preset
2. Simulate the Verilog HDL code for 4-bit binary up-down counter with asynchronous
reset using Behavioral statement
3. Simulate the Verilog HDL code for 4-bit shift register with parallel load using
Behavioral statement
4. Write a Verilog HDL code for 4-bit universal shift register with asynchronous reset.

Synthesis,Placement, Routing and Implementation of Combinational circuit design on FPGA

using Vivado 2020.1

5. Implement and test fulladder on Nexys4DDR board.

Procedure : Synthesis, placement routing and implementation of combinational circuit design on

Nexys4DDR FPGA using Vivado 2014.2
1. Open Vivado 2020.1 > Click on Open Project > In the folder created in D drive double click
on tutorialone folder. Select tutorialone > click Open.
2. Select tutorialone.xpr. Click OK
3. Make sure that fulladder_dataflow code is there in the design sources.
4. In the Project Manager window: go to simulation, click on Simulation settings .Project
settings wizard will open. In the Project settings wizard select simulation and in simulation
top module name > browse for fulladder_dataflow. Close the project settings.
5. In the flow navigator window > RTL analysis> click on open elaborated design> you get the
RTL schematic.
6. Change the default layout option to I/O planning in the main window of the Vivado.
You can observe the device I/Os in detail as shown below.

7. Maximize the I/O ports window>select all ports>expand scalar ports.

8. Enter the pin numbers for inputs and outputs.
9. Select cin . From the drop down list of site for cin select J15 , tick the Fixed option , in the
I/O std select LVCMOS33.
10. Repeat the same for cout,s, x ,y where the pin numbers are K15,H17,M13,L16 respectively.
The window will appear as follows.
(Note: refer Appendix for pin numbers of Switches and LEDs)

11. Save the constraints as .xdc file

12. Change I/O planning to default layout>

13. Connect the Nexys4DDR board to the PC using USB port.
14. In the flow navigator> program and debug>click on generate bitstream.
15. After bitstream generation wizard appears as follows

16. Select open hardware manager. Click ok.

17. In the Program and debug> Open Hardware Manager > click on Open Target >Open
New Target

18. Click next in the open hardware target wizard

19. Click next in the hardware server settings wizard
20. click next in the select hardware target wizard
21. click finish in open hardware target summary
22. In the Program and debug>Open Hardware Manager > Click on Program device . The
window appears as shown below.

23. Click on xc7a100t_0. Then program wizard appears as shown below.

24. Click on Program. In the Td console: Device xc7a100t (JTAG device index = 0) is
programmed will be displayed.
25. If the done led of FPGA board is indicated high then the program is successfully downloaded
on to the target.
26. Change the input pins and check the output leds according to the full adder truth table.
27. To observe the synthesized design: flow navigator> synthesis> click on open synthesized
design.

28. Zoom in and locate the Look Up Table where fulladder is implemented.
29. To observe the schematic of the synthesized design: flow navigator> synthesis> synthesized
design> click on schematic.
30. To see the implemented design on fpga : : flow navigator>click on open implemented design
> Zoom to view the Implemented LUT as given above .
 31. To observe how much on chip power is consumed: : flow navigator> implementation> open
implemented design> click on Report power

Self-directed learning component:

1. Implement an arithmetic logic unit circuit on Nexys4 DDR FPGA, that function as follows:
[where A, B are the 4-bit data inputs: S2, S1, S0 : select inputs, Function – output]
S2 S1 S0 Function
L L L A plus B
L L H A minus B
L H L A plus AB’
L H H AB minus 1
H L L A AND B
H L H A OR B
H H L A XNOR B
H H H B’

(Note : Refer Nexys 4 DDR FPGA design constraints for pin numbers)

Assignments

2. Simulate the Verilog HDL code for a) binary up counter with parallel load b) BCD
up/down counter with parallel load using Behavioral statement
3. Simulate the Verilog HDL code for n bit shift register with parallel load using
Behavioral statement
4. Modify Qn. 1 to make a 8-bit wide transparent latch and 8-bit wide edge triggered
register.
5. Write a Verilog HDL code to control the rotation of a dc motor. According to the given
input shaft angle must vary (as shown in the table). (Consider the circuit as sequential
circuit)
Input Output- Shaft angle(degree)

1110 215

1101 180

1011 90

0111 45

default 0
 Tutorial 6
Shift Registers

1. Design, Implement and test a circuit that generate the sequence 0-1-2-4-9-3-7-0 using
Universal Shift register IC (74LS194)
2. Design, Implement and test 4-bit Johnson counter using Universal shift register IC.
3. Design, Implement and test 4-bit Ring counter, (which generates the sequence 1000-
0100-0010-0001-…) using D flip flop
Solution:

̅̅̅̅̅ 2
𝑝𝑟𝑒 ̅̅̅̅̅ 3
𝑝𝑟𝑒 ̅̅̅̅̅ 4
𝑝𝑟𝑒
̅̅̅̅̅ 1 Q0
𝑝𝑟𝑒
Q1 Q2 Q3

D D D D

clk D f/f D f/f D f/f

D f/f

̅̅̅̅
𝑐𝑙𝑟 1 ̅̅̅̅ ̅̅̅̅ 3 ̅̅̅̅
𝑐𝑙𝑟 2 𝑐𝑙𝑟 𝑐𝑙𝑟 4

[ Procedure: Question 3]
1. Connect the clock to Monopulser.
2. Connect all the preset and clear to separate toggle switches.
3. Initially inactivate preset by making Preset1, preset2, preset3, preset4 = 1
4. Clear all the flip flops – clr 1, clr2, clr3 , clr4 = 0
5. Inactivate clear by making clr 1, clr2, clr3 , clr4 = 1
6. Apply preset1= 0, Observe the output Q = 1000
7. Change preset1to logic 1
8. Apply the clock pulse one by one , Observe the output transition 1000 ->0100
->0010->0001->1000… repeats
Note: If the flip flop States are going to unused states due to open circuit ,correct
the circuit, then clear all the flip flops and repeat the procedure]
Assignment:

4. Design and test a circuit that generate the following sequence using D flip flop. The
sequence is 0-8-12-14-15-7-3-1-0-8-12-14 -------.
 Tutorial 7
Finite State Machine

Objectives: To design, build and test Finite state machine using Flip-flops
1. Design and test a 2-bit synchronous up-counter which counts the sequence 00->01->10-
>00->01->10….., using D flip flop IC(7474).

2. Design and test a circuit that checks for the sequence 010 continuously in a data sequence
using JKFF IC. Implement the design with Mealy machine.

Assignment:

3. Design and test a 3-bit synchronous sequence generator to generate the sequence (010- 101-
100-011-000-111-010-101-100-----) using D flip flop.
 Tutorial-8
Date:

Finite State machine Modeling using Verilog HDL and Implementation of Sequential
circuit on FPGA using Vivado Design Suite 2020.1

1. A digital system has one input x and one output Z. The output Z=1 occurs every time
the input sequence 1010 is detected. Draw the state diagram for the sequence detector
using mealy machine and implement it using Verilog HDL.
2. Draw the state diagram for the sequence detector 101 and 010 using Moore machine
and simulate the Verilog HDL code for it.

Placement, Routing and Implementation of Sequential circuit design on FPGA using Vivado
Design Suite 2020.1

3. Implement a 4 bit binary up counter on Nexys 4 DDR FPGA and display the output on
the seven segment display.

Note:

Nexys 4 DDR FPGA design constraints ## Clock signal

• Pin number of FPGA clock - E3

• IOSTANDARD - LVCMOS33
• Clock frequency :100MHZ

Assignments

1. Two products are sold from a vending machine, which has two push buttons P1 and P2.
When a button is pressed, the price of the corresponding product is displayed in a 7-
segment display. If no buttons are pressed ‘0’ is displayed, signifying ‘Rs 0’. If only P1
is pressed, ‘2’ is displayed, signifying ‘Rs 2’. If only P2 is pressed, ‘5’ is displayed,
signifying ‘Rs 5’. If both P1 and P2 are pressed, ‘E’ is displayed, signifying ‘Error’.
The names of the segments in 7-segment display, and the glow of the display for ‘0’,
‘2’, ‘5’ and ‘E’ are shown below.
 Consider (i) Push Button pressed/not Pressed in an equivalent to logic 1/0 respectively.
A segment glowing / not glowing in the display is equivalent to logic 1/0 respectively.
Implement the circuit nexys 4DDR FPGA.
2. Implement a 4 bit ring counter on Nexys 4 DDR FPGA and display the results on output
LEDs.
3. Implement a Traffic light controller using Verilog HDL with the following
assumptions.
The circuit will be driven by a clock of appropriate frequency. The three light outputs
are Red, Yellow and Green. The light glow cyclically at a fixed rate.
4. A sequential circuit has two inputs, w1 and w2 and an output z. Its function is to
compare the input sequences on the two inputs .If w1=w2 during any four consecutive
cycles, the circuit produces Z=1 otherwise Z=0. Write Verilog code for the FSM
described.
5. Implement 00-99 counter on Nexys4DDR board.
 Nexys 4 DDR FPGA design constraints

## Clock signal
#set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports {
CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
#create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];

##Switches

#set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }];

#IO_L24N_T3_RS0_15 Sch=sw[0]
#set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }];
#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
#set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }];
#IO_L6N_T0_D08_VREF_14 Sch=sw[2]
#set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }];
#IO_L13N_T2_MRCC_14 Sch=sw[3]
#set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }];
#IO_L12N_T1_MRCC_14 Sch=sw[4]
#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }];
#IO_L7N_T1_D10_14 Sch=sw[5]
#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }];
#IO_L17N_T2_A13_D29_14 Sch=sw[6]
#set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }];
#IO_L5N_T0_D07_14 Sch=sw[7]
#set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }];
#IO_L24N_T3_34 Sch=sw[8]
#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }];
#IO_25_34 Sch=sw[9]
#set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }];
#IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10]
#set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }];
#IO_L23P_T3_A03_D19_14 Sch=sw[11]
#set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }];
#IO_L24P_T3_35 Sch=sw[12]
#set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }];
#IO_L20P_T3_A08_D24_14 Sch=sw[13]
#set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }];
#IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14]
#set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }];
#IO_L21P_T3_DQS_14 Sch=sw[15]

## LEDs

#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }];

#IO_L18P_T2_A24_15 Sch=led[0]
#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }];
#IO_L24P_T3_RS1_15 Sch=led[1]
#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }];
#IO_L17N_T2_A25_15 Sch=led[2]
#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }];
#IO_L8P_T1_D11_14 Sch=led[3]
#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }];
#IO_L7P_T1_D09_14 Sch=led[4]
#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }];
#IO_L18N_T2_A11_D27_14 Sch=led[5]
#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }];
#IO_L17P_T2_A14_D30_14 Sch=led[6]
#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }];
#IO_L18P_T2_A12_D28_14 Sch=led[7]
#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }];
#IO_L16N_T2_A15_D31_14 Sch=led[8]
#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }];
#IO_L14N_T2_SRCC_14 Sch=led[9]
#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }];
#IO_L22P_T3_A05_D21_14 Sch=led[10]
#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }];
#IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11]
#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }];
#IO_L16P_T2_CSI_B_14 Sch=led[12]
#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }];
#IO_L22N_T3_A04_D20_14 Sch=led[13]
#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }];
#IO_L20N_T3_A07_D23_14 Sch=led[14]
#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }];
#IO_L21N_T3_DQS_A06_D22_14 Sch=led[15]
#set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B
}]; #IO_L5P_T0_D06_14 Sch=led16_b
#set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G
}]; #IO_L10P_T1_D14_14 Sch=led16_g
#set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R
}]; #IO_L11P_T1_SRCC_14 Sch=led16_r
#set_property -dict { PACKAGE_PIN G14 IOSTANDARD LVCMOS33 } [get_ports { LED17_B
}]; #IO_L15N_T2_DQS_ADV_B_15 Sch=led17_b
#set_property -dict { PACKAGE_PIN R11 IOSTANDARD LVCMOS33 } [get_ports { LED17_G
}]; #IO_0_14 Sch=led17_g
#set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R
}]; #IO_L11N_T1_SRCC_14 Sch=led17_r

##7 segment display

#set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }];

#IO_L24N_T3_A00_D16_14 Sch=ca
#set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }];
#IO_25_14 Sch=cb
#set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }];
#IO_25_15 Sch=cc
#set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }];
#IO_L17P_T2_A26_15 Sch=cd
#set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }];
#IO_L13P_T2_MRCC_14 Sch=ce
#set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }];
#IO_L19P_T3_A10_D26_14 Sch=cf
#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }];
#IO_L4P_T0_D04_14 Sch=cg
#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }];
#IO_L19N_T3_A21_VREF_15 Sch=dp

#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }];

#IO_L23P_T3_FOE_B_15 Sch=an[0]
#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }];
#IO_L23N_T3_FWE_B_15 Sch=an[1]
#set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }];
#IO_L24P_T3_A01_D17_14 Sch=an[2]
#set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }];
#IO_L19P_T3_A22_15 Sch=an[3]
#set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }];
#IO_L8N_T1_D12_14 Sch=an[4]
#set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }];
#IO_L14P_T2_SRCC_14 Sch=an[5]
#set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }];
#IO_L23P_T3_35 Sch=an[6]
#set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }];
#IO_L23N_T3_A02_D18_14 Sch=an[7]

Note: The Nexys4 DDR board has eight 7-segment digits. All eight of the digits on the Nexys4
DDR board are connected to the same low-asserted segment pins, referred to as CA, CB,
CC,…,CG. However, each digit has its own enable which is also low-asserted. Error! R
eference source not found.below shows the eight 7-segment displays on the Nexys4 DDR
board. CA is connected to the cathode of the A segment for all eight displays, CB to the cathode
of the B segment for all displays, and so forth. Each digit has an enable signal, corresponding
to the respective bit of the signal AN[7:0]. AN[7:0] is connected via an inverter, to the anode
of all segments for the respective digit.

Figure. Common anode circuit node

 Figure. Four digit scanning 7 segment display controller timing diagram

##Buttons

#set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports {

CPU_RESETN }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn

#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }];

#IO_L9P_T1_DQS_14 Sch=btnc
#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }];
#IO_L4N_T0_D05_14 Sch=btnu
#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }];
#IO_L12P_T1_MRCC_14 Sch=btnl
#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }];
#IO_L10N_T1_D15_14 Sch=btnr
#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }];
#IO_L9N_T1_DQS_D13_14 Sch=btnd

##Pmod Headers

##Pmod Header JA

#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { JA[1] }];

#IO_L20N_T3_A19_15 Sch=ja[1]
#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { JA[2] }];
#IO_L21N_T3_DQS_A18_15 Sch=ja[2]
#set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS33 } [get_ports { JA[3] }];
#IO_L21P_T3_DQS_15 Sch=ja[3]
#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { JA[4] }];
#IO_L18N_T2_A23_15 Sch=ja[4]
#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { JA[7] }];
#IO_L16N_T2_A27_15 Sch=ja[7]
#set_property -dict { PACKAGE_PIN E17 IOSTANDARD LVCMOS33 } [get_ports { JA[8] }];
#IO_L16P_T2_A28_15 Sch=ja[8]
#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { JA[9] }];
#IO_L22N_T3_A16_15 Sch=ja[9]
#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { JA[10] }];
#IO_L22P_T3_A17_15 Sch=ja[10]

##Pmod Header JB

#set_property -dict { PACKAGE_PIN D14 IOSTANDARD LVCMOS33 } [get_ports { JB[1] }];

#IO_L1P_T0_AD0P_15 Sch=jb[1]
#set_property -dict { PACKAGE_PIN F16 IOSTANDARD LVCMOS33 } [get_ports { JB[2] }];
#IO_L14N_T2_SRCC_15 Sch=jb[2]
#set_property -dict { PACKAGE_PIN G16 IOSTANDARD LVCMOS33 } [get_ports { JB[3] }];
#IO_L13N_T2_MRCC_15 Sch=jb[3]
#set_property -dict { PACKAGE_PIN H14 IOSTANDARD LVCMOS33 } [get_ports { JB[4] }];
#IO_L15P_T2_DQS_15 Sch=jb[4]
#set_property -dict { PACKAGE_PIN E16 IOSTANDARD LVCMOS33 } [get_ports { JB[7] }];
#IO_L11N_T1_SRCC_15 Sch=jb[7]
#set_property -dict { PACKAGE_PIN F13 IOSTANDARD LVCMOS33 } [get_ports { JB[8] }];
#IO_L5P_T0_AD9P_15 Sch=jb[8]
#set_property -dict { PACKAGE_PIN G13 IOSTANDARD LVCMOS33 } [get_ports { JB[9] }];
#IO_0_15 Sch=jb[9]
#set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { JB[10] }];
#IO_L13P_T2_MRCC_15 Sch=jb[10]

##Pmod Header JC

#set_property -dict { PACKAGE_PIN K1 IOSTANDARD LVCMOS33 } [get_ports { JC[1] }];

#IO_L23N_T3_35 Sch=jc[1]
#set_property -dict { PACKAGE_PIN F6 IOSTANDARD LVCMOS33 } [get_ports { JC[2] }];
#IO_L19N_T3_VREF_35 Sch=jc[2]
#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { JC[3] }];
#IO_L22N_T3_35 Sch=jc[3]
#set_property -dict { PACKAGE_PIN G6 IOSTANDARD LVCMOS33 } [get_ports { JC[4] }];
#IO_L19P_T3_35 Sch=jc[4]
#set_property -dict { PACKAGE_PIN E7 IOSTANDARD LVCMOS33 } [get_ports { JC[7] }];
#IO_L6P_T0_35 Sch=jc[7]
#set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { JC[8] }];
#IO_L22P_T3_35 Sch=jc[8]
#set_property -dict { PACKAGE_PIN J4 IOSTANDARD LVCMOS33 } [get_ports { JC[9] }];
#IO_L21P_T3_DQS_35 Sch=jc[9]
#set_property -dict { PACKAGE_PIN E6 IOSTANDARD LVCMOS33 } [get_ports { JC[10] }];
#IO_L5P_T0_AD13P_35 Sch=jc[10]

##Pmod Header JD

#set_property -dict { PACKAGE_PIN H4 IOSTANDARD LVCMOS33 } [get_ports { JD[1] }];

#IO_L21N_T3_DQS_35 Sch=jd[1]
#set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { JD[2] }];
#IO_L17P_T2_35 Sch=jd[2]
#set_property -dict { PACKAGE_PIN G1 IOSTANDARD LVCMOS33 } [get_ports { JD[3] }];
#IO_L17N_T2_35 Sch=jd[3]
#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { JD[4] }];
#IO_L20N_T3_35 Sch=jd[4]
#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { JD[7] }];
#IO_L15P_T2_DQS_35 Sch=jd[7]
#set_property -dict { PACKAGE_PIN G4 IOSTANDARD LVCMOS33 } [get_ports { JD[8] }];
#IO_L20P_T3_35 Sch=jd[8]
#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { JD[9] }];
#IO_L15N_T2_DQS_35 Sch=jd[9]
#set_property -dict { PACKAGE_PIN F3 IOSTANDARD LVCMOS33 } [get_ports { JD[10] }];
#IO_L13N_T2_MRCC_35 Sch=jd[10]

##Pmod Header JXADC

#set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVDS } [get_ports { XA_N[1] }];

#IO_L9N_T1_DQS_AD3N_15 Sch=xa_n[1]
#set_property -dict { PACKAGE_PIN A13 IOSTANDARD LVDS } [get_ports { XA_P[1] }];
#IO_L9P_T1_DQS_AD3P_15 Sch=xa_p[1]
#set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVDS } [get_ports { XA_N[2] }];
#IO_L8N_T1_AD10N_15 Sch=xa_n[2]
#set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVDS } [get_ports { XA_P[2] }];
#IO_L8P_T1_AD10P_15 Sch=xa_p[2]
#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVDS } [get_ports { XA_N[3] }];
#IO_L7N_T1_AD2N_15 Sch=xa_n[3]
#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVDS } [get_ports { XA_P[3] }];
#IO_L7P_T1_AD2P_15 Sch=xa_p[3]
#set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVDS } [get_ports { XA_N[4] }];
#IO_L10N_T1_AD11N_15 Sch=xa_n[4]
#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVDS } [get_ports { XA_P[4] }];
#IO_L10P_T1_AD11P_15 Sch=xa_p[4]

##VGA Connector

#set_property -dict { PACKAGE_PIN A3 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[0]

}]; #IO_L8N_T1_AD14N_35 Sch=vga_r[0]
#set_property -dict { PACKAGE_PIN B4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[1]
}]; #IO_L7N_T1_AD6N_35 Sch=vga_r[1]
#set_property -dict { PACKAGE_PIN C5 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[2]
}]; #IO_L1N_T0_AD4N_35 Sch=vga_r[2]
#set_property -dict { PACKAGE_PIN A4 IOSTANDARD LVCMOS33 } [get_ports { VGA_R[3]
}]; #IO_L8P_T1_AD14P_35 Sch=vga_r[3]

#set_property -dict { PACKAGE_PIN C6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[0]

}]; #IO_L1P_T0_AD4P_35 Sch=vga_g[0]
#set_property -dict { PACKAGE_PIN A5 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[1]
}]; #IO_L3N_T0_DQS_AD5N_35 Sch=vga_g[1]
#set_property -dict { PACKAGE_PIN B6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[2]
}]; #IO_L2N_T0_AD12N_35 Sch=vga_g[2]
#set_property -dict { PACKAGE_PIN A6 IOSTANDARD LVCMOS33 } [get_ports { VGA_G[3]
}]; #IO_L3P_T0_DQS_AD5P_35 Sch=vga_g[3]

#set_property -dict { PACKAGE_PIN B7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[0]

}]; #IO_L2P_T0_AD12P_35 Sch=vga_b[0]
#set_property -dict { PACKAGE_PIN C7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[1]
}]; #IO_L4N_T0_35 Sch=vga_b[1]
#set_property -dict { PACKAGE_PIN D7 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[2]
}]; #IO_L6N_T0_VREF_35 Sch=vga_b[2]
#set_property -dict { PACKAGE_PIN D8 IOSTANDARD LVCMOS33 } [get_ports { VGA_B[3]
}]; #IO_L4P_T0_35 Sch=vga_b[3]

#set_property -dict { PACKAGE_PIN B11 IOSTANDARD LVCMOS33 } [get_ports { VGA_HS

}]; #IO_L4P_T0_15 Sch=vga_hs
#set_property -dict { PACKAGE_PIN B12 IOSTANDARD LVCMOS33 } [get_ports { VGA_VS
}]; #IO_L3N_T0_DQS_AD1N_15 Sch=vga_vs

##Micro SD Connector

#set_property -dict { PACKAGE_PIN E2 IOSTANDARD LVCMOS33 } [get_ports { SD_RESET

}]; #IO_L14P_T2_SRCC_35 Sch=sd_reset
#set_property -dict { PACKAGE_PIN A1 IOSTANDARD LVCMOS33 } [get_ports { SD_CD }];
#IO_L9N_T1_DQS_AD7N_35 Sch=sd_cd
#set_property -dict { PACKAGE_PIN B1 IOSTANDARD LVCMOS33 } [get_ports { SD_SCK }];
#IO_L9P_T1_DQS_AD7P_35 Sch=sd_sck
#set_property -dict { PACKAGE_PIN C1 IOSTANDARD LVCMOS33 } [get_ports { SD_CMD
}]; #IO_L16N_T2_35 Sch=sd_cmd
#set_property -dict { PACKAGE_PIN C2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[0]
}]; #IO_L16P_T2_35 Sch=sd_dat[0]
#set_property -dict { PACKAGE_PIN E1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[1]
}]; #IO_L18N_T2_35 Sch=sd_dat[1]
#set_property -dict { PACKAGE_PIN F1 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[2]
}]; #IO_L18P_T2_35 Sch=sd_dat[2]
#set_property -dict { PACKAGE_PIN D2 IOSTANDARD LVCMOS33 } [get_ports { SD_DAT[3]
}]; #IO_L14N_T2_SRCC_35 Sch=sd_dat[3]

##Accelerometer

#set_property -dict { PACKAGE_PIN E15 IOSTANDARD LVCMOS33 } [get_ports { ACL_MISO

}]; #IO_L11P_T1_SRCC_15 Sch=acl_miso
#set_property -dict { PACKAGE_PIN F14 IOSTANDARD LVCMOS33 } [get_ports { ACL_MOSI
}]; #IO_L5N_T0_AD9N_15 Sch=acl_mosi
#set_property -dict { PACKAGE_PIN F15 IOSTANDARD LVCMOS33 } [get_ports { ACL_SCLK
}]; #IO_L14P_T2_SRCC_15 Sch=acl_sclk
#set_property -dict { PACKAGE_PIN D15 IOSTANDARD LVCMOS33 } [get_ports { ACL_CSN
}]; #IO_L12P_T1_MRCC_15 Sch=acl_csn
#set_property -dict { PACKAGE_PIN B13 IOSTANDARD LVCMOS33 } [get_ports {
ACL_INT[1] }]; #IO_L2P_T0_AD8P_15 Sch=acl_int[1]
#set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports {
ACL_INT[2] }]; #IO_L20P_T3_A20_15 Sch=acl_int[2]

##Temperature Sensor

#set_property -dict { PACKAGE_PIN C14 IOSTANDARD LVCMOS33 } [get_ports { TMP_SCL

}]; #IO_L1N_T0_AD0N_15 Sch=tmp_scl
#set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { TMP_SDA
}]; #IO_L12N_T1_MRCC_15 Sch=tmp_sda
#set_property -dict { PACKAGE_PIN D13 IOSTANDARD LVCMOS33 } [get_ports { TMP_INT
}]; #IO_L6N_T0_VREF_15 Sch=tmp_int
#set_property -dict { PACKAGE_PIN B14 IOSTANDARD LVCMOS33 } [get_ports { TMP_CT
}]; #IO_L2N_T0_AD8N_15 Sch=tmp_ct

##Omnidirectional Microphone

#set_property -dict { PACKAGE_PIN J5 IOSTANDARD LVCMOS33 } [get_ports { M_CLK }];

#IO_25_35 Sch=m_clk
#set_property -dict { PACKAGE_PIN H5 IOSTANDARD LVCMOS33 } [get_ports { M_DATA
}]; #IO_L24N_T3_35 Sch=m_data
#set_property -dict { PACKAGE_PIN F5 IOSTANDARD LVCMOS33 } [get_ports { M_LRSEL
}]; #IO_0_35 Sch=m_lrsel
##PWM Audio Amplifier
#set_property -dict { PACKAGE_PIN A11 IOSTANDARD LVCMOS33 } [get_ports {
AUD_PWM }]; #IO_L4N_T0_15 Sch=aud_pwm
#set_property -dict { PACKAGE_PIN D12 IOSTANDARD LVCMOS33 } [get_ports { AUD_SD
}]; #IO_L6P_T0_15 Sch=aud_sd

##USB-RS232 Interface

#set_property -dict { PACKAGE_PIN C4 IOSTANDARD LVCMOS33 } [get_ports {

UART_TXD_IN }]; #IO_L7P_T1_AD6P_35 Sch=uart_txd_in
#set_property -dict { PACKAGE_PIN D4 IOSTANDARD LVCMOS33 } [get_ports {
UART_RXD_OUT }]; #IO_L11N_T1_SRCC_35 Sch=uart_rxd_out
#set_property -dict { PACKAGE_PIN D3 IOSTANDARD LVCMOS33 } [get_ports { UART_CTS
}]; #IO_L12N_T1_MRCC_35 Sch=uart_cts
#set_property -dict { PACKAGE_PIN E5 IOSTANDARD LVCMOS33 } [get_ports { UART_RTS
}]; #IO_L5N_T0_AD13N_35 Sch=uart_rts

##USB HID (PS/2)

#set_property -dict { PACKAGE_PIN F4 IOSTANDARD LVCMOS33 } [get_ports { PS2_CLK

}]; #IO_L13P_T2_MRCC_35 Sch=ps2_clk
#set_property -dict { PACKAGE_PIN B2 IOSTANDARD LVCMOS33 } [get_ports { PS2_DATA
}]; #IO_L10N_T1_AD15N_35 Sch=ps2_data

##SMSC Ethernet PHY

#set_property -dict { PACKAGE_PIN C9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDC

}]; #IO_L11P_T1_SRCC_16 Sch=eth_mdc
#set_property -dict { PACKAGE_PIN A9 IOSTANDARD LVCMOS33 } [get_ports { ETH_MDIO
}]; #IO_L14N_T2_SRCC_16 Sch=eth_mdio
#set_property -dict { PACKAGE_PIN B3 IOSTANDARD LVCMOS33 } [get_ports { ETH_RSTN
}]; #IO_L10P_T1_AD15P_35 Sch=eth_rstn
#set_property -dict { PACKAGE_PIN D9 IOSTANDARD LVCMOS33 } [get_ports {
ETH_CRSDV }]; #IO_L6N_T0_VREF_16 Sch=eth_crsdv
#set_property -dict { PACKAGE_PIN C10 IOSTANDARD LVCMOS33 } [get_ports {
ETH_RXERR }]; #IO_L13N_T2_MRCC_16 Sch=eth_rxerr
#set_property -dict { PACKAGE_PIN C11 IOSTANDARD LVCMOS33 } [get_ports {
ETH_RXD[0] }]; #IO_L13P_T2_MRCC_16 Sch=eth_rxd[0]
#set_property -dict { PACKAGE_PIN D10 IOSTANDARD LVCMOS33 } [get_ports {
ETH_RXD[1] }]; #IO_L19N_T3_VREF_16 Sch=eth_rxd[1]
#set_property -dict { PACKAGE_PIN B9 IOSTANDARD LVCMOS33 } [get_ports { ETH_TXEN
}]; #IO_L11N_T1_SRCC_16 Sch=eth_txen
#set_property -dict { PACKAGE_PIN A10 IOSTANDARD LVCMOS33 } [get_ports {
ETH_TXD[0] }]; #IO_L14P_T2_SRCC_16 Sch=eth_txd[0]
#set_property -dict { PACKAGE_PIN A8 IOSTANDARD LVCMOS33 } [get_ports {
ETH_TXD[1] }]; #IO_L12N_T1_MRCC_16 Sch=eth_txd[1]
#set_property -dict { PACKAGE_PIN D5 IOSTANDARD LVCMOS33 } [get_ports {
ETH_REFCLK }]; #IO_L11P_T1_SRCC_35 Sch=eth_refclk
#set_property -dict { PACKAGE_PIN B8 IOSTANDARD LVCMOS33 } [get_ports { ETH_INTN
}]; #IO_L12P_T1_MRCC_16 Sch=eth_intn
##Quad SPI Flash

#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports {

QSPI_DQ[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports {
QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
#set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports {
QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
#set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports {
QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN
}]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn
General Purpose I/O devices on the Nexys4 DDR
VIVADO design Flow:
 Digital IC Pin Details and Functional Tables

1) 7400 QUAD 2 INPUT NAND GATE:

𝒀 = ̅̅̅̅
𝑨𝑩

Inputs Output
A B Y
L L H
L H H
H L H
H H L

H=High Logic Level

L=Low Logic Level

2) 7402 QUAD 2 INPUT NOR GATE:

𝒀 = ̅̅̅̅̅̅̅̅
𝑨+𝑩

Inputs Output
A B Y
L L H
L H L
H L L
H H L

H=High Logic Level

L=Low Logic Level

3) 7404 HEX INVERTER/NOT GATE:

̅
𝒀=𝑨

Input Output
A Y
L H
H L

H=High Logic Level

L=Low Logic Level
4) 7408 QUAD 2 INPUT AND GATE:
𝒀 = 𝑨𝑩
Inputs Output
A B Y
L L L
L H L
H L L
H H H

H=High Logic Level

L=Low Logic Level

5) 7410 TRIPLE 3 INPUT NAND GA TE:

𝒀 = ̅̅̅̅̅̅
𝑨𝑩𝑪
Inputs Output
A B C Y
X X L H
X L X H
L X X H
H H H L

H=High Logic Level

L=Low Logic Level
X=Either Low or High Logic Level

6) 7411 TRIPLE 3 INPUT AND GATE:

𝒀 = 𝑨𝑩𝑪

Inputs Output
A B C Y
X X L L
X L X L
L X X L
H H H H

H=High Logic Level

L=Low Logic Level
X=Either Low or High Logic Level
7) 7420 DUAL 4 INPUT NAND GATE:
̅̅̅̅̅̅̅̅̅
𝒀 = 𝑨𝑩𝑪𝑫
Inputs Output
A B C D Y
X X X L H
X X L X H
X L X X H
L X X X H
H H H H L

H=High Logic Level

L=Low Logic Level
X=Either Low or High Logic Level

8) 7421 DUAL 4 INPUT AND GATE:

𝒀 = 𝑨𝑩𝑪𝑫

Inputs Output
A B C D Y
X X X L L
X X L X L
X L X X L
L X X X L
H H H H H

H=High Logic Level

L=Low Logic Level
X=Either Low or High Logic Level

9) 7427 TRIPLE 3 INPUT NOR GATE:

𝒀 = ̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑨+𝑩+𝑪

Inputs Output
A B C Y
X X H L
X H X L
H X X L
L L L H
H=High Logic Level
L=Low Logic Level
X=Either Low or High Logic Level
10) 74LS30 - 8 INPUT NAND GATE:
𝒀 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑨𝑩𝑪𝑫𝑬𝑭𝑮𝑯

Inputs Output
A through H Y
All inputs H L
One or more inputs L H

H=High Logic Level

L=Low Logic Level

11) 7432 QUAD 2 INPUT OR GATE:

𝑌 =𝐴+𝐵

Inputs Output
A B Y
L L L
L H H
H L H
H H H

H=High Logic Level

L=Low Logic Level

12) 7446/7447 BCD TO SEVEN SEGMENT DECODER:

Symbol Description
A, B, C, D BCD inputs
̅̅̅̅̅
RBI Ripple-Blanking Input
LT Lamp-Test Input
̅̅̅̅̅̅̅̅̅̅ Blanking Input or
BI\RBO
Ripple-Blanking Output
𝑎̅ to 𝑔̅ Outputs
13) 7448 BCD TO SEVEN SEGMENT DECODER:

Symbol Description
A, B, C, D BCD inputs
̅̅̅̅̅
RBI Ripple-Blanking Input
̅𝐿𝑇
̅̅̅ Lamp-Test Input
̅̅̅̅̅̅̅̅̅̅ Blanking Input or
BI\RBO
Ripple-Blanking Output
𝑎 to 𝑔 Outputs

H=High Logic Level

L=Low Logic Level
X=Either Low or High Logic Level
14) 7473 DUAL J-K FLIP-FLOP:

Symbol Description
Q True output
̅
Q Complement Output
Clock Clock input
J Data input1
K Data input2
Asynchronous reset
RESET
(Low activated)
GND Ground
VCC Supply Voltage
 Inputs Outputs
̅ Operating mode
RESET Clock J K Q Q
L X X X L H Asynchronous reset (Low activated)
H h h 𝑞̅ q Toggle
H l h L H Load 0 (reset)
H h l H L Load 1 (set)
H l l q 𝑞̅ Hold (no change)
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
15) 7474 DUAL D FLIP-FLOP:
Symbol Description
Q True output
̅
Q Complement Output
CLK Clock input
D Data input
Asynchronous reset
CLR
(active low)
Asynchronous set
PR
(active low)
GND Ground
VCC Supply Voltage

Inputs Outputs
̅ Operating mode
PR CLR CLK D Q Q
L H X X H L Asynchronous set (Low activated)
H L X X L H Asynchronous reset (Low activated)
L L X X H H Note1
H H h H L Load 1 (set)
H H l L H Load 0 (reset)
H H L X q 𝑞̅ Hold (no change)
 H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
q = state of referenced output one set-up time prior to the LOW-to-HIGH clock transition;
X = don’t care;
= LOW-to-HIGH clock transition.
Note1: This configuration is nonstable; That is, it will not persist when either the preset and\or clear inputs return to
their inactive (HIGH) level.

16) 7478 DUAL J-K FLIP-FLOP WITH PRESET, COMMON CLOCK, AND
COMMON CLEAR:

Symbol Description
Q True output
̅
Q Complement Output
CLK Clock input
J Data input1
K Data input2
Asynchronous reset
CLR
(Low activated)
Asynchronous set
PR
(Low activated)
GND Ground
VCC Supply Voltage

Inputs Outputs
̅ Operating mode
PR CLR Clock J K Q Q
L H X X X H L Asynchronous set (Low activated)
H L X X X L H Asynchronous reset (Low activated)
L L X X X H H Note 1
H H h h 𝑞̅ q Toggle
H H l h L H Load 0 (reset)
H H h l H L Load 1 (set)
H H l l q 𝑞̅ Hold (no change)
H H H X X q 𝑞̅ Hold (no change)
 H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
Note1: This configuration is nonstable; That is, it will not persist when either the preset and\or clear inputs return to
their inactive (HIGH) level.

17) 7485 – 4 BIT MAGNITUDE COMPARATOR:

Symbol Description
A0-A3, B0-B3 Parallel inputs
IA=B A=B Expander inputs
A<B, A>B,
IA<B, IA>B
Expander inputs
OA>B A greater than B output
OA<B B greater than A output
OA=B A equal to B output

H = HIGH voltage level;

L = LOW voltage level;
X = don’t care
18) 7486 – QUAD 2 INPUT EXCLUSIVE OR GATE:
𝑌 = 𝐴⨁𝐵 = 𝐴̅𝐵 + 𝐴𝐵̅

Inputs Output
A B Y
L L L
L H H
H L H
H H L

H = HIGH voltage level;

L = LOW voltage level;

19) 7490 ASYNCHRONOUS DECADE COUNTER:

H = HIGH voltage level;

L = LOW voltage level;
X=Either Low or High Logic Level

Symbol Description
̅̅̅̅̅ Clock (Active LOW going edge) Input to divide by
𝐶𝑃0
2 Section
̅̅̅̅̅ Clock (Active LOW going edge) Input to divide by
𝐶𝑃1
5 Section
MR1, MR2 Master Reset (Clear) Inputs
MS1, MS2 Master Set (Preset-9) Inputs
Q0 Output from divide by 2 Section
Q1, Q2, Q3 Outputs from divide by 5 Section
20) 7493 ASYNCHRONOUS BINARY COUNTER:

H = HIGH voltage level;

L = LOW voltage level;
X=Either Low or High Logic Level

Symbol Description

̅̅̅̅̅ Clock (Active LOW going edge) Input to divide by

𝐶𝑃0
2 Section
̅̅̅̅̅ Clock (Active LOW going edge) Input to divide by
𝐶𝑃1
5 Section
MR1, MR2 Master Reset (Clear) Inputs
Q0 Output from divide by 2 Section
Q1, Q2, Q3 Outputs from divide by 5 Section

21) 74112 JK FLIP FLOP WITH PRESET AND CLEAR:

Symbol Description
Q True output
̅
Q Complement Output
CLK Clock input
J Data input1
K Data input2
Asynchronous reset
CLR
(Low activated)
Asynchronous set
PR
(Low activated)
GND Ground
VCC Supply Voltage
 Inputs Outputs
̅ Operating mode
PR CLR Clock J K Q Q
L H X X X H L Asynchronous set (Low activated)
H L X X X L H Asynchronous reset (Low activated)
L L X X X H H Note 1
H H h h 𝑞̅ q Toggle
H H l h L H Load 0 (reset)
H H h l H L Load 1 (set)
H H l l q 𝑞̅ Hold (no change)
H H H X X q 𝑞̅ Hold (no change)

H = HIGH voltage level;

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
Note1: This configuration is nonstable; That is, it will not persist when either the preset and\or clear inputs return to
their inactive (HIGH) level.

22) 74138 -3:8 DECODER:

Symbol Description
A0-A2 Address inputs
̅̅̅̅
𝐸1, ̅̅̅̅
𝐸2 Enable (Active low) inputs
E3 Enable (Active high) input
𝑂̅0 − 𝑂̅7 Active low outputs
 Inputs Outputs

E1 E2 E3 A0 A1 A2 𝑂̅0 𝑂̅1 𝑂̅2 𝑂̅3 𝑂̅4 𝑂̅5 𝑂̅6 𝑂̅7

H X X X X X H H H H H H H H
X H X X X X H H H H H H H H
X X L X X X H H H H H H H H
L L H L L L L H H H H H H H
L L H H L L H L H H H H H H
L L H L H L H H L H H H H H
L L H H H L H H H L H H H H
L L H L L H H H H H L H H H
L L H H L H H H H H H L H H
L L H L H H H H H H H H L H
L L H H H H H H H H H H H L
H = HIGH voltage level;
L = LOW voltage level;
X = don’t care

23) 74139 -2:4 DECODER:

Symbol Description
A0-A2 Address inputs
Enable (Active low)
E
inputs
𝑂̅0 − 𝑂̅3 Active low outputs

Inputs Outputs
E A0 A1 𝑂̅0 𝑂̅1 𝑂̅2 𝑂̅3
H X X H H H H
L L L L H H H H = HIGH voltage level;
L H L H L H H L = LOW voltage level;
X = don’t care
L L H H H L H
L H H H H H L
24) 74147 -10 LINE TO 4 LINE PRIORITY ENCODER:

H = HIGH voltage level;

L = LOW voltage level;
X = don’t care
 25) 74148 -8 LINE TO 3 LINE PRIORITY ENCODER:

H = HIGH voltage level;

L = LOW voltage level;
X = don’t care

Note: 74148 provides cascading circuitry (Enable input EI and enable output EO) octal expansion without the need
for external circuitry. GS is the glitch free output.
26) 74151 -8:1 MULTIPLEXER:

Symbol Description
S0-S2 Select inputs
Enable (Active low)
E
input
I0-I7 Multiplexer inputs
Z Multiplexer output
Complementary
𝑍̅
multiplexer output

H = HIGH voltage level;

L = LOW voltage level;
X = don’t care
27) 74153 -4:1 MULTIPLEXER:

Symbol Description
S0-S1 Select inputs
Enable (Active low)
𝐸̅
input
I0-I3 Multiplexer inputs
Z Multiplexer output

H = HIGH voltage level;

L = LOW voltage level;
X = don’t care
 28) 74154 – 4:16 DECODER / DEMULTIPLXER:

Symbol Description
A-D Address inputs
̅̅̅̅
𝐺1-𝐺2̅̅̅̅ Strobe (Active low)
inputs
0-15 Active low outputs

Inputs Outputs
̅̅̅
𝐺1 ̅̅̅
𝐺2 D C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
L L L L L L L H H H H H H H H H H H H H H H
L L L L L H H L H H H H H H H H H H H H H H
L L L L H L H H L H H H H H H H H H H H H H
L L L L H H H H H L H H H H H H H H H H H H
L L L H L L H H H H L H H H H H H H H H H H
L L L H L H H H H H H L H H H H H H H H H H
L L L H H L H H H H H H L H H H H H H H H H
L L L H H H H H H H H H H L H H H H H H H H
L L H L L L H H H H H H H H L H H H H H H H
L L H L L H H H H H H H H H H L H H H H H H
L L H L H L H H H H H H H H H H L H H H H H
L L H L H H H H H H H H H H H H H L H H H H
L L H H L L H H H H H H H H H H H H L H H H
L L H H L H H H H H H H H H H H H H H L H H
L L H H H L H H H H H H H H H H H H H H L H
L L H H H H H H H H H H H H H H H H H H H L
L H X X X X H H H H H H H H H H H H H H H H
H L X X X X H H H H H H H H H H H H H H H H
H H X X X X H H H H H H H H H H H H H H H H

H = HIGH voltage level;

L = LOW voltage level;
X = don’t care
 29) 74155 – 2:4 DECODER / DEMULTIPLXER:

Symbol Description
A0-A1 Address inputs
Enable (Active low)
𝐸̅
inputs
̅ ̅
𝑂0-𝑂3 Active low outputs

H = HIGH voltage level;

L = LOW voltage level;
X = don’t care

30) 74160 – BCD DECADE COUNTERS:

Symbol Description
̅̅̅̅ Parallel Enable (Active low)
𝑃𝐸
inputs
𝑃0 − 𝑃3 Parallel inputs
CEP Count Enable parallel input
CET Count Enable Trickle input
Clock (Active high going
CP
edge) input
Master reset (Active low)
MR
input
𝑄0 − 𝑄3 Parallel outputs
TC Terminal count output
 H = HIGH voltage level;
L = LOW voltage level;
X = don’t care

31) 74168 – BCD DECADE BI-DIRECTIONAL COUNTERS:

Symbol Description
̅̅̅̅ Parallel Enable (Active low)
𝑃𝐸
inputs
𝑃0 − 𝑃3 Parallel Data inputs
Count Enable parallel input
CEP
(Active low)
̅̅̅̅̅̅ Count Enable Trickle input
𝐶𝐸𝑇
(Active low)
Clock (Active positive going
CP
edge) input
̅ Up-Down Count Control
𝑈/𝐷
Input
𝑄0 − 𝑄3 Parallel outputs
̅̅̅̅
𝑇𝐶 Terminal count output

H = HIGH voltage level;

L = LOW voltage level;
X = don’t care
 32) 74170 – 4 X 4 REGISTER FILE:

Symbol Description
𝐷1 − 𝐷4 Data inputs
𝑊𝐴 , 𝑊𝐵 Write Address Inputs
Write Enable
𝐸̅𝑊
(Active LOW) Input
𝑅𝐴 , 𝑅𝐵 Read Address Inputs
Read Enable
𝐸̅𝑅
(Active LOW) Input
𝑄1 − 𝑄4 Outputs

Write Function

Read Function

 H = HIGH voltage level; L = LOW voltage level; X = don’t care;

 (Q = D) = The four selected internal flip-flop outputs will assume the states applied to the four external data
inputs.
 Q0 = the level of Q before the indicated input conditions were established.
 W0B1 = The first bit of word 0, etc.
33) 74181 – 4 BIT ARITHMETIC LOGIC UNIT:

Symbol Description
𝐴̅0 − 𝐴̅3 Operand (Active LOW) Inputs
𝐵̅0 − 𝐵̅3 Operand (Active LOW) Inputs
𝑆0 − 𝑆3 Function – select inputs
M Mode Control Input
𝐶𝑛 Carry Input
𝐹̅0 − 𝐹̅3 Function (Active LOW) Outputs
A=B Comparator Output

𝐺̅ Carry Generator (Active LOW) Output

𝑃̅ Carry Propagate (Active LOW) Output

𝐶𝑛+1 Carry Output
 L = LOW Voltage Level
 H = HIGH Voltage Level
 *Each bit is shifted to the next more significant position
 **Arithmetic operations expressed in 2s complement notation

34) 74190 – PRESETTABLE BCD/DECADE UP/DOWN COUNTERS:

 Symbol Description
̅̅̅̅
𝐶𝐸 Count Enable (Active LOW) Input
CP Clock Pulse (Active HIGH going edge) Input
̅/D
𝑈 Up/Down Count Control Input
̅̅̅̅
𝑃𝐿 Parallel Load Control (Active LOW) Input
Pn Parallel Data Inputs
Qn Flip-Flop Outputs
̅̅̅̅
𝑅𝐶 Ripple Clock Output
TC Terminal Count Output

Mode select table

H = HIGH voltage level;

L = LOW voltage level;
X = don’t care

35) 74194 – 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER COUNTERS:

 Symbol Description
𝑆0 , 𝑆1 Mode Control Inputs
𝑃0 − 𝑃3 Parallel Data Inputs
𝐷𝑆𝑅 Serial (Shift Right) Data Input
𝐷𝑆𝐿 Serial (Shift Left) Data Input
𝐶𝑃 Clock (Active HIGH Going Edge) Input
̅̅̅̅̅
𝑀𝑅 Master Reset (Active LOW) Input
𝑄0 − 𝑄3 Parallel Outputs

 H = HIGH voltage level;

 L = LOW voltage level;
 X = don’t care
 I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition
 h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition
 pn (qn) = Lower case letters indicate the state of the referenced input (or output) one set-up time
prior to the LOW to HIGH clock transition.
 36) 74280 – 9-BIT ODD/EVEN PARITY GENERATORS/CHECKERS:

Function Table:

37) 74283 – 4-BIT BINARY FULL ADDER WITH FAST CARRY:

 Symbol Description
𝐴1 − 𝐴4 Operand A Inputs
𝐵1 − 𝐵4 Operand B Inputs
𝐶0 Carry Input
∑1 − ∑4 Sum Outputs
𝐶4 Carry Output
Example:

Function Truth Table:

C1-C3 are generated internally

C0 is an external input
C4 is an output generated internally
38) LT-542 SEVEN SEGMENT DISPLAY (COMMON ANODE):

g f VCC a b

f LT542 b

e c

d
dp

e d VCC c dp

39) LT-540 SEVEN SEGMENT DISPLAY (COMMON CATHODE):