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Am 67

The AM67x processors feature a quad-core Arm Cortex-A53 architecture with advanced multimedia capabilities, including support for multiple display interfaces and high-performance graphics processing. They are designed for a variety of applications such as smart vision cameras, industrial automation, and healthcare monitoring, integrating deep learning accelerators and a range of connectivity options. The processors also emphasize functional safety and security, making them suitable for safety-critical applications.

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Am 67

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AM67, AM67A

SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

AM67x Processors
1 Features Multimedia:
Processor Cores: • Display subsystem
• Up to Quad 64-bit Arm® Cortex®-A53 – Triple display support over OLDI/LVDS (1x
microprocessor subsystem at up to 1.4GHz OLDI-DL, 1x or 2x OLDI-SL), DSI or DPI
– Quad-core Cortex-A53 cluster with 512KB L2 • OLDI-SL (Single Link): up to 1920 x 1080 at
shared cache with SECDED ECC 60fps (165-MHz Pixel Clock)
– Each A53 core has 32KB L1 DCache with • OLDI-DL (Dual Link): up to 3840 x 1080 at
SECDED ECC and 32KB L1 ICache with Parity 60fps (150-MHz Pixel Clock)
protection • MIPI® DSI: with 4 Lane MIPI® D-PHY
• Single-core Arm® Cortex®-R5F at up to 800MHz, supports up to 3840 x 1080 at 60fps (300-
integrated as part of MCU Channel with FFI MHz Pixel Clock)
• DPI (24-bit RGB parallel interface): up to
– 32KB ICache, 32KB L1 DCache, and 64KB
1920 x 1080 at 60fps (165-MHz pixel clock)
TCM with SECDED ECC on all memories
– Four display pipelines with hardware overlay
– 512KB SRAM with SECDED ECC
support. A maximum of two display pipelines
• Single-core Arm® Cortex®-R5F at up to 800MHz,
may be used per display.
integrated to support Device Management
– 32KB ICache, 32KB L1 DCache, and 64KB – Supports safety features such as freeze frame
TCM with SECDED ECC on all memories detection and data correctness check
• Single-core Arm® Cortex®-R5F at up to 800MHz, • 3D Graphics Processing Unit
integrated to support Run-time Management – IMG BXS-4-64 with 256KB cache
– 32KB ICache, 32KB L1 DCache, and 64KB – Up to 50 GFLOPS
TCM with SECDED ECC on all memories – Single shader core
• Two Deep Learning Accelerators (up to 4 TOPS – OpenGL ES3.2 and Vulkan 1.2 API support
total), each with: • Four Camera Serial Interface (CSI-2) Receiver
– C7x floating point, up to 40 GFLOPS, 256-bit with 4 Lane D-PHY
Vector DSP at up to 1.0GHz – MIPI® CSI-2 v1.3 Compliant + MIPI® D-PHY
– Matrix Multiply Accelerator (MMA), up to 2 1.2
TOPS (8b) at up to 1.0GHz – CSI-RX supports for 1,2,3, or 4 data lane mode
– 32KB L1 DCache with SECDED ECC and up to 2.5Gbps per lane
64KB L1 ICache with Parity protection • One CSI2.0 Transmitter with 4 Lane D-PHY
– 2.25MB of L2 SRAM with SECDED ECC (shared with MIPI DSI)
• Depth and Motion Processing Accelerators – CSI-TX supports for 1,2, or 4 data lane mode
(DMPAC) up to 2.5Gbps per lane
– Dense Optical Flow (DOF) Accelerator • Video Encoder/Decoder
– Stereo Disparity Engine (SDE) Accelerator – Support for HEVC (H.265) Main profiles at
• Vision Processing Accelerators (VPAC) with Image Level 5.1 High-tier
Signal Processor (ISP) and multiple vision assist – Support for H.264 BaseLine/Main/High Profiles
accelerators: at Level 5.2
– 600MP/s ISP – Support for up to 4K UHD resolution
– Support for 12-bit RGB-IR (3840 × 2160)
– Support for up to 16-bit input RAW format • Up to 400MP/s operation
– Line support up to 4096 • Motion JPEG encode at 416MPixels/s with
– Wide Dynamic Range (WDR), Lens Distortion resolutions up to 4K UHD (3840 × 2160)
Correction (LDC), Vision Imaging Subsystem
Memory Subsystem:
(VISS), and Multi-Scalar (MSC) support
• Output color format : 8-bits, 12-bits, and • On-chip RAM dedicated to key processing cores
YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL – 256KB of On-Chip RAM (OCRAM) with
SECDED ECC
– 256KB of On-Chip RAM with SECDED ECC in
SMS Subsystem

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
AM67, AM67A
SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com

– 512KB of On-chip RAM with SECDED ECC in • Debugging security

Cortex-R5F MCU Subsystem – Secure software controlled debug access
– 64KB of On-chip RAM with SECDED ECC in – Security aware debugging
R5F Device Manager Subsystem
– 64KB of On-chip RAM with SECDED ECC in High-Speed Interfaces:
R5F Run-Time Manager Subsystem • PCI-Express® Gen3 single lane controller (PCIE)
– 2.25MB of L2 SRAM with SECDED ECC in – Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3
each C7x Deep Learning Accelerator (up to (8.0GT/s) operation with auto-negotiation
4.5MB total) • Integrated Ethernet switch supporting (total 2
• DDR Subsystem (DDRSS) external ports)
– Supports LPDDR4 memory types – RMII(10/100) or RGMII (10/100/1000) or SGMII
– 32-bit data bus with inline ECC (1Gbps)
– Supports speeds up to 4000MT/s – IEEE1588 (Annex D, Annex E, Annex F with
– Max LPDDR4 size of 8GB 802.1AS PTP)
Functional Safety: – Clause 45 MDIO PHY management
– Packet Classifier based on ALE engine with
• Functional Safety-Compliant targeted (on select 512 classifiers
part numbers) – Priority based flow control
– Developed for functional safety applications – Time Sensitive Networking (TSN) support
– Documentation will be available to aid IEC – Four CPU H/W interrupt Pacing
61508 functional safety system design – IP/UDP/TCP checksum offload in hardware
– Systematic capability up to SIL 3 targeted • USB3.1-Gen1 Port
– Hardware Integrity up to SIL 2 targeted – One enhanced SuperSpeed Gen1 port
– Safety-related certification – Port configurable as USB host, USB peripheral,
• IEC 61508 planned or USB Dual-Role Device
Security: – Integrated USB VBUS detection
• USB2.0 Port
• Secure boot supported – Port configurable as USB host, USB peripheral,
– Hardware-enforced Root-of-Trust (RoT) or USB Dual-Role Device (DRD mode)
– Support to switch RoT via backup key – Integrated USB VBUS detection
– Support for takeover protection, IP protection,
and anti-roll back protection General Connectivity and Automotive interfaces:
• Trusted Execution Environment (TEE) supported • 9x Universal Asynchronous Receiver-Transmitters
– Arm TrustZone® based TEE (UART)
– Extensive firewall support for isolation • 5x Serial Peripheral Interface (SPI) controllers
– Secure watchdog/timer/IPC • 7x Inter-Integrated Circuit (I2C) ports
– Secure storage support • 5x Multichannel Audio Serial Ports (McASP)
– Replay Protected Memory Block (RPMB) • General-Purpose I/O (GPIO), All LVCMOS I/O can
support be configured as GPIO
• Dedicated Security Controller with user • 4x Controller Area Network (CAN) modules with
programmable HSM core and dedicated security CAN-FD support
DMA & IPC subsystem for isolated processing
Media and Data Storage:
• Cryptographic acceleration supported
– Session-aware cryptographic engine with ability • 3x Secure Digital® (SD®) (4b+4b+8b) interfaces
to auto-switch key-material based on incoming – 1x 8-bit eMMC interface up to HS400 speed
data stream – 2x 4-bit SD/SDIO interfaces up to UHS-I
• Supports cryptographic cores – Compliant with eMMC 5.1, SD 3.0, and SDIO
– AES – 128-/192-/256-Bit key sizes Version 3.0
– SHA2 – 224-/256-/384-/512-Bit key sizes • 1× General-Purpose Memory Controller (GPMC)
– DRBG with true random number generator up to 133MHz
– PKA (Public Key Accelerator) to Assist in • OSPI/QSPI with DDR / SDR support
RSA/ECC processing for secure boot – Support for Serial NAND and Serial NOR Flash
– 4GBytes memory address support
– XIP mode with optional on-the-fly encryption

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Technology / Package:
• 16-nm FinFET technology 2 Applications
• 18 mm x 18 mm, 0.65 mm pitch with VCA (AMW)
• Human Machine Interface (HMI)
Companion Power Management Solution: • Hospital patient monitoring
• Functional Safety-Compliant support up to ASIL-B • Industrial PC
or SIL-2 targeted • Building security system
• TPS6522x PMIC • Off-highway vehicle
• TPS6287x Stackable, Fast Transient Bucks • Test and measurement
• Energy storage systems
• Video Surveillance
• Machine Vision
• Industrial mobile robot (AGV/AMR)
• Front camera systems
3 Description
The AM67x scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart
Vision Camera and General Compute applications and built on extensive market knowledge accumulated over
a decade of TI’s leadership in the Vision processor market. The AM67x family is built for a broad set of
cost-sensitive high performance compute applications in Factory Automation, Building Automation, and other
markets.
The AM67x provides high performance compute technology for both traditional and deep learning algorithms
at industry leading power/performance ratios with a high level of system integration to enable scalability and
lower costs for advanced vision camera applications. Key cores include the latest Arm and GPU processors for
general compute, next generation DSP with scalar and vector cores, dedicated deep learning and traditional
algorithm accelerators, an integrated next generation imaging subsystem (ISP), video codec, and MCU cores. All
protected by industrial-grade security hardware accelerators.
AM67x contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator
(VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL), Dense
Optical Flow (DOF) video and 3D Graphics accelerators, a Cortex®-R5F MCU Island core and two Cortex®-
R5F cores for Device and Run-time Management. The Cortex-A53s provide the powerful computing elements
necessary for Linux applications as well as the implementation of traditional vision computing based algorithms.
Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader
sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics
applications. Key cores include two “C7x” next generation DSP with scalar and vector cores, dedicated “MMA”
deep learning accelerator combined with a large 2.25MB L2 memory enabling performance up to 4 TOPS
within the lowest power envelope in the industry when operating at the typical automotive worst case junction
temperature of 125°C.
The AM67x integrates high-speed IOs including a PCIe Gen-3 (1L) and 3-port Gigabit Ethernet switch with
one internal port and two external ports with TSN support. In addition, an extensive peripherals set is included
in AM67x to enable system level connectivity such as USB, MMC/SD, four CSI2.0 Camera interface, OSPI,
CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM67x supports secure boot for IP
protection with the built-in HSM (Hardware Security Module) and employs advanced power management support
for power-sensitive applications.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
XJ722S5A AMW (FCBGA, 594) with VCA 18mm x 18mm
AM67A94 AMW (FCBGA, 594) with VCA 18mm x 18mm
AM67A74 AMW (FCBGA, 594) with VCA 18mm x 18mm
AM6754 AMW (FCBGA, 594) with VCA 18mm x 18mm

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Package Information (continued)

PART NUMBER PACKAGE(1) PACKAGE SIZE(2)
AM6734 AMW (FCBGA, 594) with VCA 18mm x 18mm

(1) For more information, see Mechanical, Packaging, and Orderable Information.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.

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www.ti.com SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

3.1 Functional Block Diagram

Note
To understand what device features are currently supported by TI Software Development Kits (SDKs),
see the PROCESSOR-SDK-AM67 Software Build Sheet and PROCESSOR-SDK-AM67A Software
Build Sheet.

Figure 3-1 is functional block diagram for the device.

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AM67x

Application Cores MCU Channel Device Management

with FFI
2x Arm
Arm®® Arm® Arm® 64KB TCM
® Arm® Cortex®-R5F with ECC
Cortex®-A53
Cortex -A53 Cortex®-A53
Cortex®-R5F

Run-time Management
Arm® Arm® 64KB TCM
Cortex®-A53 Cortex®-A53 with ECC
Arm® 64KB TCM
512KB SRAM Cortex®-R5F with ECC
with ECC
512KB Shared L2 with ECC
Safety DTK System Memory
256KB SRAM
with ECC GPMC
Deep Learning Accelerator (2 TOPS) Deep Learning Accelerator (2 TOPS) (Shared)

C7x DSP 256b + MMA C7x DSP 256b + MMA LPDDR4

with inline ECC 3x MMCSD
2.25MB L2 SRAM with ECC 2.25MB L2 SRAM with ECC (32b)

General Connectivity and IO

General Connectivity Multimedia
2-port Gb Ethernet w/ 1588 (MCUSS)
H.264/H.265
JPEG Encode
Video Codec
3x SPI GPIO GPIO
3x Display with OLDI/DPI/DSI
7x UART McASP 2x SPI
3D Graphics Processing Unit
2x CAN-FD PCIe Gen3 UART

USB 3.1 RGB-IR VPAC DOF

5x I2C 2x CAN-FD

OSPI USB 2.0 I2C 4x 4L CSI2-RX 4L CSI2-TX

Security
HSM
(Secure Boot) SHA PKA DRBG
SMS
MD5 AES TRNG
426KB SRAM with ECC

System Services

DMA Firewall Secure Boot DCC RTC

Power System
Manager Monitor
Debug IPC ECC ESM Timers

Figure 3-1. Functional Block Diagram

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www.ti.com SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

Table of Contents
1 Features............................................................................1 6.9 Timing and Switching Characteristics....................... 95
2 Applications..................................................................... 3 7 Detailed Description....................................................215
3 Description.......................................................................3 7.1 Overview................................................................. 215
3.1 Functional Block Diagram........................................... 5 8 Applications, Implementation, and Layout............... 216
4 Device Comparison......................................................... 7 8.1 Device Connection and Layout Fundamentals....... 216
5 Terminal Configuration and Functions..........................9 8.2 Peripheral- and Interface-Specific Design
5.1 Pin Diagrams.............................................................. 9 Information................................................................ 217
5.2 Pin Attributes.............................................................10 8.3 Clock Routing Guidelines........................................224
5.3 Signal Descriptions................................................... 48 9 Device and Documentation Support..........................225
5.4 Pin Connectivity Requirements.................................79 9.1 Device Nomenclature..............................................225
6 Specifications................................................................ 82 9.2 Tools and Software................................................. 228
6.1 Absolute Maximum Ratings...................................... 82 9.3 Documentation Support.......................................... 228
6.2 ESD Ratings for Devices which are not AEC - 9.4 Support Resources................................................. 228
Q100 Qualified............................................................ 84 9.5 Trademarks............................................................. 228
6.3 Power-On Hours (POH)............................................ 84 9.6 Electrostatic Discharge Caution..............................229
6.4 Recommended Operating Conditions.......................85 9.7 Glossary..................................................................229
6.5 Operating Performance Points..................................87 10 Revision History........................................................ 229
6.6 Electrical Characteristics...........................................88 11 Mechanical, Packaging, and Orderable
6.7 VPP Specifications for One-Time Programmable Information.................................................................. 231
(OTP) eFuses..............................................................93 11.1 Packaging Information.......................................... 231
6.8 Thermal Resistance Characteristics......................... 94

4 Device Comparison
Table 4-1 shows a comparison between devices, highlighting the differences.

Note
Availability of features listed in this table are a function of shared IO pins, where IO signals associated
with many of the features are multiplexed to a limited number of pins. The SysConfig tool should
be used to assign signal functions to pins. This will provide a better understanding of limitations
associated with pin multiplexing.

Note
To understand what device features are currently supported by TI Software Development Kits (SDKs),
see the PROCESSOR-SDK-AM67 Software Build Sheet and PROCESSOR-SDK-AM67A Software
Build Sheet.

Table 4-1. Device Comparison

REFERENCE
FEATURES(1) AM67A94 AM67A74 AM6754 AM6734
NAME
PROCESSORS AND ACCELERATORS
Speed Grades (See Device Speed Grades) J, K
Arm Cortex-A53
Arm A53 Quad Core
Microprocessor Subsystem
Arm Cortex-R5F in MCU domain MCU_R5F Single Core
Arm Cortex-R5F in MAIN domain R5FSS0 Single Core
Device Management Subsystem WKUP_R5F Single Core
Hardware Security Module HSM Yes
Crypto Accelerators Security Yes
C7x Floating Point, Vector DSP C7x256V DSP Dual Core(6) No
Deep Learning Accelerator MMA Dual Core(6) No
Graphics Processing Unit GPU Yes No Yes No
Video Encoder / Decoder VENC/VDEC Yes No
Motion JPEG Encoder JPEG Yes No

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Table 4-1. Device Comparison (continued)

REFERENCE
FEATURES(1) AM67A94 AM67A74 AM6754 AM6734
NAME
Depth and Motion Processing Accelerators DMPAC Yes No
Vision Processing Accelerators VPAC3L Yes No
SAFETY AND SECURITY
Safety Targeted Safety Optional(2)
Device Security Security Optional(3)
AEC-Q100 Qualified Q1 No
PROGRAM AND DATA STORAGE
On-Chip Shared Memory (RAM) in MAIN Domain OCSRAM 256KB
On-Chip Shared Memory (RAM) in MCU Domain MCU_MSRAM 512KB
LPDDR4 DDR Subsystem DDRSS 32-bit data with inline ECC up to 8GB
General-Purpose Memory Controller GPMC Up to 128MB with ECC
PERIPHERALS
1x DPI
Display Subsystem DSS7UL 1x LVDS
1x DSI
Modular Controller Area Network Interface MCAN 4
Full CAN-FD Support CAN-FD Yes
General-Purpose I/O GPIO Up to 147
Inter-Integrated Circuit Interface I2C 7
Multichannel Audio Serial Port MCASP 5
Multichannel Serial Peripheral Interface MCSPI 5
1x eMMC (8-bits)
Multi-Media Card/Secure Digital Interface MMC/SD
2x SD/SDIO (4-bits)
Flash Subsystem (FSS)(4) OSPI0/QSPI0 Yes(4)
Gigabit Ethernet Interface CPSW3G(5) 2 Ports (RGMII/RMII/SGMII(5))
General-Purpose Timers TIMER 14 (4 in MCU and 2 in WKUP)
Enhanced Pulse-Width Modulator Module EPWM 3
Enhanced Capture Module ECAP 3
Enhanced Quadrature Encoder Pulse Module EQEP 3
Universal Asynchronous Receiver and Transmitter UART 9
PCI Express Gen3 Port with Integrated PHY PCIe(5) Single Lane
CSI2-RX Controller with DPHY CSI-RX 4x4L
CSI2-TX Controller CSI-TX 1x4L
USB2.0 Controller with PHY USB 2.0 1
USB3.0 Controller with PHY USB 3.1 Gen 1(5) 1

(1) J722S is the base part number for the superset device. Software should constrain the features used to match the intended production
device.
(2) Safety features including SIL/ASIL ratings are only applicable to select part number variants as indicated by the Device Type (Y)
identifier in the Device Naming Convention table.
(3) Device security features including Secure Boot and Customer Programmable Keys are applicable to select part number variants as
indicated by the Device Type (Y) identifier in the Table 10-1, Nomenclature Description table
(4) One flash interface, configured as OSPI0 or QSPI0.
(5) PCIe, USB3.0 and SGMII share a total of 2 SERDES ports.
(6) On the AM67A SoC, the Deep Learning Accelerator C7x + MMA are reserved for executing TI provided code, and are not available for
custom code.

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5 Terminal Configuration and Functions

5.1 Pin Diagrams
Note
The terms "ball", "pin", and "terminal" are used interchangeably throughout the document. An attempt
is made to use "ball" only when referring to the physical package.

Figure 5-1 shows the ball locations for the 594-ball flip chip ball grid array (FCBGA) package to quickly locate
signal names and ball grid numbering. This figure is used in conjuction with Section 5.2.1 through Section 5.4
(Pin Attributes table and all Signal Descriptions tables, including the Pin Connectivity Requirements table).
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

WKUP WKUP MCU_OSC0 MCU_OSC0 PMIC_LPM MCU_SPI0 MCU_SPI0 SERDES1 SERDES1 SERDES0 SERDES0 SERDES0 SERDES0 EXT MCASP0 MCASP0
A VSS _LFOSC0 _LFOSC0 VSS VSS TCK VSS VSS I2C1_SDA MMC1_SDWP VSS
_XO _XI _XI _XO _EN0 _CLK _CS1 _TX0_N _TX0_P _REFCLK0P _REFCLK0N _RX0_P _RX0_N _REFCLK1 _AXR3 _AXR2

MCU_MCAN1 MCU_MCAN0 WKUP MCU_UART0 MCU_UART0 MCU MCU_UART0 WKUP_I2C0 MCU_SPI0 MCU_I2C0 SERDES1 SERDES1 SERDES0 SERDES0 UART0 MCASP0 USB1
B _UART0 RSVD16 TRSTn SPI0_CS0 I2C0_SDA EXTINTn MMC1_SDCD
_RX _TX _RXD _TXD _CTSn _ERRORn _RXD _SCL _D0 _SCL _REFCLK0N _REFCLK0P _TX0_P _TX0_N _RTSn _AXR1 _DRVVBUS

MCU_MCAN1 WKUP WKUP MCU_UART0 WKUP MCU_SPI0 MCU_SPI0 SERDES1 SERDES1 MCASP0 MCASP0
C VSS _UART0 _UART0 RSVD14 _UART0 EMU0 RSVD17 SPI0_CS1 MCAN0_RX VSS I2C1_SCL
_TX _RTSn _CTSn _RTSn _TXD _D1 _CS0 _RX0_N _RX0_P _AFSX _AFSR

MCU_MCAN0 MCU WKUP_I2C0 MCASP0

D VDDS_DDR DDR0_DQ1 DDR0_DQ3 DDR0_DQ0 RSVD20 RSVD19 RSVD18 USB1_DP SPI0_CLK MCAN0_TX I2C0_SCL VSS PORz_OUT
_RX _RESETz _SDA _ACLKX

MCU_I2C0 MCU_RESETS SERDES0 USB1 UART0 USB0 RESET RESETSTA

E DDR0_DQS0 DDR0_DQ5 VSS MCU_PORz RSVD0 TDI USB1_DM SPI0_D0 SPI0_D1
_SDA TATz _REXT _RCALIB _CTSn _DRVVBUS _REQz Tz

DDR0_DQS0 WKUP SERDES1 MCASP0 MCASP0 PCIE0

F VSS DDR0_DQ7 DDR0_DQ2 RSVD15 EMU1 TDO TMS VSS VSS VSS USB1_VBUS UART0_RXD UART0_TXD VSS MMC2_SDCD MMC2_CMD
_n _CLKOUT0 _REXT _AXR0 _ACLKR _CLKREQn

VMON_ER VDDA_1P8 VDDA_3P3

G VSS DDR0_DM0 VSS DDR0_DQ4 VSS DDR0_DQ6 VSS VPP VSS VDDA_MCU VSS VSS VSS VSS VDDSHV0 CAP_VDDS5 VSS MMC2_DAT0 MMC2_DAT1
_VSYS _SERDES _USB1

CAP_VDDS VDDSHV VDDSHV VDDA_0P85 VDDA_0P85 VDDA_CORE VDDA_1P8

H DDR0_DQS1 DDR0_DQ9 DDR0_DQ15 VSS DDR0_DQ8 DDR0_DM1 VSS VDDA_MCU VSS CAP_VDDS0 VDDSHV0 VDDSHV5 MMC1_DAT1 MMC2_SDWP MMC1_CMD MMC1_DAT0 MMC1_CLK MMC1_DAT3 MMC2_CLK MMC2_DAT2
_CANUART _CANUART _MCU _SERDES _SERDES _USB1 _USB1

DDR0_DQS1 VMON_1P8 VDD CAP_VDDS VDDA_0P85 OSPI0

J DDR0_DQ14 VSS DDR0_DQ13 VSS DDR0_DQ12 VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS CAP_VDDS6 VDDSHV6 MMC1_DAT2 VSS MMC2_DAT3
_n _SOC _CANUART _MCU _SERDES_C _CSn3

VMON_3P3 OSPI0 OSPI0 OSPI0

K VSS DDR0_DQ10 VDDS_OSC0 VDD_CORE VDDA_PLL1 VDD_CORE VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDDSHV1 OSPI0_D0
_SOC _CSn2 _CSn1 _CSn0

VDDA OSPI0
L DDR0_DQ11 DDR0_A5 DDR0_A3 DDR0_A0 RSVD10 DDR0_A1 VDDS_DDR VDDS_DDR VSS VSS VDD_CORE VSS VSS VDDA_PLL0 VSS VDD_CORE VSS CAP_VDDS1 VDDSHV1 OSPI0_D4 OSPI0_DQS OSPI0_CLK OSPI0_D3 OSPI0_D2 OSPI0_D1
_TEMP2 _LBCLKO

DDR0_RAS DDR0_CAS
M VSS RSVD21 DDR0_A2 RSVD11 VSS VSS VDD_CORE VDD_CORE VSS VDDA_PLL2 VDDR_CORE VSS VDD_CORE VSS VDD_CORE VSS VDDR_CORE VDDSHV3 OSPI0_D5 OSPI0_D7
_n _n

DDR0_CK0 GPMC0 GPMC0_OEn

N DDR0_A4 VDDS_DDR VDDS_DDR VSS VDD_CORE VDD_CORE VSS VDDR_CORE VDD_CORE VSS VDD_CORE VSS VDD_CORE VDDR_CORE CAP_VDDS3 GPMC0_WEn GPMC0_WPn GPMC0_DIR VSS OSPI0_D6
_n _ADVn_ALE _REn

DDR0_CS1 DDR0_CS0 VDDS_DDR VDDA_DDR GPMC0 GPMC0 GPMC0 GPMC0 GPMC0

P DDR0_CK0 DDR0_CKE0 VSS DDR0_CKE1 VSS VSS VDD_CORE VDD_CORE VSS VDD_CORE VSS VDDA_PLL5 VSS VDD_CORE VSS VDDSHV3
_n _n _C _PLL0 _CSn1 _CSn2 _CSn3 _BE1n _BE0n_CLE

GPMC0
R VSS DDR0_DQ17 DDR0_DQ20 VSS DDR0_DQ18 DDR0_CAL0 VSS VSS VDD_CORE VSS VDDA_PLL3 VDD_CORE VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VSS VDDSHV3 GPMC0_AD0 GPMC0_AD1 GPMC0_AD2
_CSn0

VDDA
T DDR0_DQS2 DDR0_DQ19 VDDS_DDR VDDS_DDR VDD_CORE VSS VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VSS VDDSHV2 VDDSHV2 GPMC0_AD6 GPMC0_AD7 GPMC0_CLK GPMC0_AD5 GPMC0_AD4 VSS GPMC0_AD3
_TEMP1

DDR0_DQS2 DDR0
U DDR0_DQ21 VSS DDR0_DM2 DDR0_DQ22 VSS VDD_CORE VSS VDDR_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VDDR_CORE VSS VSS CAP_VDDS2 GPMC0_AD9 GPMC0_AD8
_n _RESET0_n

GPMC0 GPMC0 GPMC0 GPMC0 GPMC0 GPMC0 GPMC0

V VSS DDR0_DQ23 DDR0_DQ16 VSS DDR0_DQ26 DDR0_DQ28 VSS VDD_CORE VSS VDDR_CORE VSS VDD_CORE VSS VDD_CORE VSS VDD_CORE VDDR_CORE VDDA_PLL4 VDD_CORE VSS
_WAIT0 _AD14 _AD15 _AD13 _AD11 _AD12 _AD10

VDDA_0P85 VDDA_CORE VDDA_1P8 VDDA_CORE VDDA_1P8 VDDA_1P8 VOUT0 VOUT0 VOUT0 VOUT0 VOUT0 GPMC0 VOUT0
W DDR0_DQS3 DDR0_DQ27 DDR0_DQ29 DDR0_DQ25 VSS USB0_VBUS VSS VDD_MMC0 VSS VSS VSS VDD_CORE VSS
_DLL_MMC0 _USB0 _CSI_DSI _CSI_DSI _CSI_DSI _OLDI0 _DATA5 _DATA4 _DATA3 _DATA2 _DATA1 _WAIT1 _DATA0

DDR0_DQS3 VDDA_3P3 VDDA_1P8 VDDA_1P8 VDDA_CORE VDDA_CORE VDDA VDDA_1P8 VOUT0 VOUT0
Y DDR0_DQ24 VSS VSS VDDS_MMC0 VSS VSS _CSI_DSI VSS VDD_CORE VDD_CORE
_n _USB0 _USB0 _CSI_DSI _CSI_DSI _CLK _TEMP0 _OLDI0 _DATA6 _DATA7

USB0 CSI1 DSI0 VOUT0 VOUT0 VOUT0 VOUT0 VOUT0

AA VSS DDR0_DM3 DDR0_DQ30 VSS DDR0_DQ31 USB0_DP RSVD5 RSVD9 RSVD8 VSS RSVD1 OLDI0_A7P VSS VSS
_RCALIB _RXRCALIB _TXRCALIB _DATA13 _DATA12 _DATA8 _DATA10 _DATA9

CSI0 CSI2 CSI3 VOUT0 VOUT0 VOUT0 VOUT0 VOUT0

AB VDDS_DDR MMC0_DAT7 MMC0_DAT5 MMC0_DAT2 USB0_DM RSVD2 RSVD4 RSVD6 RSVD7 RSVD12 RSVD13 OLDI0_A7N OLDI0_A2N OLDI0_A2P
_RXRCALIB _RXRCALIB _RXRCALIB _VSYNC _HSYNC _DATA11 _DATA14 _DATA15

MMC0 CSI0 CSI0 RGMII1 VOUT0

AC MMC0_DAT3 MMC0_DAT4 RSVD3 CSI1_RXP3 CSI1_RXN3 CSI2_RXP3 CSI2_RXN3 CSI3_RXN3 CSI3_RXP3 DSI0_TXN3 DSI0_TXP3 OLDI0_A4P MDIO0_MDC VOUT0_DE
_CALPAD _RXCLKP _RXCLKN _RD0 _PCLK

OLDI0 RGMII1_RX MDIO0 RGMII1

AD MMC0_DS MMC0_DAT1 MMC0_DAT0 CSI0_RXP0 CSI0_RXN0 CSI1_RXP2 CSI1_RXN2 CSI2_RXN2 CSI2_RXP2 CSI3_RXP2 CSI3_RXN2 DSI0_TXN0 DSI0_TXP0 OLDI0_A4N VSS
_CLK1N _CTL _MDIO _RD1

DSI0 DSI0 OLDI0 OLDI0 RGMII1 RGMII1 RGMII1 RGMII1

AE MMC0_CLK MMC0_CMD CSI0_RXP1 CSI0_RXN1 CSI1_RXP1 CSI1_RXN1 CSI2_RXN1 CSI2_RXP1 CSI3_RXP1 CSI3_RXN1
_TXCLKN _TXCLKP _CLK1P _CLK0P _TD1 _RD2 _RD3 _RXC

OLDI0 RGMII1 RGMII1_TX RGMII1

AF MMC0_DAT6 CSI0_RXP2 CSI0_RXN2 CSI1_RXP0 CSI1_RXN0 CSI2_RXN0 CSI2_RXP0 CSI3_RXP0 CSI3_RXN0 DSI0_TXN1 DSI0_TXP1 OLDI0_A5P OLDI0_A5N OLDI0_A0N
_CLK0N _TD3 _CTL _TD0

CSI1 CSI1 CSI2 CSI2 CSI3 CSI3 RGMII1 RGMII1

AG VSS CSI0_RXP3 CSI0_RXN3 DSI0_TXN2 DSI0_TXP2 OLDI0_A6N OLDI0_A6P OLDI0_A3N OLDI0_A3P OLDI0_A1N OLDI0_A1P OLDI0_A0P VSS
_RXCLKP _RXCLKN _RXCLKN _RXCLKP _RXCLKP _RXCLKN _TD2 _TXC

Not to scale

Figure 5-1. AMW FCBGA-N594 Pin Diagram (Top View)

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5.2 Pin Attributes

The following list describes the contents of each column in the Table 5-1, Pin Attributes (AMW Package) table:
1. BALL NUMBER: Ball numbers assigned to each terminal of the Ball Grid Array package.
2. BALL NAME: Ball name assigned to each terminal of the Ball Grid Array package (this name is typically
taken from the primary MUXMODE 0 signal function).
3. SIGNAL NAME: Signal name(s) of all dedicated and pin multiplexed signal functions associated with a ball.

Note
Many device pins support multiple signal functions. Some signal functions are selected via a single
layer of multiplexers associated with pins. Other signal functions are selected via two or more layers
of multiplexers, where one layer is associated with the pins and other layers are associated with
peripheral logic functions.
The Table 5-1, Pin Attributes (AMW Package) table only defines signal multiplexing at the pins. For
more information, related to signal multiplexing at the pins, see Pad Configuration Registers section
in Device Configuration chapter of the device TRM. Refer to the respective peripheral chapter in the
device TRM for information associated with peripheral signal multiplexing.

4. MUX MODE: The MUXMODE value associated with each pin multiplexed signal function:
a. MUXMODE 0 is the primary pin multiplexed signal function. However, the primary pin multiplexed signal
function is not necessarily the default pin multiplexed signal function.

Note
The value found in the MUX MODE AFTER RESET column defines the default pin multiplexed
signal function selected when MCU_PORz is deasserted.

a. MUXMODE values 1 through 15 are possible for pin multiplexed signal functions. However, not all
MUXMODE values have been implemented. The only valid MUXMODE values are those defined as pin
multiplexed signal functions within the Pin Attributes table. Only valid values of MUXMODE should be
used.
b. Bootstrap defines SOC configuration pins, where the logic state applied to each pin is latched on the
rising edge of PORz_OUT. These input signal functions are fixed to their respective pins and are not
programable via MUXMODE.
c. An empty box means Not Applicable.

Note
The following configurations of MUXMODE must be avoided for proper device operation.
• Configuring multiple pins operating as inputs to the same pin multiplexed signal function is not
supported as it can yield unexpected results.
• Configuring a pin to an undefined pin multiplexing mode will cause the pin behavior to be
undefined.

5. TYPE: Signal type and direction:

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• PWR = Power
• GND = Ground
• CAP = LDO Capacitor.
6. DSIS: The deselected input state (DSIS) indicates the state driven to the subsystem input (logic "0", logic
"1", or "pad" level) when the pin multiplexed signal function is not selected by MUXMODE.
• 0: Logic 0 driven to the subsystem input.
• 1: Logic 1 driven to the subsystem input.
• pad: Logic state of the pad is driven to the subsystem input.
• An empty box means Not Applicable.
7. BALL STATE DURING RESET (RX/TX/PULL): State of the terminal while MCU_PORz is asserted, where
RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state
of internal pull resistors:
• RX (Input buffer)
– Off: The input buffer is disabled.
– On: The input buffer is enabled.
• TX (Output buffer)
– Off: The output buffer is disabled.
– Low: The output buffer is enabled and drives VOL.
• PULL (Internal pull resistors)
– Off: Internal pull resistors are turned off.
– Up: Internal pull-up resistor is turned on.
– Down: Internal pull-down resistor is turned on.
– NA: Not Applicable.
• An empty box means Not Applicable.
8. BALL STATE AFTER RESET (RX/TX/PULL): State of the terminal after MCU_PORz is deasserted, where
RX defines the state of the input buffer, TX defines the state of the output buffer, and PULL defines the state
of internal pull resistors:
• RX (Input buffer)
– Off: The input buffer is disabled.
– On: The input buffer is enabled.
• TX (Output buffer)
– Off: The output buffer is disabled.
– SS: The subsystem selected with MUXMODE determines the output buffer state.
• PULL (Internal pull resistors)
– Off: Internal pull resistors are turned off.
– Up: Internal pull-up resistor is turned on.
– Down: Internal pull-down resistor is turned on.
– NA: Not Applicable.
• An empty box means Not Applicable.
9. MUX MODE AFTER RESET: The value found in this column defines the default pin multiplexed signal
function after MCU_PORz is deasserted.
An empty box means Not Applicable.
10. I/O VOLTAGE VALUE: This column describes I/O operating voltage options of the respective power supply,
when applicable.
An empty box means Not Applicable.
For more information, see valid operating voltage range(s) defined for each power supply in Section 6.4,
Recommended Operating Conditions.
11. POWER: The power supply of the associated I/O, when applicable.

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An empty box means Not Applicable.

12. HYS: Indicates if the input buffer associated with this I/O has hysteresis:
• Yes: With hysteresis
• No: Without hysteresis
• An empty box means Not Applicable.
For more information, see the hysteresis values in Section 6.6, Electrical Characteristics.
13. BUFFER TYPE: This column defines the buffer type associated with a terminal. This information can be
used to determine which Electrical Characteristics table is applicable.
An empty box means Not Applicable.
For electrical characteristics, refer to the appropriate buffer type table in Section 6.6, Electrical
Characteristics.
14. PULL UP/DOWN TYPE: Indicates the presence of an internal pullup or pulldown resistor. Pullup and
pulldown resistors can be enabled or disabled via software.
• PU: Internal pull-up
• PD: Internal pull-down
• PU/PD: Internal pull-up and pull-down
• An empty box means No internal pull.
15. PADCONFIG Register: Name of the IO pad configuration register associated with Ball.
16. PADCONFIG Address: Physical address of the IO pad configuration register associated with Ball.

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Table 5-1. Pin Attributes (AMW Package)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
H17 CAP_VDDS0 CAP_VDDS0 CAP
L19 CAP_VDDS1 CAP_VDDS1 CAP
U20 CAP_VDDS2 CAP_VDDS2 CAP
N20 CAP_VDDS3 CAP_VDDS3 CAP
G19 CAP_VDDS5 CAP_VDDS5 CAP
J20 CAP_VDDS6 CAP_VDDS6 CAP
H8 CAP_VDDS_CANUART CAP_VDDS_CANUART CAP
J10 CAP_VDDS_MCU CAP_VDDS_MCU CAP
AC7 CSI0_RXCLKN CSI0_RXCLKN I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AC6 CSI0_RXCLKP CSI0_RXCLKP I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AB8 CSI0_RXRCALIB CSI0_RXRCALIB A 1.8 V VDDA_1P8_CSI_DSI D-PHY
AG6 CSI1_RXCLKN CSI1_RXCLKN I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AG5 CSI1_RXCLKP CSI1_RXCLKP I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AA10 CSI1_RXRCALIB CSI1_RXRCALIB A 1.8 V VDDA_1P8_CSI_DSI D-PHY
AG8 CSI2_RXCLKN CSI2_RXCLKN I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AG9 CSI2_RXCLKP CSI2_RXCLKP I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AB14 CSI2_RXRCALIB CSI2_RXRCALIB A 1.8 V VDDA_1P8_CSI_DSI D-PHY
AG12 CSI3_RXCLKN CSI3_RXCLKN I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AG11 CSI3_RXCLKP CSI3_RXCLKP I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AB15 CSI3_RXRCALIB CSI3_RXRCALIB A 1.8 V VDDA_1P8_CSI_DSI D-PHY
AD6 CSI0_RXN0 CSI0_RXN0 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AE5 CSI0_RXN1 CSI0_RXN1 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AF4 CSI0_RXN2 CSI0_RXN2 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AG3 CSI0_RXN3 CSI0_RXN3 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AD5 CSI0_RXP0 CSI0_RXP0 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AE4 CSI0_RXP1 CSI0_RXP1 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AF3 CSI0_RXP2 CSI0_RXP2 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AG2 CSI0_RXP3 CSI0_RXP3 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AF7 CSI1_RXN0 CSI1_RXN0 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AE8 CSI1_RXN1 CSI1_RXN1 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AD9 CSI1_RXN2 CSI1_RXN2 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AC10 CSI1_RXN3 CSI1_RXN3 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AF6 CSI1_RXP0 CSI1_RXP0 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AE7 CSI1_RXP1 CSI1_RXP1 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AD8 CSI1_RXP2 CSI1_RXP2 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AC9 CSI1_RXP3 CSI1_RXP3 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AF9 CSI2_RXN0 CSI2_RXN0 I 1.8 V VDDA_1P8_CSI_DSI D-PHY

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
AE10 CSI2_RXN1 CSI2_RXN1 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AD11 CSI2_RXN2 CSI2_RXN2 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AC13 CSI2_RXN3 CSI2_RXN3 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AF10 CSI2_RXP0 CSI2_RXP0 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AE11 CSI2_RXP1 CSI2_RXP1 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AD12 CSI2_RXP2 CSI2_RXP2 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AC12 CSI2_RXP3 CSI2_RXP3 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AF13 CSI3_RXN0 CSI3_RXN0 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AE14 CSI3_RXN1 CSI3_RXN1 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AD15 CSI3_RXN2 CSI3_RXN2 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AC15 CSI3_RXN3 CSI3_RXN3 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AF12 CSI3_RXP0 CSI3_RXP0 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AE13 CSI3_RXP1 CSI3_RXP1 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AD14 CSI3_RXP2 CSI3_RXP2 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
AC16 CSI3_RXP3 CSI3_RXP3 I 1.8 V VDDA_1P8_CSI_DSI D-PHY
VDDS_DDR,
M4 DDR0_CAS_n DDR0_CAS_n O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
M3 DDR0_RAS_n DDR0_RAS_n O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
L4 DDR0_A0 DDR0_A0 O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
L6 DDR0_A1 DDR0_A1 O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
M5 DDR0_A2 DDR0_A2 O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
L3 DDR0_A3 DDR0_A3 O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
N2 DDR0_A4 DDR0_A4 O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
L2 DDR0_A5 DDR0_A5 O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
R6 DDR0_CAL0 DDR0_CAL0 A 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
P1 DDR0_CK0 DDR0_CK0 O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
N1 DDR0_CK0_n DDR0_CK0_n O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
P2 DDR0_CKE0 DDR0_CKE0 O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
P6 DDR0_CKE1 DDR0_CKE1 O 1.1 V/1.2 V DDR
VDDS_DDR_C

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
VDDS_DDR,
P4 DDR0_CS0_n DDR0_CS0_n O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
P3 DDR0_CS1_n DDR0_CS1_n O 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
G2 DDR0_DM0 DDR0_DM0 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
H6 DDR0_DM1 DDR0_DM1 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
U4 DDR0_DM2 DDR0_DM2 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
AA2 DDR0_DM3 DDR0_DM3 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
D6 DDR0_DQ0 DDR0_DQ0 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
D2 DDR0_DQ1 DDR0_DQ1 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
F6 DDR0_DQ2 DDR0_DQ2 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
D3 DDR0_DQ3 DDR0_DQ3 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
G4 DDR0_DQ4 DDR0_DQ4 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
E2 DDR0_DQ5 DDR0_DQ5 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
G6 DDR0_DQ6 DDR0_DQ6 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
F3 DDR0_DQ7 DDR0_DQ7 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
H5 DDR0_DQ8 DDR0_DQ8 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
H2 DDR0_DQ9 DDR0_DQ9 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
K2 DDR0_DQ10 DDR0_DQ10 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
L1 DDR0_DQ11 DDR0_DQ11 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
J6 DDR0_DQ12 DDR0_DQ12 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
J4 DDR0_DQ13 DDR0_DQ13 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
J2 DDR0_DQ14 DDR0_DQ14 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
H3 DDR0_DQ15 DDR0_DQ15 IO 1.1 V/1.2 V DDR
VDDS_DDR_C

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
VDDS_DDR,
V3 DDR0_DQ16 DDR0_DQ16 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
R2 DDR0_DQ17 DDR0_DQ17 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
R5 DDR0_DQ18 DDR0_DQ18 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
T2 DDR0_DQ19 DDR0_DQ19 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
R3 DDR0_DQ20 DDR0_DQ20 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
U2 DDR0_DQ21 DDR0_DQ21 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
U5 DDR0_DQ22 DDR0_DQ22 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
V2 DDR0_DQ23 DDR0_DQ23 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
Y2 DDR0_DQ24 DDR0_DQ24 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
W4 DDR0_DQ25 DDR0_DQ25 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
V5 DDR0_DQ26 DDR0_DQ26 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
W2 DDR0_DQ27 DDR0_DQ27 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
V6 DDR0_DQ28 DDR0_DQ28 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
W3 DDR0_DQ29 DDR0_DQ29 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
AA3 DDR0_DQ30 DDR0_DQ30 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
AA5 DDR0_DQ31 DDR0_DQ31 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
E1 DDR0_DQS0 DDR0_DQS0 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
F1 DDR0_DQS0_n DDR0_DQS0_n IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
H1 DDR0_DQS1 DDR0_DQS1 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
J1 DDR0_DQS1_n DDR0_DQS1_n IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
T1 DDR0_DQS2 DDR0_DQS2 IO 1.1 V/1.2 V DDR
VDDS_DDR_C
VDDS_DDR,
U1 DDR0_DQS2_n DDR0_DQS2_n IO 1.1 V/1.2 V DDR
VDDS_DDR_C

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Table 5-1. Pin Attributes (AMW Package) (continued)

C9 PADCONFIG EMU0 0 IO 0 On / Off / Up On / Off / Up 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG30
0x04084078
EMU1

F9 PADCONFIG EMU1 0 IO 0 On / Off / Up On / Off / Up 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG31
0x0408407C
EXTINTn EXTINTn 0 I 1
PADCONFIG I2C OPEN
B23 Off / Off / NA Off / Off / NA 7 1.8 V/3.3 V VDDSHV0 Yes
PADCONFIG125 GPIO1_31 7 IOD pad DRAIN
0x000F41F4
EXT_REFCLK1 0 I 0
SYNC1_OUT 1 O
SPI2_CS3 2 IO 1
EXT_REFCLK1 SYSCLKOUT0 3 O
A23 PADCONFIG TIMER_IO4 4 IO 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG124
0x000F41F0 CLKOUT0 5 O
CP_GEMAC_CPTS0_RFT_CLK 6 I 0
GPIO1_30 7 IO pad
ECAP0_IN_APWM_OUT 8 IO 0

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
GPMC0_ADVn_ALE 0 O
GPMC0_ADVn_ALE
MCASP1_AXR2 2 IO 0
N21 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG33 TRC_DATA7 6 O
0x000F4084
GPIO0_32 7 IO pad
GPMC0_CLK 0 O
GPMC0_CLK MCASP1_AXR3 2 IO 0
T23 PADCONFIG GPMC0_FCLK_MUX 3 O Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG31
0x000F407C TRC_DATA6 6 O
GPIO0_31 7 IO pad
GPMC0_DIR 0 O
MCASP2_AXR13 3 IO 0
GPMC0_DIR
MAIN_ERRORn 5 IO 1
N25 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG41 TRC_DATA14 6 O
0x000F40A4
GPIO0_40 7 IO pad
EQEP2_S 8 IO 0
GPMC0_OEn_REn 0 O
GPMC0_OEn_REn
MCASP1_AXR1 2 IO 0
N22 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG34 TRC_DATA8 6 O
0x000F4088
GPIO0_33 7 IO pad
GPMC0_WEn 0 O
GPMC0_WEn
MCASP1_AXR0 2 IO 0
N23 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG35 TRC_DATA9 6 O
0x000F408C
GPIO0_34 7 IO pad
GPMC0_WPn 0 O
AUDIO_EXT_REFCLK1 1 IO 0
GPMC0_WPn
GPMC0_A22 2 OZ
N24 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG40 UART6_TXD 3 O
0x000F40A0
TRC_DATA13 6 O
GPIO0_39 7 IO pad
GPMC0_AD0 0 IO 0
GPMC0_AD0 MCASP2_AXR4 3 IO 0
R22 PADCONFIG TRC_CLK 6 O On / Off / Off On / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG15
0x000F403C GPIO0_15 7 IO pad
BOOTMODE00 Bootstrap I

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
GPMC0_AD1 0 IO 0
GPMC0_AD1 MCASP2_AXR5 3 IO 0
R23 PADCONFIG TRC_CTL 6 O On / Off / Off On / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG16
0x000F4040 GPIO0_16 7 IO pad
BOOTMODE01 Bootstrap I
GPMC0_AD2 0 IO 0
GPMC0_AD2 MCASP2_AXR6 3 IO 0
R26 PADCONFIG TRC_DATA0 6 O On / Off / Off On / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG17
0x000F4044 GPIO0_17 7 IO pad
BOOTMODE02 Bootstrap I
GPMC0_AD3 0 IO 0
GPMC0_AD3 MCASP2_AXR7 3 IO 0
T27 PADCONFIG TRC_DATA1 6 O On / Off / Off On / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG18
0x000F4048 GPIO0_18 7 IO pad
BOOTMODE03 Bootstrap I
GPMC0_AD4 0 IO 0
GPMC0_AD4 MCASP2_AXR8 3 IO 0
T25 PADCONFIG TRC_DATA2 6 O On / Off / Off On / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG19
0x000F404C GPIO0_19 7 IO pad
BOOTMODE04 Bootstrap I
GPMC0_AD5 0 IO 0
GPMC0_AD5 MCASP2_AXR9 3 IO 0
T24 PADCONFIG TRC_DATA3 6 O On / Off / Off On / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG20
0x000F4050 GPIO0_20 7 IO pad
BOOTMODE05 Bootstrap I
GPMC0_AD6 0 IO 0
GPMC0_AD6 MCASP2_AXR10 3 IO 0
T21 PADCONFIG TRC_DATA4 6 O On / Off / Off On / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG21
0x000F4054 GPIO0_21 7 IO pad
BOOTMODE06 Bootstrap I
GPMC0_AD7 0 IO 0
GPMC0_AD7 MCASP2_AXR11 3 IO 0
T22 PADCONFIG TRC_DATA5 6 O On / Off / Off On / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG22
0x000F4058 GPIO0_22 7 IO pad
BOOTMODE07 Bootstrap I

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Table 5-1. Pin Attributes (AMW Package) (continued)

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Table 5-1. Pin Attributes (AMW Package) (continued)

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Table 5-1. Pin Attributes (AMW Package) (continued)

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Table 5-1. Pin Attributes (AMW Package) (continued)

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Table 5-1. Pin Attributes (AMW Package) (continued)

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
MCASP0_ACLKX 0 IO 0
MCASP0_ACLKX SPI2_CS1 1 IO 1
D25 PADCONFIG ECAP2_IN_APWM_OUT 2 IO 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG105
0x000F41A4 GPIO1_11 7 IO pad
EQEP1_A 8 I 0
MCASP0_AFSR 0 IO 0
SPI2_CS0 1 IO 1
MCASP0_AFSR
UART1_RXD 2 I 1
C27 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG107 EHRPWM0_A 6 IO 0
0x000F41AC
GPIO1_13 7 IO pad
EQEP1_S 8 IO 0
MCASP0_AFSX 0 IO 0
MCASP0_AFSX SPI2_CS3 1 IO 1
C26 PADCONFIG AUDIO_EXT_REFCLK1 2 IO 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG106
0x000F41A8 GPIO1_12 7 IO pad
EQEP1_B 8 I 0
MCASP0_AXR0 0 IO 0
MCASP0_AXR0 AUDIO_EXT_REFCLK0 2 IO 0
F23 PADCONFIG EHRPWM1_B 6 IO 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG104
0x000F41A0 GPIO1_10 7 IO pad
EQEP0_I 8 IO 0
MCASP0_AXR1 0 IO 0
SPI2_CS2 1 IO 1
MCASP0_AXR1 ECAP1_IN_APWM_OUT 2 IO 0
B25 PADCONFIG MAIN_ERRORn 5 IO 1 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG103
0x000F419C EHRPWM1_A 6 IO 0
GPIO1_9 7 IO pad
EQEP0_S 8 IO 0
MCASP0_AXR2 0 IO 0
SPI2_D1 1 IO 0
MCASP0_AXR2 UART1_RTSn 2 O
A26 PADCONFIG UART6_TXD 3 O Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG102
0x000F4198 ECAP2_IN_APWM_OUT 5 IO 0
GPIO1_8 7 IO pad
EQEP0_B 8 I 0

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Table 5-1. Pin Attributes (AMW Package) (continued)

B7 PADCONFIG MCU_ERRORn 0 IO Off / Off / Down On / SS / Down 0 1.8 V VDDS_OSC0 Yes LVCMOS PU/PD
MCU_PADCONFIG24
0x04084060
MCU_I2C0_SCL MCU_I2C0_SCL 0 IOD 1
PADCONFIG I2C OPEN
B13 Off / Off / NA On / SS / NA 7 1.8 V/3.3 V VDDSHV_MCU Yes
MCU_PADCONFIG17 MCU_GPIO0_17 7 IOD pad DRAIN
0x04084044
MCU_I2C0_SDA MCU_I2C0_SDA 0 IOD 1
PADCONFIG I2C OPEN
E11 Off / Off / NA On / SS / NA 7 1.8 V/3.3 V VDDSHV_MCU Yes
MCU_PADCONFIG18 MCU_GPIO0_18 7 IOD pad DRAIN
0x04084048
MCU_MCAN0_RX 0 I 1
MCU_MCAN0_RX
MCU_TIMER_IO0 1 IO 0
D8 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG14 MCU_SPI1_CS3 2 IO 1
0x04084038
MCU_GPIO0_14 7 IO pad
MCU_MCAN0_TX 0 O
MCU_MCAN0_TX
WKUP_TIMER_IO0 1 IO 0
B2 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG13 MCU_SPI0_CS3 2 IO 1
0x04084034
MCU_GPIO0_13 7 IO pad
MCU_MCAN1_RX 0 I 1
MCU_TIMER_IO3 1 IO 0
MCU_MCAN1_RX
MCU_SPI0_CS2 2 IO 1
B1 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG16 MCU_SPI1_CS2 3 IO 1
0x04084040
MCU_SPI1_CLK 4 IO 0
MCU_GPIO0_16 7 IO pad
MCU_MCAN1_TX 0 O
MCU_MCAN1_TX MCU_TIMER_IO2 1 IO 0
C1 PADCONFIG MCU_SPI1_CS1 3 IO 1 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG15
0x0408403C MCU_EXT_REFCLK0 4 I 0
MCU_GPIO0_15 7 IO pad
A5 MCU_OSC0_XI MCU_OSC0_XI I 1.8 V VDDS_OSC0 Yes HFXOSC

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Table 5-1. Pin Attributes (AMW Package) (continued)

E8 PADCONFIG MCU_PORz 0 I 0 1.8 V VDDS_OSC0 Yes FS_RESET

MCU_PADCONFIG22
0x04084058
MCU_RESETSTATz MCU_RESETSTATz 0 O

E13 PADCONFIG Off / Low / Off Off / SS / Off 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG23 MCU_GPIO0_21 7 IO pad
0x0408405C
MCU_RESETz

D10 PADCONFIG MCU_RESETz 0 I On / Off / Up On / Off / Up 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG21
0x04084054
MCU_SPI0_CLK MCU_SPI0_CLK 0 IO 0

A9 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG2 MCU_GPIO0_2 7 IO pad
0x04084008
MCU_SPI0_CS0 MCU_SPI0_CS0 0 IO 1

C12 PADCONFIG WKUP_TIMER_IO1 4 IO 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG0
0x04084000 MCU_GPIO0_0 7 IO pad

MCU_SPI0_CS1 0 IO 1
MCU_OBSCLK0 1 O
MCU_SPI0_CS1
MCU_SYSCLKOUT0 2 O
A10 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG1 MCU_EXT_REFCLK0 3 I 0
0x04084004
MCU_TIMER_IO1 4 IO 0
MCU_GPIO0_1 7 IO pad
MCU_SPI0_D0 MCU_SPI0_D0 0 IO 0

B12 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG3 MCU_GPIO0_3 7 IO pad
0x0408400C
MCU_SPI0_D1 MCU_SPI0_D1 0 IO 0

C11 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG4 MCU_GPIO0_4 7 IO pad
0x04084010
MCU_UART0_CTSn 0 I 1
MCU_UART0_CTSn
MCU_TIMER_IO0 1 IO 0
B5 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG7 MCU_SPI1_D0 3 IO 0
0x0408401C
MCU_GPIO0_7 7 IO pad
MCU_UART0_RTSn 0 O
MCU_UART0_RTSn
MCU_TIMER_IO1 1 IO 0
C5 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG8 MCU_SPI1_D1 3 IO 0
0x04084020
MCU_GPIO0_8 7 IO pad

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Table 5-1. Pin Attributes (AMW Package) (continued)

B8 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG5 MCU_GPIO0_5 7 IO pad
0x04084014
MCU_UART0_TXD MCU_UART0_TXD 0 O

B4 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG6 MCU_GPIO0_6 7 IO pad
0x04084018
MDIO0_MDC MDIO0_MDC 0 O

AC24 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG88 GPIO0_86 7 IO pad
0x000F4160
MDIO0_MDIO MDIO0_MDIO 0 IO 0

AD25 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG87 GPIO0_85 7 IO pad
0x000F415C
AC1 MMC0_CALPAD MMC0_CALPAD A 1.8 V VDDS_MMC0 eMMCPHY
AE1 MMC0_CLK MMC0_CLK IO 0 On / Low / Off On / SS / Off 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AE2 MMC0_CMD MMC0_CMD IO 1 On / Off / Up On / SS / Up 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AD1 MMC0_DS MMC0_DS IO 1 On / Off / Down On / Off / Down 1.8 V VDDS_MMC0 eMMCPHY PU/PD
MMC1_CLK 0 IO 0
TIMER_IO4 2 IO 0
MMC1_CLK
UART3_RXD 3 IO 0
H24 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD
PADCONFIG141 SPI1_CS0 5 IO 0
0x000F4234
SPI2_CS2 6 IO 0
GPIO1_46 7 IO 0
MMC1_CMD 0 IO 1
TIMER_IO5 2 IO 1
MMC1_CMD
UART3_TXD 3 IO 1
H22 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD
PADCONFIG143 SPI1_CLK 5 IO 1
0x000F423C
SPI2_CS0 6 IO 1
GPIO1_47 7 IO 1
MMC1_SDCD 0 I 0
UART6_RXD 1 I 0
TIMER_IO6 2 I 0
MMC1_SDCD
UART3_RTSn 3 I 0
B24 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG144 MCAN1_TX 4 I 0
0x000F4240
SPI1_CS3 5 I 0
SPI2_CLK 6 I 0
GPIO1_48 7 I 0

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
MMC1_SDWP 0 I 0
UART6_TXD 1 I 0
MMC1_SDWP TIMER_IO7 2 I 0
A24 PADCONFIG UART3_CTSn 3 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG145
0x000F4244 MCAN1_RX 4 I 0
SPI1_CS1 5 I 0
GPIO1_49 7 I 0
MMC2_CLK 0 IO 0
MCASP1_ACLKR 1 IO 0
MMC2_CLK MCASP1_AXR5 2 IO 0
H26 PADCONFIG UART6_RXD 3 I 1 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD
PADCONFIG70
0x000F4118 EHRPWM0_SYNCI 4 I 0
I2C3_SCL 6 IOD 1
GPIO0_69 7 IO pad
MMC2_CMD 0 IO 1
MCASP1_AFSR 1 IO 0
MCASP1_AXR4 2 IO 0
MMC2_CMD
UART6_TXD 3 O
F27 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV6 Yes SDIO PU/PD
PADCONFIG72 EHRPWM0_SYNCO 4 O
0x000F4120
EHRPWM_TZn_IN0 5 I 0
I2C3_SDA 6 IOD 1
GPIO0_70 7 IO pad
MMC2_SDCD 0 I 0
MCASP1_ACLKX 1 IO 0
MMC2_SDCD
UART4_RXD 3 I 1
F26 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV6 Yes LVCMOS PU/PD
PADCONFIG73 EHRPWM2_A 4 IO 0
0x000F4124
EHRPWM_TZn_IN1 5 I 0
GPIO0_71 7 IO pad
MMC2_SDWP 0 I 0
MCASP1_AFSX 1 IO 0
MMC2_SDWP
UART4_TXD 3 O
H21 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV6 Yes LVCMOS PU/PD
PADCONFIG74 EHRPWM2_B 4 IO 0
0x000F4128
EHRPWM_TZn_IN2 5 I 0
GPIO0_72 7 IO pad
AD3 MMC0_DAT0 MMC0_DAT0 IO 1 On / Off / Up On / SS / Up 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AD2 MMC0_DAT1 MMC0_DAT1 IO 1 On / Off / Up On / SS / Up 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AB4 MMC0_DAT2 MMC0_DAT2 IO 1 On / Off / Up On / SS / Up 1.8 V VDDS_MMC0 eMMCPHY PU/PD

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
AC2 MMC0_DAT3 MMC0_DAT3 IO 1 On / Off / Up On / SS / Up 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AC3 MMC0_DAT4 MMC0_DAT4 IO 1 On / Off / Up On / SS / Up 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AB3 MMC0_DAT5 MMC0_DAT5 IO 1 On / Off / Up On / SS / Up 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AF1 MMC0_DAT6 MMC0_DAT6 IO 1 On / Off / Up On / SS / Up 1.8 V VDDS_MMC0 eMMCPHY PU/PD
AB2 MMC0_DAT7 MMC0_DAT7 IO 1 On / Off / Up On / SS / Up 1.8 V VDDS_MMC0 eMMCPHY PU/PD
MMC1_DAT0 0 IO 1
CP_GEMAC_CPTS0_HW2TSPUSH 1 IO 1
MMC1_DAT0 TIMER_IO3 2 IO 1
H23 PADCONFIG UART2_CTSn 3 IO 1 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD
PADCONFIG140
0x000F4230 ECAP2_IN_APWM_OUT 4 IO 1
SPI2_D1 6 IO 1
GPIO1_45 7 IO 1
MMC1_DAT1 0 IO 1
CP_GEMAC_CPTS0_HW1TSPUSH 1 IO 1
TIMER_IO2 2 IO 1
MMC1_DAT1
UART2_RTSn 3 IO 1
H20 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD
PADCONFIG139 ECAP1_IN_APWM_OUT 4 IO 1
0x000F422C
SPI1_CS2 5 IO 1
SPI2_D0 6 IO 1
GPIO1_44 7 IO 1
MMC1_DAT2 0 IO 1
CP_GEMAC_CPTS0_TS_SYNC 1 IO 1
TIMER_IO1 2 IO 1
MMC1_DAT2
UART2_TXD 3 IO 1
J23 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD
PADCONFIG138 MCAN1_RX 4 IO 1
0x000F4228
SPI1_D1 5 IO 1
SPI2_CS3 6 IO 1
GPIO1_43 7 IO 1
MMC1_DAT3 0 IO 1
CP_GEMAC_CPTS0_TS_COMP 1 IO 1
TIMER_IO0 2 IO 1
MMC1_DAT3
UART2_RXD 3 IO 1
H25 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV5 Yes SDIO PU/PD
PADCONFIG137 MCAN1_TX 4 IO 1
0x000F4224
SPI1_D0 5 IO 1
SPI2_CS1 6 IO 1
GPIO1_42 7 IO 1

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Table 5-1. Pin Attributes (AMW Package) (continued)

AF23 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG152 GPIO1_53 7 IO pad
0x000F4260
OLDI0_A0P OLDI0_A0P 0 IO 0

AG24 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG151 GPIO1_52 7 IO pad
0x000F425C
OLDI0_A1N OLDI0_A1N 0 IO 0

AG22 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG154 GPIO1_55 7 IO pad
0x000F4268

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Table 5-1. Pin Attributes (AMW Package) (continued)

AG23 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG153 GPIO1_54 7 IO pad
0x000F4264
OLDI0_A2N OLDI0_A2N 0 IO 0

AB20 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG156 GPIO1_57 7 IO pad
0x000F4270
OLDI0_A2P OLDI0_A2P 0 IO 0

AB21 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG155 GPIO1_56 7 IO pad
0x000F426C
OLDI0_A3N OLDI0_A3N 0 IO 0

AG20 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG158 GPIO1_59 7 IO pad
0x000F4278
OLDI0_A3P OLDI0_A3P 0 IO 0

AG21 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG157 GPIO1_58 7 IO pad
0x000F4274
OLDI0_A4N OLDI0_A4N 0 IO 0

AD21 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG160 GPIO1_61 7 IO pad
0x000F4280
OLDI0_A4P OLDI0_A4P 0 IO 0

AC21 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG159 GPIO1_60 7 IO pad
0x000F427C
OLDI0_A5N OLDI0_A5N 0 IO 0

AF19 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG162 GPIO1_63 7 IO pad
0x000F4288
OLDI0_A5P OLDI0_A5P 0 IO 0

AF18 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG161 GPIO1_62 7 IO pad
0x000F4284
OLDI0_A6N OLDI0_A6N 0 IO 0

AG17 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG164 GPIO1_65 7 IO pad
0x000F4290
OLDI0_A6P OLDI0_A6P 0 IO 0

AG18 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG163 GPIO1_64 7 IO pad
0x000F428C

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Table 5-1. Pin Attributes (AMW Package) (continued)

AB19 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG166 GPIO1_67 7 IO pad
0x000F4298
OLDI0_A7P OLDI0_A7P 0 IO 0

AA20 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG165 GPIO1_66 7 IO pad
0x000F4294
OLDI0_CLK0N OLDI0_CLK0N 0 IO 0

AF21 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG168 GPIO1_69 7 IO pad
0x000F42A0
OLDI0_CLK0P OLDI0_CLK0P 0 IO 0

AE20 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG167 GPIO1_68 7 IO pad
0x000F429C
OLDI0_CLK1N OLDI0_CLK1N 0 IO 0

AD20 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG170 GPIO1_71 7 IO pad
0x000F42A8
OLDI0_CLK1P OLDI0_CLK1P 0 IO 0

AE19 PADCONFIG Off / Off / NA Off / Off / NA 0 1.8 V VDDA_1P8_OLDI0 MLB_LVDS

PADCONFIG169 GPIO1_70 7 IO pad
0x000F42A4
OSPI0_CLK OSPI0_CLK 0 O

L24 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG0 GPIO0_0 7 IO pad
0x000F4000
OSPI0_DQS OSPI0_DQS 0 I 0

L22 PADCONFIG UART5_CTSn 5 I 1 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG2
0x000F4008 GPIO0_2 7 IO pad

OSPI0_LBCLKO OSPI0_LBCLKO 0 IO 0

L23 PADCONFIG UART5_RTSn 5 O Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG1
0x000F4004 GPIO0_1 7 IO pad

OSPI0_CSn0 OSPI0_CSn0 0 O

K26 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG11 GPIO0_11 7 IO pad
0x000F402C
OSPI0_CSn1 OSPI0_CSn1 0 O

K23 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG12 GPIO0_12 7 IO pad
0x000F4030

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Table 5-1. Pin Attributes (AMW Package) (continued)

K27 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG3 GPIO0_3 7 IO pad
0x000F400C
OSPI0_D1 OSPI0_D1 0 IO 0

L27 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG4 GPIO0_4 7 IO pad
0x000F4010
OSPI0_D2 OSPI0_D2 0 IO 0

L26 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG5 GPIO0_5 7 IO pad
0x000F4014
OSPI0_D3 OSPI0_D3 0 IO 0

L25 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG6 GPIO0_6 7 IO pad
0x000F4018
OSPI0_D4 0 IO 0
OSPI0_D4 SPI1_CS0 1 IO 1
L21 PADCONFIG MCASP1_AXR1 2 IO 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG7
0x000F401C UART6_RXD 3 I 1
GPIO0_7 7 IO pad
OSPI0_D5 0 IO 0
OSPI0_D5 SPI1_CLK 1 IO 0
M26 PADCONFIG MCASP1_AXR0 2 IO 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV1 Yes LVCMOS PU/PD
PADCONFIG8
0x000F4020 UART6_TXD 3 O
GPIO0_8 7 IO pad

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Table 5-1. Pin Attributes (AMW Package) (continued)

A8 PADCONFIG Off / Off / Off Off / SS / Off 0 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG32 MCU_GPIO0_22 7 IO pad
0x04084080
PORz_OUT

D27 PADCONFIG PORz_OUT 0 O Off / Low / Off Off / SS / Off 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG148
0x000F4250
RESETSTATz

E27 PADCONFIG RESETSTATz 0 O Off / Low / Off Off / SS / Off 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG147
0x000F424C
RESET_REQz

E26 PADCONFIG RESET_REQz 0 I On / Off / Up On / Off / Up 0 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG146
0x000F4248
RGMII1_RXC RGMII1_RXC 0 I 0

AE27 PADCONFIG RMII1_REF_CLK 1 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG82
0x000F4148 GPIO0_80 7 IO pad

RGMII1_RX_CTL RGMII1_RX_CTL 0 I 0

AD23 PADCONFIG RMII1_RX_ER 1 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG81
0x000F4144 GPIO0_79 7 IO pad

RGMII1_TXC RGMII1_TXC 0 O

AG26 PADCONFIG RMII1_CRS_DV 1 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG76
0x000F4130 GPIO0_74 7 IO pad

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Table 5-1. Pin Attributes (AMW Package) (continued)

AF25 PADCONFIG RMII1_TX_EN 1 O Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG75
0x000F412C GPIO0_73 7 IO pad

RGMII1_RD0 RGMII1_RD0 0 I 0

AC25 PADCONFIG RMII1_RXD0 1 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG83
0x000F414C GPIO0_81 7 IO pad

RGMII1_RD1 RGMII1_RD1 0 I 0

AD27 PADCONFIG RMII1_RXD1 1 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG84
0x000F4150 GPIO0_82 7 IO pad

RGMII1_RD2 RGMII1_RD2 0 I 0

AE24 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG85 GPIO0_83 7 IO pad
0x000F4154
RGMII1_RD3 RGMII1_RD3 0 I 0

AE26 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG86 GPIO0_84 7 IO pad
0x000F4158
RGMII1_TD0 RGMII1_TD0 0 O

AF27 PADCONFIG RMII1_TXD0 1 O Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG77
0x000F4134 GPIO0_75 7 IO pad

RGMII1_TD1 RGMII1_TD1 0 O

AE23 PADCONFIG RMII1_TXD1 1 O Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG78
0x000F4138 GPIO0_76 7 IO pad

RGMII1_TD2 RGMII1_TD2 0 O

AG25 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG79 GPIO0_77 7 IO pad
0x000F413C
RGMII1_TD3 RGMII1_TD3 0 O

AF24 PADCONFIG CLKOUT0 1 O Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV2 Yes LVCMOS PU/PD
PADCONFIG80
0x000F4140 GPIO0_78 7 IO pad

E9 RSVD0 RSVD0 N/A

AA19 RSVD1 RSVD1 N/A
AB7 RSVD2 RSVD2 N/A
AC5 RSVD3 RSVD3 N/A
AB10 RSVD4 RSVD4 N/A
AA12 RSVD5 RSVD5 N/A
AB12 RSVD6 RSVD6 N/A
AB13 RSVD7 RSVD7 N/A

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
AA15 RSVD8 RSVD8 N/A
AA14 RSVD9 RSVD9 N/A
L5 RSVD10 RSVD10 N/A
M6 RSVD11 RSVD11 N/A
AB16 RSVD12 RSVD12 N/A
AB18 RSVD13 RSVD13 N/A
C6 RSVD14 RSVD14 N/A
F8 RSVD15 RSVD15 N/A
B6 RSVD16 RSVD16 N/A
C17 RSVD17 RSVD17 N/A
D16 RSVD18 RSVD18 N/A
D14 RSVD19 RSVD19 N/A
D13 RSVD20 RSVD20 N/A
M2 RSVD21 RSVD21 N/A
E15 SERDES0_REXT SERDES0_REXT A 1.8 V VDDA_1P8_SERDES 4L_PHY
F14 SERDES1_REXT SERDES1_REXT A 1.8 V VDDA_1P8_SERDES 4L_PHY
A17 SERDES0_REFCLK0N SERDES0_REFCLK0N IO 1.8 V VDDA_1P8_SERDES 4L_PHY
A16 SERDES0_REFCLK0P SERDES0_REFCLK0P IO 1.8 V VDDA_1P8_SERDES 4L_PHY
A20 SERDES0_RX0_N SERDES0_RX0_N I 1.8 V VDDA_1P8_SERDES 4L_PHY
A19 SERDES0_RX0_P SERDES0_RX0_P I 1.8 V VDDA_1P8_SERDES 4L_PHY
B19 SERDES0_TX0_N SERDES0_TX0_N O 1.8 V VDDA_1P8_SERDES 4L_PHY
B18 SERDES0_TX0_P SERDES0_TX0_P O 1.8 V VDDA_1P8_SERDES 4L_PHY
B15 SERDES1_REFCLK0N SERDES1_REFCLK0N IO 1.8 V VDDA_1P8_SERDES 4L_PHY
B16 SERDES1_REFCLK0P SERDES1_REFCLK0P IO 1.8 V VDDA_1P8_SERDES 4L_PHY
C14 SERDES1_RX0_N SERDES1_RX0_N I 1.8 V VDDA_1P8_SERDES 4L_PHY
C15 SERDES1_RX0_P SERDES1_RX0_P I 1.8 V VDDA_1P8_SERDES 4L_PHY
A13 SERDES1_TX0_N SERDES1_TX0_N O 1.8 V VDDA_1P8_SERDES 4L_PHY
A14 SERDES1_TX0_P SERDES1_TX0_P O 1.8 V VDDA_1P8_SERDES 4L_PHY
SPI0_CLK 0 IO 0
SPI0_CLK
CP_GEMAC_CPTS0_TS_SYNC 1 O
D20 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG111 EHRPWM1_A 2 IO 0
0x000F41BC
GPIO1_17 7 IO pad
SPI0_CS0 SPI0_CS0 0 IO 1

B20 PADCONFIG EHRPWM0_A 2 IO 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG109
0x000F41B4 GPIO1_15 7 IO pad

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Table 5-1. Pin Attributes (AMW Package) (continued)

A11 PADCONFIG TCK 0 I On / Off / Up On / Off / Up 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG25
0x04084064
TDI

E12 PADCONFIG TDI 0 I On / Off / Up On / Off / Up 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG27
0x0408406C
TDO

F10 PADCONFIG TDO 0 OZ Off / Off / Up Off / SS / Up 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG28
0x04084070
TMS

F11 PADCONFIG TMS 0 I On / Off / Up On / Off / Up 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG29
0x04084074
TRSTn

B10 PADCONFIG TRSTn 0 I On / Off / Down On / Off / Down 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG26
0x04084068

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Table 5-1. Pin Attributes (AMW Package) (continued)

E25 PADCONFIG Off / Off / Down Off / Off / Down 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG149 GPIO1_50 7 IO pad
0x000F4254
VDDA_1P8_USB0,
AA8 USB0_RCALIB USB0_RCALIB A 1.8 V/3.3 V USB2PHY
VDDA_3P3_USB0

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Table 5-1. Pin Attributes (AMW Package) (continued)

B27 PADCONFIG Off / Off / Down Off / Off / Down 7 1.8 V/3.3 V VDDSHV0 Yes LVCMOS PU/PD
PADCONFIG150 GPIO1_51 7 IO pad
0x000F4258
VDDA_1P8_USB1,
E18 USB1_RCALIB USB1_RCALIB A 1.8 V/3.3 V USB2PHY
VDDA_3P3_USB1
VDDA_1P8_USB1,
F18 USB1_VBUS USB1_VBUS A 1.8 V/3.3 V USB2PHY
VDDA_3P3_USB1
H12, H13 VDDA_0P85_SERDES VDDA_0P85_SERDES PWR
J13 VDDA_0P85_SERDES_C VDDA_0P85_SERDES_C PWR
W9 VDDA_0P85_DLL_MMC0 VDDA_0P85_DLL_MMC0 PWR
W13, W16,
VDDA_1P8_CSI_DSI VDDA_1P8_CSI_DSI PWR
Y13
G13 VDDA_1P8_SERDES VDDA_1P8_SERDES PWR
W18, Y19 VDDA_1P8_OLDI0 VDDA_1P8_OLDI0 PWR
Y12 VDDA_1P8_USB0 VDDA_1P8_USB0 PWR
H16 VDDA_1P8_USB1 VDDA_1P8_USB1 PWR
Y11 VDDA_3P3_USB0 VDDA_3P3_USB0 PWR
G15 VDDA_3P3_USB1 VDDA_3P3_USB1 PWR
W15, Y15 VDDA_CORE_CSI_DSI VDDA_CORE_CSI_DSI PWR
Y16 VDDA_CORE_CSI_DSI_CLK VDDA_CORE_CSI_DSI_CLK PWR
W11 VDDA_CORE_USB0 VDDA_CORE_USB0 PWR
H15 VDDA_CORE_USB1 VDDA_CORE_USB1 PWR
P9 VDDA_DDR_PLL0 VDDA_DDR_PLL0 PWR
G11, H11 VDDA_MCU VDDA_MCU PWR
L15 VDDA_PLL0 VDDA_PLL0 PWR
K10 VDDA_PLL1 VDDA_PLL1 PWR
M12 VDDA_PLL2 VDDA_PLL2 PWR
R11 VDDA_PLL3 VDDA_PLL3 PWR
V18 VDDA_PLL4 VDDA_PLL4 PWR
P16 VDDA_PLL5 VDDA_PLL5 PWR
Y17 VDDA_TEMP0 VDDA_TEMP0 PWR
T11 VDDA_TEMP1 VDDA_TEMP1 PWR
L9 VDDA_TEMP2 VDDA_TEMP2 PWR

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Table 5-1. Pin Attributes (AMW Package) (continued)

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
VOUT0_DE 0 O
GPMC0_A17 1 OZ
VOUT0_DE RGMII2_RD1 2 I 0
AC27 PADCONFIG RMII2_RXD1 3 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG63
0x000F40FC UART3_CTSn 4 I 1
MCASP4_AXR5 6 IO 0
GPIO0_62 7 IO pad
VOUT0_HSYNC 0 O
GPMC0_A16 1 OZ
VOUT0_HSYNC RGMII2_RD0 2 I 0
AB24 PADCONFIG RMII2_RXD0 3 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG62
0x000F40F8 UART3_RTSn 4 O
MCASP4_AXR4 6 IO 0
GPIO0_61 7 IO pad
VOUT0_PCLK 0 O
GPMC0_A19 1 OZ
VOUT0_PCLK
RGMII2_RD3 2 I 0
AC26 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG65 UART2_CTSn 4 I 1
0x000F4104
MCASP4_AFSX 6 IO 0
GPIO0_64 7 IO pad
VOUT0_VSYNC 0 O
GPMC0_A18 1 OZ
VOUT0_VSYNC
RGMII2_RD2 2 I 0
AB23 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG64 UART2_RTSn 4 O
0x000F4100
MCASP4_ACLKX 6 IO 0
GPIO0_63 7 IO pad
VOUT0_DATA0 0 O
VOUT0_DATA0 GPMC0_A0 1 OZ
W27 PADCONFIG UART2_RXD 4 I 1 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG46
0x000F40B8 MCASP3_ACLKX 6 IO 0
GPIO0_45 7 IO pad
VOUT0_DATA1 0 O
VOUT0_DATA1 GPMC0_A1 1 OZ
W25 PADCONFIG UART2_TXD 4 O Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG47
0x000F40BC MCASP3_AFSX 6 IO 0
GPIO0_46 7 IO pad

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Table 5-1. Pin Attributes (AMW Package) (continued)

MUX
BALL STATE BALL STATE
BALL NAME [2] MUX MODE I/O PULL
BALL TYPE DSIS DURING AFTER HYS BUFFER
PADCONFIG Register [15] SIGNAL NAME [3] MODE AFTER OPERATING POWER [11] UP/DOWN
NUMBER [1] [5] [6] RESET RESET [12] TYPE [13]
PADCONFIG Address [16] [4] RESET VOLTAGE [10] TYPE [14]
(RX/TX/PULL) [7] (RX/TX/PULL) [8]
[9]
VOUT0_DATA2 0 O
VOUT0_DATA2 GPMC0_A2 1 OZ
W24 PADCONFIG UART3_RXD 4 I 1 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG48
0x000F40C0 MCASP3_AXR0 6 IO 0
GPIO0_47 7 IO pad
VOUT0_DATA3 0 O
GPMC0_A3 1 OZ
VOUT0_DATA3
UART3_TXD 4 O
W23 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG49 AUDIO_EXT_REFCLK0 5 IO 0
0x000F40C4
MCASP3_AXR1 6 IO 0
GPIO0_48 7 IO pad
VOUT0_DATA4 0 O
GPMC0_A4 1 OZ
VOUT0_DATA4
UART4_RXD 4 I 1
W22 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG50 EQEP2_I 5 IO 0
0x000F40C8
MCASP3_AXR2 6 IO 0
GPIO0_49 7 IO pad
VOUT0_DATA5 0 O
GPMC0_A5 1 OZ
VOUT0_DATA5
UART4_TXD 4 O
W21 PADCONFIG Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG51 EQEP2_S 5 IO 0
0x000F40CC
MCASP3_AXR3 6 IO 0
GPIO0_50 7 IO pad
VOUT0_DATA6 0 O
GPMC0_A6 1 OZ
VOUT0_DATA6 UART5_RXD 4 I 1
Y26 PADCONFIG EQEP2_A 5 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG52
0x000F40D0 MCASP3_AXR6 6 IO 0
GPIO0_51 7 IO pad
MCASP3_ACLKR 8 IO 0
VOUT0_DATA7 0 O
GPMC0_A7 1 OZ
VOUT0_DATA7 UART5_TXD 4 O
Y27 PADCONFIG EQEP2_B 5 I 0 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV3 Yes LVCMOS PU/PD
PADCONFIG53
0x000F40D4 MCASP3_AXR7 6 IO 0
GPIO0_52 7 IO pad
MCASP3_AFSR 8 IO 0

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Table 5-1. Pin Attributes (AMW Package) (continued)

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Table 5-1. Pin Attributes (AMW Package) (continued)

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Table 5-1. Pin Attributes (AMW Package) (continued)

F12 PADCONFIG Off / Off / Off Off / SS / Off 0 1.8 V/3.3 V VDDSHV_MCU Yes LVCMOS PU/PD
MCU_PADCONFIG33 MCU_GPIO0_23 7 IO pad
0x04084084

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Table 5-1. Pin Attributes (AMW Package) (continued)

B3 PADCONFIG MCU_SPI0_CS2 2 IO 1 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG9
0x04084024 MCU_GPIO0_9 7 IO pad

WKUP_UART0_TXD WKUP_UART0_TXD 0 O

C8 PADCONFIG MCU_SPI1_CS2 2 IO 1 Off / Off / Off Off / Off / Off 7 1.8 V/3.3 V VDDSHV_CANUART Yes LVCMOS PU/PD
MCU_PADCONFIG10
0x04084028 MCU_GPIO0_10 7 IO pad

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5.3 Signal Descriptions

Many signals are available on multiple pins, according to the software configuration of the pin multiplexing
options.
The following list describes the column headers:
1. SIGNAL NAME: The name of the signal passing through the pin.

Note
Signal names and descriptions provided in each Signal Descriptions table, represent the pin
multiplexed signal function which is implemented at the pin and selected via PADCONFIG registers.
Device subsystems may provide secondary multiplexing of signal functions, which are not described
in these tables. For more information on secondary multiplexed signal functions, see the respective
peripheral chapter of the device TRM.

2. PIN TYPE: Signal direction and type:

• I = Input
• O = Output
• OD = Output, with open-drain output function
• IO = Input, Output, or simultaneously Input and Output
• IOD = Input, Output, or simultaneously Input and Output with open-drain output function
• IOZ = Input, Output, or simultaneously Input and Output with three-state output function
• OZ = Output with three-state output function
• A = Analog
• PWR = Power
• GND = Ground
• CAP = LDO Capacitor
3. DESCRIPTION: Description of the signal
4. BALL: Ball number(s) associated with signal
5.3.1 CPSW3G
5.3.1.1 MAIN Domain
Table 5-2. CPSW3G0 RGMII1 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
RGMII1_RXC I RGMII Receive Clock AE27
RGMII1_RX_CTL I RGMII Receive Control AD23
RGMII1_TXC O RGMII Transmit Clock AG26
RGMII1_TX_CTL O RGMII Transmit Control AF25
RGMII1_RD0 I RGMII Receive Data 0 AC25
RGMII1_RD1 I RGMII Receive Data 1 AD27
RGMII1_RD2 I RGMII Receive Data 2 AE24
RGMII1_RD3 I RGMII Receive Data 3 AE26
RGMII1_TD0 O RGMII Transmit Data 0 AF27
RGMII1_TD1 O RGMII Transmit Data 1 AE23
RGMII1_TD2 O RGMII Transmit Data 2 AG25
RGMII1_TD3 O RGMII Transmit Data 3 AF24

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Table 5-3. CPSW3G0 RGMII2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
RGMII2_RXC I RGMII Receive Clock AB27
RGMII2_RX_CTL I RGMII Receive Control AB26
RGMII2_TXC O RGMII Transmit Clock AA27
RGMII2_TX_CTL O RGMII Transmit Control AA24
RGMII2_RD0 I RGMII Receive Data 0 AB24
RGMII2_RD1 I RGMII Receive Data 1 AC27
RGMII2_RD2 I RGMII Receive Data 2 AB23
RGMII2_RD3 I RGMII Receive Data 3 AC26
RGMII2_TD0 O RGMII Transmit Data 0 AA25
RGMII2_TD1 O RGMII Transmit Data 1 AB25
RGMII2_TD2 O RGMII Transmit Data 2 AA23
RGMII2_TD3 O RGMII Transmit Data 3 AA22

Table 5-4. CPSW3G0 RMII1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
RMII1_CRS_DV I RMII Carrier Sense / Data Valid AG26
RMII1_REF_CLK I RMII Reference Clock AE27
RMII1_RX_ER I RMII Receive Data Error AD23
RMII1_TX_EN O RMII Transmit Enable AF25
RMII1_RXD0 I RMII Receive Data 0 AC25
RMII1_RXD1 I RMII Receive Data 1 AD27
RMII1_TXD0 O RMII Transmit Data 0 AF27
RMII1_TXD1 O RMII Transmit Data 1 AE23

Table 5-5. CPSW3G0 RMII2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
RMII2_CRS_DV I RMII Carrier Sense / Data Valid AA27
RMII2_REF_CLK I RMII Reference Clock AB27
RMII2_RX_ER I RMII Receive Data Error AB26
RMII2_TX_EN O RMII Transmit Enable AA24
RMII2_RXD0 I RMII Receive Data 0 AB24
RMII2_RXD1 I RMII Receive Data 1 AC27
RMII2_TXD0 O RMII Transmit Data 0 AA25
RMII2_TXD1 O RMII Transmit Data 1 AB25

5.3.2 CPTS
5.3.2.1 MAIN Domain
Table 5-6. CPTS Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
CP_GEMAC_CPTS0_RFT_CLK I CPTS Reference Clock Input A23
CP_GEMAC_CPTS0_TS_COMP O CPTS Time Stamp Counter Compare Output from C20, H25
CPSW3G0 CPTS

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Table 5-6. CPTS Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
CP_GEMAC_CPTS0_TS_SYNC IO CPTS Time Stamp Counter Bit Output from CPSW3G0 D20, J23
CPTS
CP_GEMAC_CPTS0_HW1TSPUSH IO CPTS Hardware Time Stamp Push Input to Time Sync E19, H20
Router
CP_GEMAC_CPTS0_HW2TSPUSH IO CPTS Hardware Time Stamp Push Input to Time Sync E20, H23
Router

5.3.3 CSI-2
5.3.3.1 MAIN Domain
Table 5-7. CSIRX0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] ((2)) DESCRIPTION [3] AMW PIN [4]
[2]
CSI0_RXCLKN I CSI Differential Receive Clock Input (negative) AC7
CSI0_RXCLKP I CSI Differential Receive Clock Input (positive) AC6
CSI0_RXRCALIB (1) A CSI pin connected to external resistor for on-chip resistor AB8
calibration
CSI0_RXN0 I CSI Differential Receive Input (negative) AD6
CSI0_RXN1 I CSI Differential Receive Input (negative) AE5
CSI0_RXN2 I CSI Differential Receive Input (negative) AF4
CSI0_RXN3 I CSI Differential Receive Input (negative) AG3
CSI0_RXP0 I CSI Differential Receive Input (positive) AD5
CSI0_RXP1 I CSI Differential Receive Input (positive) AE4
CSI0_RXP2 I CSI Differential Receive Input (positive) AF3
CSI0_RXP3 I CSI Differential Receive Input (positive) AG2

Table 5-8. CSIRX1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
CSI1_RXCLKN I CSI Differential Receive Clock Input (negative) AG6
CSI1_RXCLKP I CSI Differential Receive Clock Input (positive) AG5
CSI1_RXRCALIB (1) A CSI pin connected to external resistor for on-chip resistor AA10
calibration
CSI1_RXN0 I CSI Differential Receive Input (negative) AF7
CSI1_RXN1 I CSI Differential Receive Input (negative) AE8
CSI1_RXN2 I CSI Differential Receive Input (negative) AD9
CSI1_RXN3 I CSI Differential Receive Input (negative) AC10
CSI1_RXP0 I CSI Differential Receive Input (positive) AF6
CSI1_RXP1 I CSI Differential Receive Input (positive) AE7
CSI1_RXP2 I CSI Differential Receive Input (positive) AD8
CSI1_RXP3 I CSI Differential Receive Input (positive) AC9

(1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.

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Table 5-9. CSIRX2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
CSI2_RXCLKN I CSI Differential Receive Clock Input (negative) AG8
CSI2_RXCLKP I CSI Differential Receive Clock Input (positive) AG9
CSI2_RXRCALIB (1) A CSI pin connected to external resistor for on-chip resistor AB14
calibration
CSI2_RXN0 I CSI Differential Receive Input (negative) AF9
CSI2_RXN1 I CSI Differential Receive Input (negative) AE10
CSI2_RXN2 I CSI Differential Receive Input (negative) AD11
CSI2_RXN3 I CSI Differential Receive Input (negative) AC13
CSI2_RXP0 I CSI Differential Receive Input (positive) AF10
CSI2_RXP1 I CSI Differential Receive Input (positive) AE11
CSI2_RXP2 I CSI Differential Receive Input (positive) AD12
CSI2_RXP3 I CSI Differential Receive Input (positive) AC12

(1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.

Table 5-10. CSIRX3 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
CSI3_RXCLKN I CSI Differential Receive Clock Input (negative) AG12
CSI3_RXCLKP I CSI Differential Receive Clock Input (positive) AG11
CSI3_RXRCALIB (1) A CSI pin connected to external resistor for on-chip resistor AB15
calibration
CSI3_RXN0 I CSI Differential Receive Input (negative) AF13
CSI3_RXN1 I CSI Differential Receive Input (negative) AE14
CSI3_RXN2 I CSI Differential Receive Input (negative) AD15
CSI3_RXN3 I CSI Differential Receive Input (negative) AC15
CSI3_RXP0 I CSI Differential Receive Input (positive) AF12
CSI3_RXP1 I CSI Differential Receive Input (positive) AE13
CSI3_RXP2 I CSI Differential Receive Input (positive) AD14
CSI3_RXP3 I CSI Differential Receive Input (positive) AC16

(1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
5.3.4 DDRSS
5.3.4.1 MAIN Domain
Table 5-11. DDRSS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
DDR0_CAS_n (1) O DDRSS Column Address Strobe / LPDDR4 Chip Select M4
1B
DDR0_RAS_n (1) O DDRSS Row Address Strobe / LPDDR4 Chip Select 0B M3
DDR0_A0 O DDRSS Address Bus L4
DDR0_A1 O DDRSS Address Bus L6
DDR0_A2 O DDRSS Address Bus M5
DDR0_A3 O DDRSS Address Bus L3
DDR0_A4 O DDRSS Address Bus N2
DDR0_A5 O DDRSS Address Bus L2
DDR0_CAL0 (2) A IO Pad Calibration Resistor R6

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Table 5-11. DDRSS0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
DDR0_CK0 O DDRSS Clock P1
DDR0_CK0_n O DDRSS Negative Clock N1
DDR0_CKE0 O DDRSS Clock Enable P2
DDR0_CKE1 O DDRSS Clock Enable P6
DDR0_CS0_n (1) O DDRSS Chip Select 0 / LPDDR4 Chip Select 0A P4
DDR0_CS1_n (1) O DDRSS Chip Select 1 / LPDDR4 Chip Select 1A P3
DDR0_DM0 IO DDRSS Data Mask G2
DDR0_DM1 IO DDRSS Data Mask H6
DDR0_DM2 IO DDRSS Data Mask U4
DDR0_DM3 IO DDRSS Data Mask AA2
DDR0_DQ0 IO DDRSS Data D6
DDR0_DQ1 IO DDRSS Data D2
DDR0_DQ2 IO DDRSS Data F6
DDR0_DQ3 IO DDRSS Data D3
DDR0_DQ4 IO DDRSS Data G4
DDR0_DQ5 IO DDRSS Data E2
DDR0_DQ6 IO DDRSS Data G6
DDR0_DQ7 IO DDRSS Data F3
DDR0_DQ8 IO DDRSS Data H5
DDR0_DQ9 IO DDRSS Data H2
DDR0_DQ10 IO DDRSS Data K2
DDR0_DQ11 IO DDRSS Data L1
DDR0_DQ12 IO DDRSS Data J6
DDR0_DQ13 IO DDRSS Data J4
DDR0_DQ14 IO DDRSS Data J2
DDR0_DQ15 IO DDRSS Data H3
DDR0_DQ16 IO DDRSS Data V3
DDR0_DQ17 IO DDRSS Data R2
DDR0_DQ18 IO DDRSS Data R5
DDR0_DQ19 IO DDRSS Data T2
DDR0_DQ20 IO DDRSS Data R3
DDR0_DQ21 IO DDRSS Data U2
DDR0_DQ22 IO DDRSS Data U5
DDR0_DQ23 IO DDRSS Data V2
DDR0_DQ24 IO DDRSS Data Y2
DDR0_DQ25 IO DDRSS Data W4
DDR0_DQ26 IO DDRSS Data V5
DDR0_DQ27 IO DDRSS Data W2
DDR0_DQ28 IO DDRSS Data V6
DDR0_DQ29 IO DDRSS Data W3
DDR0_DQ30 IO DDRSS Data AA3
DDR0_DQ31 IO DDRSS Data AA5
DDR0_DQS0 IO DDRSS Data Strobe E1
DDR0_DQS0_n IO DDRSS Complimentary Data Strobe F1

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Table 5-11. DDRSS0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
DDR0_DQS1 IO DDRSS Data Strobe H1
DDR0_DQS1_n IO DDRSS Complimentary Data Strobe J1
DDR0_DQS2 IO DDRSS Data Strobe T1
DDR0_DQS2_n IO DDRSS Complimentary Data Strobe U1
DDR0_DQS3 IO DDRSS Data Strobe W1
DDR0_DQS3_n IO DDRSS Complimentary Data Strobe Y1
DDR0_RESET0_n O DDRSS Reset U6

(1) DDRSS implements different signal functions on Column Address Strobe, Row Address Strobe, Chip Select 0, and Chip Select 1
when configured to operate with LPDDR4 memory devices. These signals function as Chip Select 1B, Chip Select 0B, Chip Select 0A,
and Chip Select 1A respectively when DDRSS is configured to operate with LPDDR4 memory devices. For more information, refer to
Section 8.2.1, DDR Board Design and Layout Guidelines.
(2) An external 240 Ω ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
5.3.5 DSI
5.3.5.1 MAIN Domain
Table 5-12. DSITX0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] ((2)) DESCRIPTION [3] AMW PIN [4]
[2]
DSI0_TXCLKN IO DSI Differential Transmit Clock Ouput (negative) AE16
DSI0_TXCLKP IO DSI Differential Transmit Clock Ouput (positive) AE17
DSI0_TXRCALIB (1) A DSI pin connected to external resistor for on-chip resistor AA16
calibration
DSI0_TXN0 IO DSI Differential Transmit Ouput (negative) AD17
DSI0_TXN1 IO DSI Differential Transmit Ouput (negative) AF15
DSI0_TXN2 IO DSI Differential Transmit Ouput (negative) AG14
DSI0_TXN3 IO DSI Differential Transmit Ouput (negative) AC18
DSI0_TXP0 IO DSI Differential Transmit Ouput (positive) AD18
DSI0_TXP1 IO DSI Differential Transmit Ouput (positive) AF16
DSI0_TXP2 IO DSI Differential Transmit Ouput (positive) AG15
DSI0_TXP3 IO DSI Differential Transmit Ouput (positive) AC19

(1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
(2) The functionality of these pins is controlled by DPHY_TX0_CTRL[1:0] LANE_FUNC_SEL. 0x0 = DSI PPI, 0x1 = CSI0 TX.
5.3.6 DSS
5.3.6.1 MAIN Domain
Table 5-13. DSS0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
VOUT0_DE O Video Output Data Enable AC27
VOUT0_EXTPCLKIN I Video Output External Pixel Clock Input W26
VOUT0_HSYNC O Video Output Horizontal Sync AB24
VOUT0_PCLK O Video Output Pixel Clock Output AC26
VOUT0_VSYNC O Video Output Vertical Sync AB23
VOUT0_DATA0 O Video Output Data 0 W27
VOUT0_DATA1 O Video Output Data 1 W25
VOUT0_DATA2 O Video Output Data 2 W24
VOUT0_DATA3 O Video Output Data 3 W23

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Table 5-13. DSS0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
VOUT0_DATA4 O Video Output Data 4 W22
VOUT0_DATA5 O Video Output Data 5 W21
VOUT0_DATA6 O Video Output Data 6 Y26
VOUT0_DATA7 O Video Output Data 7 Y27
VOUT0_DATA8 O Video Output Data 8 AA24
VOUT0_DATA9 O Video Output Data 9 AA27
VOUT0_DATA10 O Video Output Data 10 AA25
VOUT0_DATA11 O Video Output Data 11 AB25
VOUT0_DATA12 O Video Output Data 12 AA23
VOUT0_DATA13 O Video Output Data 13 AA22
VOUT0_DATA14 O Video Output Data 14 AB26
VOUT0_DATA15 O Video Output Data 15 AB27
VOUT0_DATA16 O Video Output Data 16 U27
VOUT0_DATA17 O Video Output Data 17 U26
VOUT0_DATA18 O Video Output Data 18 V27
VOUT0_DATA19 O Video Output Data 19 V25
VOUT0_DATA20 O Video Output Data 20 V26
VOUT0_DATA21 O Video Output Data 21 V24
VOUT0_DATA22 O Video Output Data 22 V22
VOUT0_DATA23 O Video Output Data 23 V23

5.3.7 ECAP
5.3.7.1 MAIN Domain
Table 5-14. ECAP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
ECAP0_IN_APWM_OUT IO Enhanced Capture (ECAP) Input or Auxiliary PWM A23, C20
(APWM) Ouput

Table 5-15. ECAP1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
ECAP1_IN_APWM_OUT IO Enhanced Capture (ECAP) Input or Auxiliary PWM A25, B25, D23, F19,
(APWM) Ouput H20

Table 5-16. ECAP2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
ECAP2_IN_APWM_OUT IO Enhanced Capture (ECAP) Input or Auxiliary PWM A26, B22, D25, F20,
(APWM) Ouput H23

5.3.8 Emulation and Debug

5.3.8.1 MAIN Domain
Table 5-17. Trace Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
TRC_CLK O Trace Clock R22

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Table 5-17. Trace Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
TRC_CTL O Trace Control R23
TRC_DATA0 O Trace Data 0 R26
TRC_DATA1 O Trace Data 1 T27
TRC_DATA2 O Trace Data 2 T25
TRC_DATA3 O Trace Data 3 T24
TRC_DATA4 O Trace Data 4 T21
TRC_DATA5 O Trace Data 5 T22
TRC_DATA6 O Trace Data 6 T23
TRC_DATA7 O Trace Data 7 N21
TRC_DATA8 O Trace Data 8 N22
TRC_DATA9 O Trace Data 9 N23
TRC_DATA10 O Trace Data 10 P27
TRC_DATA11 O Trace Data 11 P26
TRC_DATA12 O Trace Data 12 V21
TRC_DATA13 O Trace Data 13 N24
TRC_DATA14 O Trace Data 14 N25
TRC_DATA15 O Trace Data 15 R27
TRC_DATA16 O Trace Data 16 P21
TRC_DATA17 O Trace Data 17 P22
TRC_DATA18 O Trace Data 18 P23
TRC_DATA19 O Trace Data 19 V23
TRC_DATA20 O Trace Data 20 V22
TRC_DATA21 O Trace Data 21 V24
TRC_DATA22 O Trace Data 22 V26
TRC_DATA23 O Trace Data 23 V25

5.3.8.2 MCU Domain

Table 5-18. JTAG Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EMU0 IO Emulation Control 0 C9
EMU1 IO Emulation Control 1 F9
TCK I JTAG Test Clock Input A11
TDI I JTAG Test Data Input E12
TDO OZ JTAG Test Data Output F10
TMS I JTAG Test Mode Select Input F11
TRSTn I JTAG Reset B10

5.3.9 EPWM
5.3.9.1 MAIN Domain
Table 5-19. EPWM Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EHRPWM_SOCA O EHRPWM Start of Conversion A D23
EHRPWM_SOCB O EHRPWM Start of Conversion B B22

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Table 5-19. EPWM Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EHRPWM_TZn_IN0 I EHRPWM Trip Zone Input 0 (active low) E20, F27
EHRPWM_TZn_IN1 I EHRPWM Trip Zone Input 1 (active low) F26
EHRPWM_TZn_IN2 I EHRPWM Trip Zone Input 2 (active low) H21
EHRPWM_TZn_IN3 I EHRPWM Trip Zone Input 3 (active low) D22
EHRPWM_TZn_IN4 I EHRPWM Trip Zone Input 4 (active low) C22
EHRPWM_TZn_IN5 I EHRPWM Trip Zone Input 5 (active low) C20

Table 5-20. EPWM0 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EHRPWM0_A IO EHRPWM Output A B20, C27, J27
EHRPWM0_B IO EHRPWM Output B C20, F24, H27
EHRPWM0_SYNCI I Sync Input to EHRPWM module from an external pin C24, H26
EHRPWM0_SYNCO O Sync Input to EHRPWM module from an external pin A22, F27

Table 5-21. EPWM1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EHRPWM1_A IO EHRPWM Output A B25, D20, G27
EHRPWM1_B IO EHRPWM Output B E19, F23, G26

Table 5-22. EPWM2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EHRPWM2_A IO EHRPWM Output A C24, F19, F26
EHRPWM2_B IO EHRPWM Output B A22, F20, H21

5.3.10 EQEP
5.3.10.1 MAIN Domain
Table 5-23. EQEP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EQEP0_A (1) I EQEP Quadrature Input A A25
EQEP0_B (1) I EQEP Quadrature Input B A26
EQEP0_I (1) IO EQEP Index F23
EQEP0_S (1) IO EQEP Strobe B25

(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.

Table 5-24. EQEP1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EQEP1_A (1) I EQEP Quadrature Input A D25
EQEP1_B (1) I EQEP Quadrature Input B C26
EQEP1_I (1) IO EQEP Index F24

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Table 5-24. EQEP1 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EQEP1_S (1) IO EQEP Strobe C27

(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.

Table 5-25. EQEP2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
EQEP2_A (1) I EQEP Quadrature Input A D23, Y26
EQEP2_B (1) I EQEP Quadrature Input B B22, Y27
EQEP2_I (1) IO EQEP Index D22, W22, W26
EQEP2_S (1) IO EQEP Strobe C22, N25, W21

(1) This EQEP input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
5.3.11 GPIO
5.3.11.1 MAIN Domain
Table 5-26. GPIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
GPIO0_0 IO General Purpose Input/Output L24
GPIO0_1 IO General Purpose Input/Output L23
GPIO0_2 IO General Purpose Input/Output L22
GPIO0_3 IO General Purpose Input/Output K27
GPIO0_4 IO General Purpose Input/Output L27
GPIO0_5 IO General Purpose Input/Output L26
GPIO0_6 IO General Purpose Input/Output L25
GPIO0_7 IO General Purpose Input/Output L21
GPIO0_8 IO General Purpose Input/Output M26
GPIO0_9 IO General Purpose Input/Output N27
GPIO0_10 IO General Purpose Input/Output M27
GPIO0_11 IO General Purpose Input/Output K26
GPIO0_12 IO General Purpose Input/Output K23
GPIO0_13 (1) IO General Purpose Input/Output K22
GPIO0_14 (1) IO General Purpose Input/Output J22
GPIO0_15 IO General Purpose Input/Output R22
GPIO0_16 IO General Purpose Input/Output R23
GPIO0_17 IO General Purpose Input/Output R26
GPIO0_18 IO General Purpose Input/Output T27
GPIO0_19 IO General Purpose Input/Output T25
GPIO0_20 IO General Purpose Input/Output T24
GPIO0_21 IO General Purpose Input/Output T21
GPIO0_22 IO General Purpose Input/Output T22
GPIO0_23 IO General Purpose Input/Output U27
GPIO0_24 IO General Purpose Input/Output U26
GPIO0_25 IO General Purpose Input/Output V27
GPIO0_26 IO General Purpose Input/Output V25
GPIO0_27 IO General Purpose Input/Output V26

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Table 5-26. GPIO0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
GPIO0_28 IO General Purpose Input/Output V24
GPIO0_29 IO General Purpose Input/Output V22
GPIO0_30 IO General Purpose Input/Output V23
GPIO0_31 IO General Purpose Input/Output T23
GPIO0_32 IO General Purpose Input/Output N21
GPIO0_33 IO General Purpose Input/Output N22
GPIO0_34 IO General Purpose Input/Output N23
GPIO0_35 IO General Purpose Input/Output P27
GPIO0_36 IO General Purpose Input/Output P26
GPIO0_37 IO General Purpose Input/Output V21
GPIO0_38 IO General Purpose Input/Output W26
GPIO0_39 IO General Purpose Input/Output N24
GPIO0_40 IO General Purpose Input/Output N25
GPIO0_41 IO General Purpose Input/Output R27
GPIO0_42 IO General Purpose Input/Output P21
GPIO0_43 (1) IO General Purpose Input/Output P22
GPIO0_44 (1) IO General Purpose Input/Output P23
GPIO0_45 IO General Purpose Input/Output W27
GPIO0_46 IO General Purpose Input/Output W25
GPIO0_47 IO General Purpose Input/Output W24
GPIO0_48 IO General Purpose Input/Output W23
GPIO0_49 IO General Purpose Input/Output W22
GPIO0_50 IO General Purpose Input/Output W21
GPIO0_51 IO General Purpose Input/Output Y26
GPIO0_52 IO General Purpose Input/Output Y27
GPIO0_53 IO General Purpose Input/Output AA24
GPIO0_54 IO General Purpose Input/Output AA27
GPIO0_55 IO General Purpose Input/Output AA25
GPIO0_56 IO General Purpose Input/Output AB25
GPIO0_57 IO General Purpose Input/Output AA23
GPIO0_58 IO General Purpose Input/Output AA22
GPIO0_59 IO General Purpose Input/Output AB26
GPIO0_60 IO General Purpose Input/Output AB27
GPIO0_61 IO General Purpose Input/Output AB24
GPIO0_62 IO General Purpose Input/Output AC27
GPIO0_63 IO General Purpose Input/Output AB23
GPIO0_64 IO General Purpose Input/Output AC26
GPIO0_65 (1) IO General Purpose Input/Output J27
GPIO0_66 (1) IO General Purpose Input/Output H27
GPIO0_67 (1) IO General Purpose Input/Output G27
GPIO0_68 (1) IO General Purpose Input/Output G26
GPIO0_69 (1) IO General Purpose Input/Output H26
GPIO0_70 (1) IO General Purpose Input/Output F27
GPIO0_71 (1) IO General Purpose Input/Output F26

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Table 5-26. GPIO0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
GPIO0_72 (1) IO General Purpose Input/Output H21
GPIO0_73 IO General Purpose Input/Output AF25
GPIO0_74 IO General Purpose Input/Output AG26
GPIO0_75 IO General Purpose Input/Output AF27
GPIO0_76 IO General Purpose Input/Output AE23
GPIO0_77 IO General Purpose Input/Output AG25
GPIO0_78 IO General Purpose Input/Output AF24
GPIO0_79 IO General Purpose Input/Output AD23
GPIO0_80 IO General Purpose Input/Output AE27
GPIO0_81 IO General Purpose Input/Output AC25
GPIO0_82 IO General Purpose Input/Output AD27
GPIO0_83 IO General Purpose Input/Output AE24
GPIO0_84 IO General Purpose Input/Output AE26
GPIO0_85 IO General Purpose Input/Output AD25
GPIO0_86 IO General Purpose Input/Output AC24

(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.

Table 5-27. GPIO1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
GPIO1_7 IO General Purpose Input/Output A25
GPIO1_8 IO General Purpose Input/Output A26
GPIO1_9 IO General Purpose Input/Output B25
GPIO1_10 IO General Purpose Input/Output F23
GPIO1_11 IO General Purpose Input/Output D25
GPIO1_12 IO General Purpose Input/Output C26
GPIO1_13 IO General Purpose Input/Output C27
GPIO1_14 IO General Purpose Input/Output F24
GPIO1_15 IO General Purpose Input/Output B20
GPIO1_16 (1) IO General Purpose Input/Output C20
GPIO1_17 IO General Purpose Input/Output D20
GPIO1_18 IO General Purpose Input/Output E19
GPIO1_19 IO General Purpose Input/Output E20
GPIO1_20 IO General Purpose Input/Output F19
GPIO1_21 IO General Purpose Input/Output F20
GPIO1_22 IO General Purpose Input/Output E22
GPIO1_23 IO General Purpose Input/Output B21
GPIO1_24 IO General Purpose Input/Output D22
GPIO1_25 IO General Purpose Input/Output C22
GPIO1_26 IO General Purpose Input/Output D23
GPIO1_27 IO General Purpose Input/Output B22
GPIO1_28 IO General Purpose Input/Output C24
GPIO1_29 IO General Purpose Input/Output A22
GPIO1_30 IO General Purpose Input/Output A23
GPIO1_31 (1) IOD General Purpose Input/Output B23

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Table 5-27. GPIO1 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
GPIO1_42 (1) IO General Purpose Input/Output H25
GPIO1_43 (1) IO General Purpose Input/Output J23
GPIO1_44 (1) IO General Purpose Input/Output H20
GPIO1_45 (1) IO General Purpose Input/Output H23
GPIO1_46 (1) IO General Purpose Input/Output H24
GPIO1_47 (1) IO General Purpose Input/Output H22
GPIO1_48 (1) I General Purpose Input/Output B24
GPIO1_49 (1) I General Purpose Input/Output A24
GPIO1_50 IO General Purpose Input/Output E25
GPIO1_51 IO General Purpose Input/Output B27
GPIO1_52 IO General Purpose Input/Output AG24
GPIO1_53 IO General Purpose Input/Output AF23
GPIO1_54 IO General Purpose Input/Output AG23
GPIO1_55 IO General Purpose Input/Output AG22
GPIO1_56 IO General Purpose Input/Output AB21
GPIO1_57 IO General Purpose Input/Output AB20
GPIO1_58 IO General Purpose Input/Output AG21
GPIO1_59 IO General Purpose Input/Output AG20
GPIO1_60 IO General Purpose Input/Output AC21
GPIO1_61 IO General Purpose Input/Output AD21
GPIO1_62 IO General Purpose Input/Output AF18
GPIO1_63 IO General Purpose Input/Output AF19
GPIO1_64 IO General Purpose Input/Output AG18
GPIO1_65 IO General Purpose Input/Output AG17
GPIO1_66 IO General Purpose Input/Output AA20
GPIO1_67 IO General Purpose Input/Output AB19
GPIO1_68 IO General Purpose Input/Output AE20
GPIO1_69 IO General Purpose Input/Output AF21
GPIO1_70 IO General Purpose Input/Output AE19
GPIO1_71 IO General Purpose Input/Output AD20
GPIO1_72 IOD General Purpose Input/Output F25

(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
5.3.11.2 MCU Domain
Table 5-28. MCU_GPIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_GPIO0_0 (1) IO General Purpose Input/Output C12
MCU_GPIO0_1 (1) IO General Purpose Input/Output A10
MCU_GPIO0_2 IO General Purpose Input/Output A9
MCU_GPIO0_3 IO General Purpose Input/Output B12
MCU_GPIO0_4 IO General Purpose Input/Output C11
MCU_GPIO0_5 IO General Purpose Input/Output B8
MCU_GPIO0_6 IO General Purpose Input/Output B4
MCU_GPIO0_7 (1) IO General Purpose Input/Output B5

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Table 5-28. MCU_GPIO0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_GPIO0_8 (1) IO General Purpose Input/Output C5
MCU_GPIO0_9 IO General Purpose Input/Output B3
MCU_GPIO0_10 IO General Purpose Input/Output C8
MCU_GPIO0_11 (1) IO General Purpose Input/Output C4
MCU_GPIO0_12 (1) IO General Purpose Input/Output C3
MCU_GPIO0_13 IO General Purpose Input/Output B2
MCU_GPIO0_14 IO General Purpose Input/Output D8
MCU_GPIO0_15 (1) IO General Purpose Input/Output C1
MCU_GPIO0_16 (1) IO General Purpose Input/Output B1
MCU_GPIO0_17 IOD General Purpose Input/Output B13
MCU_GPIO0_18 IOD General Purpose Input/Output E11
MCU_GPIO0_19 IOD General Purpose Input/Output B9
MCU_GPIO0_20 IOD General Purpose Input/Output D11
MCU_GPIO0_21 IO General Purpose Input/Output E13
MCU_GPIO0_22 IO General Purpose Input/Output A8
MCU_GPIO0_23 IO General Purpose Input/Output F12

(1) This GPIO input signal has a debounce function. For more information on I/O Debounce configuration, see the TRM Device
Configuration chapter.
5.3.12 GPMC
5.3.12.1 MAIN Domain
Table 5-29. GPMC0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
GPMC0_ADVn_ALE O GPMC Address Valid (active low) or Address Latch N21
Enable
GPMC0_CLK O GPMC clock T23
GPMC0_DIR O GPMC Data Bus Signal Direction Control N25
GPMC0_FCLK_MUX O GPMC functional clock output T23
GPMC0_OEn_REn O GPMC Output Enable (active low) or Read Enable N22
(active low)
GPMC0_WEn O GPMC Write Enable (active low) N23
GPMC0_WPn O GPMC Flash Write Protect (active low) N24
GPMC0_A0 OZ GPMC Address 0 Output. Only used to effectively W27
address 8-bit data non-multiplexed memories
GPMC0_A1 OZ GPMC address 1 Output in A/D non-multiplexed mode W25
and Address 17 in A/D multiplexed mode
GPMC0_A2 OZ GPMC address 2 Output in A/D non-multiplexed mode W24
and Address 18 in A/D multiplexed mode
GPMC0_A3 OZ GPMC address 3 Output in A/D non-multiplexed mode W23
and Address 19 in A/D multiplexed mode
GPMC0_A4 OZ GPMC address 4 Output in A/D non-multiplexed mode W22
and Address 20 in A/D multiplexed mode
GPMC0_A5 OZ GPMC address 5 Output in A/D non-multiplexed mode W21
and Address 21 in A/D multiplexed mode
GPMC0_A6 OZ GPMC address 6 Output in A/D non-multiplexed mode Y26
and Address 22 in A/D multiplexed mode
GPMC0_A7 OZ GPMC address 7 Output in A/D non-multiplexed mode Y27
and Address 23 in A/D multiplexed mode

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Table 5-29. GPMC0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
GPMC0_A8 OZ GPMC address 8 Output in A/D non-multiplexed mode AA24
and Address 24 in A/D multiplexed mode
GPMC0_A9 OZ GPMC address 9 Output in A/D non-multiplexed mode AA27
and Address 25 in A/D multiplexed mode
GPMC0_A10 OZ GPMC address 10 Output in A/D non-multiplexed mode AA25
and Address 26 in A/D multiplexed mode
GPMC0_A11 OZ GPMC address 11 Output in A/D non-multiplexed mode AB25
and unused in A/D multiplexed mode
GPMC0_A12 OZ GPMC address 12 Output in A/D non-multiplexed mode AA23
and unused in A/D multiplexed mode
GPMC0_A13 OZ GPMC address 13 Output in A/D non-multiplexed mode AA22
and unused in A/D multiplexed mode
GPMC0_A14 OZ GPMC address 14 Output in A/D non-multiplexed mode AB26
and unused in A/D multiplexed mode
GPMC0_A15 OZ GPMC address 15 Output in A/D non-multiplexed mode AB27
and unused in A/D multiplexed mode
GPMC0_A16 OZ GPMC address 16 Output in A/D non-multiplexed mode AB24
and unused in A/D multiplexed mode
GPMC0_A17 OZ GPMC address 17 Output in A/D non-multiplexed mode AC27
and unused in A/D multiplexed mode
GPMC0_A18 OZ GPMC address 18 Output in A/D non-multiplexed mode AB23
and unused in A/D multiplexed mode
GPMC0_A19 OZ GPMC address 19 Output in A/D non-multiplexed mode AC26
and unused in A/D multiplexed mode
GPMC0_A20 OZ GPMC address 20 Output in A/D non-multiplexed mode P23
and unused in A/D multiplexed mode
GPMC0_A21 OZ GPMC address 21 Output in A/D non-multiplexed mode W26
and unused in A/D multiplexed mode
GPMC0_A22 OZ GPMC address 22 Output in A/D non-multiplexed mode N24
and unused in A/D multiplexed mode
GPMC0_AD0 IO GPMC Data 0 Input/Output in A/D non-multiplexed mode R22
and additionally Address 1 Output in A/D multiplexed
mode
GPMC0_AD1 IO GPMC Data 1 Input/Output in A/D non-multiplexed mode R23
and additionally Address 2 Output in A/D multiplexed
mode
GPMC0_AD2 IO GPMC Data 2 Input/Output in A/D non-multiplexed mode R26
and additionally Address 3 Output in A/D multiplexed
mode
GPMC0_AD3 IO GPMC Data 3 Input/Output in A/D non-multiplexed mode T27
and additionally Address 3 Output in A/D multiplexed
mode
GPMC0_AD4 IO GPMC Data 4 Input/Output in A/D non-multiplexed mode T25
and additionally Address 3 Output in A/D multiplexed
mode
GPMC0_AD5 IO GPMC Data 5 Input/Output in A/D non-multiplexed mode T24
and additionally Address 3 Output in A/D multiplexed
mode
GPMC0_AD6 IO GPMC Data 6 Input/Output in A/D non-multiplexed mode T21
and additionally Address 3 Output in A/D multiplexed
mode
GPMC0_AD7 IO GPMC Data 7 Input/Output in A/D non-multiplexed mode T22
and additionally Address 3 Output in A/D multiplexed
mode

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Table 5-29. GPMC0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
GPMC0_AD8 IO GPMC Data 8 Input/Output in A/D non-multiplexed mode U27
and additionally Address 3 Output in A/D multiplexed
mode
GPMC0_AD9 IO GPMC Data 9 Input/Output in A/D non-multiplexed mode U26
and additionally Address 3 Output in A/D multiplexed
mode
GPMC0_AD10 IO GPMC Data 10 Input/Output in A/D non-multiplexed V27
mode and additionally Address 11 Output in A/D
multiplexed mode
GPMC0_AD11 IO GPMC Data 11 Input/Output in A/D non-multiplexed V25
mode and additionally Address 12 Output in A/D
multiplexed mode
GPMC0_AD12 IO GPMC Data 12 Input/Output in A/D non-multiplexed V26
mode and additionally Address 13 Output in A/D
multiplexed mode
GPMC0_AD13 IO GPMC Data 13 Input/Output in A/D non-multiplexed V24
mode and additionally Address 14 Output in A/D
multiplexed mode
GPMC0_AD14 IO GPMC Data 14 Input/Output in A/D non-multiplexed V22
mode and additionally Address 15 Output in A/D
multiplexed mode
GPMC0_AD15 IO GPMC Data 15 Input/Output in A/D non-multiplexed V23
mode and additionally Address 16 Output in A/D
multiplexed mode
GPMC0_BE0n_CLE O GPMC Lower-Byte Enable (active low) or Command P27
Latch Enable
GPMC0_BE1n O GPMC Upper-Byte Enable (active low) P26
GPMC0_CSn0 O GPMC Chip Select 0 (active low) R27
GPMC0_CSn1 O GPMC Chip Select 1 (active low) P21
GPMC0_CSn2 O GPMC Chip Select 2 (active low) P22
GPMC0_CSn3 O GPMC Chip Select 3 (active low) P23
GPMC0_WAIT0 I GPMC External Indication of Wait V21
GPMC0_WAIT1 I GPMC External Indication of Wait W26

5.3.13 I2C
5.3.13.1 MAIN Domain
Table 5-30. I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
I2C0_SCL IOD I2C Clock D23
I2C0_SDA IOD I2C Data B22

Table 5-31. I2C1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
I2C1_SCL IOD I2C Clock C24
I2C1_SDA IOD I2C Data A22

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Table 5-32. I2C2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
I2C2_SCL IOD I2C Clock G26, P22
I2C2_SDA IOD I2C Data G27, H27, P23

Table 5-33. I2C3 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
I2C3_SCL IOD I2C Clock E22, H26
I2C3_SDA IOD I2C Data B21, F27

Table 5-34. I2C4 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
I2C4_SCL IOD I2C Clock D22, R27
I2C4_SDA IOD I2C Data C22, P21

5.3.13.2 MCU Domain

Table 5-35. MCU_I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_I2C0_SCL IOD I2C Clock B13
MCU_I2C0_SDA IOD I2C Data E11

5.3.13.3 WKUP Domain

Table 5-36. WKUP_I2C0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
WKUP_I2C0_SCL IOD I2C Clock B9
WKUP_I2C0_SDA IOD I2C Data D11

5.3.14 MCAN
5.3.14.1 MAIN Domain
Table 5-37. MCAN0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCAN0_RX I MCAN Receive Data C22
MCAN0_TX O MCAN Transmit Data D22

Table 5-38. MCAN1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCAN1_RX I MCAN Receive Data A24, J23, P23
MCAN1_TX O MCAN Transmit Data B24, H25, P22

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5.3.14.2 MCU Domain

Table 5-39. MCU_MCAN0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_MCAN0_RX I MCAN Receive Data D8
MCU_MCAN0_TX O MCAN Transmit Data B2

Table 5-40. MCU_MCAN1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_MCAN1_RX I MCAN Receive Data B1
MCU_MCAN1_TX O MCAN Transmit Data C1

5.3.15 MCASP
5.3.15.1 MAIN Domain
Table 5-41. MCASP0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCASP0_ACLKR IO MCASP Receive Bit Clock F24
MCASP0_ACLKX IO MCASP Transmit Bit Clock D25
MCASP0_AFSR IO MCASP Receive Frame Sync C27
MCASP0_AFSX IO MCASP Transmit Frame Sync C26
MCASP0_AXR0 IO MCASP Serial Data (Input/Output) F23
MCASP0_AXR1 IO MCASP Serial Data (Input/Output) B25
MCASP0_AXR2 IO MCASP Serial Data (Input/Output) A26
MCASP0_AXR3 IO MCASP Serial Data (Input/Output) A25

Table 5-42. MCASP1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCASP1_ACLKR IO MCASP Receive Bit Clock H26, J22, P23
MCASP1_ACLKX IO MCASP Transmit Bit Clock F26, N27, P27
MCASP1_AFSR IO MCASP Receive Frame Sync F27, K22, P22
MCASP1_AFSX IO MCASP Transmit Frame Sync H21, M27, V21
MCASP1_AXR0 IO MCASP Serial Data (Input/Output) G26, M26, N23
MCASP1_AXR1 IO MCASP Serial Data (Input/Output) G27, L21, N22
MCASP1_AXR2 IO MCASP Serial Data (Input/Output) H27, K22, N21
MCASP1_AXR3 IO MCASP Serial Data (Input/Output) J22, J27, T23
MCASP1_AXR4 IO MCASP Serial Data (Input/Output) F27, P22
MCASP1_AXR5 IO MCASP Serial Data (Input/Output) H26, P23

Table 5-43. MCASP2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCASP2_ACLKR IO MCASP Receive Bit Clock V23
MCASP2_ACLKX IO MCASP Transmit Bit Clock B21, V24
MCASP2_AFSR IO MCASP Receive Frame Sync V22
MCASP2_AFSX IO MCASP Transmit Frame Sync E22, V26

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Table 5-43. MCASP2 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCASP2_AXR0 IO MCASP Serial Data (Input/Output) D22, U27
MCASP2_AXR1 IO MCASP Serial Data (Input/Output) C22, U26
MCASP2_AXR2 IO MCASP Serial Data (Input/Output) V27
MCASP2_AXR3 IO MCASP Serial Data (Input/Output) V25
MCASP2_AXR4 IO MCASP Serial Data (Input/Output) R22, V22
MCASP2_AXR5 IO MCASP Serial Data (Input/Output) R23, V23
MCASP2_AXR6 IO MCASP Serial Data (Input/Output) R26
MCASP2_AXR7 IO MCASP Serial Data (Input/Output) T27
MCASP2_AXR8 IO MCASP Serial Data (Input/Output) T25
MCASP2_AXR9 IO MCASP Serial Data (Input/Output) T24
MCASP2_AXR10 IO MCASP Serial Data (Input/Output) T21
MCASP2_AXR11 IO MCASP Serial Data (Input/Output) T22
MCASP2_AXR12 IO MCASP Serial Data (Input/Output) P26
MCASP2_AXR13 IO MCASP Serial Data (Input/Output) N25
MCASP2_AXR14 IO MCASP Serial Data (Input/Output) R27
MCASP2_AXR15 IO MCASP Serial Data (Input/Output) P21

Table 5-44. MCASP3 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCASP3_ACLKR IO MCASP Receive Bit Clock Y26
MCASP3_ACLKX IO MCASP Transmit Bit Clock W27
MCASP3_AFSR IO MCASP Receive Frame Sync Y27
MCASP3_AFSX IO MCASP Transmit Frame Sync W25
MCASP3_AXR0 IO MCASP Serial Data (Input/Output) W24
MCASP3_AXR1 IO MCASP Serial Data (Input/Output) W23
MCASP3_AXR2 IO MCASP Serial Data (Input/Output) W22
MCASP3_AXR3 IO MCASP Serial Data (Input/Output) W21
MCASP3_AXR4 IO MCASP Serial Data (Input/Output) AA24
MCASP3_AXR5 IO MCASP Serial Data (Input/Output) AA27
MCASP3_AXR6 IO MCASP Serial Data (Input/Output) Y26
MCASP3_AXR7 IO MCASP Serial Data (Input/Output) Y27
MCASP3_AXR8 IO MCASP Serial Data (Input/Output) J27
MCASP3_AXR9 IO MCASP Serial Data (Input/Output) H27

Table 5-45. MCASP4 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCASP4_ACLKR IO MCASP Receive Bit Clock AA25
MCASP4_ACLKX IO MCASP Transmit Bit Clock AB23
MCASP4_AFSR IO MCASP Receive Frame Sync AB25
MCASP4_AFSX IO MCASP Transmit Frame Sync AC26
MCASP4_AXR0 IO MCASP Serial Data (Input/Output) AA23
MCASP4_AXR1 IO MCASP Serial Data (Input/Output) AA22
MCASP4_AXR2 IO MCASP Serial Data (Input/Output) AB26

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Table 5-45. MCASP4 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCASP4_AXR3 IO MCASP Serial Data (Input/Output) AB27
MCASP4_AXR4 IO MCASP Serial Data (Input/Output) AB24
MCASP4_AXR5 IO MCASP Serial Data (Input/Output) AC27
MCASP4_AXR6 IO MCASP Serial Data (Input/Output) AA25
MCASP4_AXR7 IO MCASP Serial Data (Input/Output) AB25
MCASP4_AXR8 IO MCASP Serial Data (Input/Output) G27
MCASP4_AXR9 IO MCASP Serial Data (Input/Output) G26

5.3.16 MCSPI
5.3.16.1 MAIN Domain
Table 5-46. MCSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
SPI0_CLK IO SPI Clock D20
SPI0_CS0 IO SPI Chip Select 0 B20
SPI0_CS1 IO SPI Chip Select 1 C20
SPI0_CS2 IO SPI Chip Select 2 E22
SPI0_CS3 IO SPI Chip Select 3 B21
SPI0_D0 IO SPI Data 0 E19
SPI0_D1 IO SPI Data 1 E20

Table 5-47. MCSPI1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
SPI1_CLK IO SPI Clock H22, M26
SPI1_CS0 IO SPI Chip Select 0 H24, L21
SPI1_CS1 IO SPI Chip Select 1 A24, K22
SPI1_CS2 IO SPI Chip Select 2 H20
SPI1_CS3 I SPI Chip Select 3 B24
SPI1_D0 IO SPI Data 0 H25, N27
SPI1_D1 IO SPI Data 1 J23, M27

Table 5-48. MCSPI2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
SPI2_CLK IO SPI Clock A22, B24, F24
SPI2_CS0 IO SPI Chip Select 0 C27, D23, H22
SPI2_CS1 IO SPI Chip Select 1 C24, D25, H25
SPI2_CS2 IO SPI Chip Select 2 B22, B25, H24
SPI2_CS3 IO SPI Chip Select 3 A23, C26, J23
SPI2_D0 IO SPI Data 0 A25, F19, H20
SPI2_D1 IO SPI Data 1 A26, F20, H23

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5.3.16.2 MCU Domain

Table 5-49. MCU_MCSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_SPI0_CLK IO SPI Clock A9
MCU_SPI0_CS0 IO SPI Chip Select 0 C12
MCU_SPI0_CS1 IO SPI Chip Select 1 A10
MCU_SPI0_CS2 IO SPI Chip Select 2 B1, B3
MCU_SPI0_CS3 IO SPI Chip Select 3 B2
MCU_SPI0_D0 IO SPI Data 0 B12
MCU_SPI0_D1 IO SPI Data 1 C11

Table 5-50. MCU_MCSPI1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_SPI1_CLK IO SPI Clock B1, C3
MCU_SPI1_CS0 IO SPI Chip Select 0 C4
MCU_SPI1_CS1 IO SPI Chip Select 2 C1
MCU_SPI1_CS2 IO SPI Chip Select 2 B1, C8
MCU_SPI1_CS3 IO SPI Chip Select 3 D8
MCU_SPI1_D0 IO SPI Data 0 B5
MCU_SPI1_D1 IO SPI Data 1 C5

5.3.17 MDIO
5.3.17.1 MAIN Domain
Table 5-51. MDIO0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MDIO0_MDC O MDIO Clock AC24
MDIO0_MDIO IO MDIO Data AD25

5.3.18 MMC
5.3.18.1 MAIN Domain
Table 5-52. MMC0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MMC0_CALPAD (1) A MMC/SD/SDIO Calibration Resistor AC1
MMC0_CLK IO MMC/SD/SDIO Clock AE1
MMC0_CMD IO MMC/SD/SDIO Command AE2
MMC0_DS IO MMC Data Strobe AD1
MMC0_DAT0 IO MMC/SD/SDIO Data AD3
MMC0_DAT1 IO MMC/SD/SDIO Data AD2
MMC0_DAT2 IO MMC/SD/SDIO Data AB4
MMC0_DAT3 IO MMC/SD/SDIO Data AC2
MMC0_DAT4 IO MMC/SD/SDIO Data AC3
MMC0_DAT5 IO MMC/SD/SDIO Data AB3
MMC0_DAT6 IO MMC/SD/SDIO Data AF1

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Table 5-52. MMC0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MMC0_DAT7 IO MMC/SD/SDIO Data AB2

(1) An external 10 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.

Table 5-53. MMC1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MMC1_CLK IO MMC/SD/SDIO Clock H24
MMC1_CMD IO MMC/SD/SDIO Command H22
MMC1_SDCD I SD Card Detect B24
MMC1_SDWP I SD Write Protect A24
MMC1_DAT0 IO MMC/SD/SDIO Data H23
MMC1_DAT1 IO MMC/SD/SDIO Data H20
MMC1_DAT2 IO MMC/SD/SDIO Data J23
MMC1_DAT3 IO MMC/SD/SDIO Data H25

Table 5-54. MMC2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MMC2_CLK IO MMC/SD/SDIO Clock H26
MMC2_CMD IO MMC/SD/SDIO Command F27
MMC2_SDCD I SD Card Detect C24, E22, F26
MMC2_SDWP I SD Write Protect A22, B21, H21
MMC2_DAT0 IO MMC/SD/SDIO Data G26
MMC2_DAT1 IO MMC/SD/SDIO Data G27
MMC2_DAT2 IO MMC/SD/SDIO Data H27
MMC2_DAT3 IO MMC/SD/SDIO Data J27

5.3.19 OLDI
5.3.19.1 MAIN Domain
Table 5-55. OLDI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
OLDI0_A0N IO OLDI Differential Data (negative) AF23
OLDI0_A0P IO OLDI Differential Data (positive) AG24
OLDI0_A1N IO OLDI Differential Data (negative) AG22
OLDI0_A1P IO OLDI Differential Data (positive) AG23
OLDI0_A2N IO OLDI Differential Data (negative) AB20
OLDI0_A2P IO OLDI Differential Data (positive) AB21
OLDI0_A3N IO OLDI Differential Data (negative) AG20
OLDI0_A3P IO OLDI Differential Data (positive) AG21
OLDI0_A4N IO OLDI Differential Data (negative) AD21
OLDI0_A4P IO OLDI Differential Data (positive) AC21
OLDI0_A5N IO OLDI Differential Data (negative) AF19
OLDI0_A5P IO OLDI Differential Data (positive) AF18
OLDI0_A6N IO OLDI Differential Data (negative) AG17
OLDI0_A6P IO OLDI Differential Data (positive) AG18

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Table 5-55. OLDI0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
OLDI0_A7N IO OLDI Differential Data (negative) AB19
OLDI0_A7P IO OLDI Differential Data (positive) AA20
OLDI0_CLK0N IO OLDI Differential Clock (negative) AF21
OLDI0_CLK0P IO OLDI Differential Clock (positive) AE20
OLDI0_CLK1N IO OLDI Differential Clock (negative) AD20
OLDI0_CLK1P IO OLDI Differential Clock (positive) AE19

5.3.20 OSPI
5.3.20.1 MAIN Domain
Table 5-56. OSPI0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
OSPI0_CLK O OSPI Clock L24
OSPI0_DQS I OSPI Data Strobe (DQS) or Loopback Clock Input L22
OSPI0_ECC_FAIL I OSPI ECC Status J22
OSPI0_LBCLKO IO OSPI Loopback Clock Output L23
OSPI0_CSn0 O OSPI Chip Select 0 (active low) K26
OSPI0_CSn1 O OSPI Chip Select 1 (active low) K23
OSPI0_CSn2 O OSPI Chip Select 2 (active low) K22
OSPI0_CSn3 O OSPI Chip Select 3 (active low) J22
OSPI0_D0 IO OSPI Data 0 K27
OSPI0_D1 IO OSPI Data 1 L27
OSPI0_D2 IO OSPI Data 2 L26
OSPI0_D3 IO OSPI Data 3 L25
OSPI0_D4 IO OSPI Data 4 L21
OSPI0_D5 IO OSPI Data 5 M26
OSPI0_D6 IO OSPI Data 6 N27
OSPI0_D7 IO OSPI Data 7 M27
OSPI0_RESET_OUT0 O OSPI Reset J22
OSPI0_RESET_OUT1 O OSPI Reset K22

5.3.21 Power Supply

Table 5-57. Power Supply Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
CAP_VDDS0 (1) CAP External capacitor connection for IO group 0 H17
CAP_VDDS1 (1) CAP External capacitor connection for IO group 1 L19
CAP_VDDS2 (1) CAP External capacitor connection for IO group 2 U20
CAP_VDDS3 (1) CAP External capacitor connection for IO group 3 N20
CAP_VDDS5 (1) CAP External capacitor connection for IO group 5 G19
CAP_VDDS6 (1) CAP External capacitor connection for IO group 6 J20
CAP_VDDS_CANUART (1) CAP External capacitor connection for IO CANUART H8
CAP_VDDS_MCU (1) CAP External capacitor connection for IO MCU J10
VDDA_0P85_SERDES PWR SERDES analog supply H12, H13
VDDA_0P85_SERDES_C PWR SERDES clock analog supply J13

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Table 5-57. Power Supply Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
VDDA_0P85_DLL_MMC0 PWR MMC0 DLL analog supply W9
VDDA_1P8_CSI_DSI PWR CSIRX and DSITX 1.8 V analog supply W13, W16, Y13
VDDA_1P8_SERDES PWR SERDES 1.8 V analog supply G13
VDDA_1P8_OLDI0 PWR OLDI analog supply W18, Y19
VDDA_1P8_USB0 PWR USB 1.8 V analog supply Y12
VDDA_1P8_USB1 PWR USB 1.8 V analog supply H16
VDDA_3P3_USB0 PWR USB 3.3 V analog supply Y11
VDDA_3P3_USB1 PWR USB 3.3 V analog supply G15
VDDA_CORE_CSI_DSI PWR CSIRX and DSITX Core supply W15, Y15
VDDA_CORE_CSI_DSI_CLK PWR CSIRX and DSITX clock Core supply Y16
VDDA_CORE_USB0 PWR USB Core Supply W11
VDDA_CORE_USB1 PWR USB Core Supply H15
VDDA_DDR_PLL0 PWR DDR Deskew PLL analog supply P9
VDDA_MCU PWR POR and MCU PLL analog supply G11, H11
VDDA_PLL0 PWR MAIN PLL analog supply L15
VDDA_PLL1 PWR PER0 PLL and PER1 PLL analog supply K10
VDDA_PLL2 PWR VIDEO PLL analog supply M12
VDDA_PLL3 PWR C7x PLL and DSS PLL analog supply R11
VDDA_PLL4 PWR ARM0 PLL and SMS PLL analog supply V18
VDDA_PLL5 PWR DDR PLL analog supply P16
VDDA_TEMP0 PWR TEMP0 analog supply Y17
VDDA_TEMP1 PWR TEMP1 analog supply T11
VDDA_TEMP2 PWR TEMP2 analog supply L9
VDDR_CORE PWR Core Supply M13, M19, N13, N19,
U10, U17, V10, V17
VDDSHV0 PWR IO supply for IO group 0 G18, H18
VDDSHV1 PWR IO supply for IO group 1 K20, L20
VDDSHV2 PWR IO supply for IO group 2 T19, T20
VDDSHV3 PWR IO supply for IO group 3 M20, P20, R20
VDDSHV5 PWR IO supply for IO group 5 H19
VDDSHV6 PWR IO supply for IO group 6 J21
VDDSHV_CANUART PWR IO supply for IO CANUART H9
VDDSHV_MCU PWR IO supply for IO MCU H10
VDDS_DDR PWR DDR PHY IO supply AB1, D1, L7, L8, N7,
N8, T7, T8
VDDS_DDR_C PWR DDR clock IO supply P8
VDDS_MMC0 PWR MMC0 PHY IO supply Y9
VDDS_OSC0 PWR MCU_OSC0 supply K8
VDD_CANUART PWR CANUART Core Supply J8

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Table 5-57. Power Supply Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
VDD_CORE PWR Core supply J11, J14, J16, J18,
K11, K12, K14, K16,
K18, K9, L12, L17,
M10, M15, M17, M9,
N10, N11, N14, N16,
N18, P11, P12, P14,
P18, R12, R13, R15,
R17, R9, T13, T15,
T17, T9, U12, U14,
U16, U8, V12, V14,
V16, V19, V8, W19,
Y20, Y21
VDD_MMC0 PWR MMC0 PHY core supply W10
VPP PWR eFuse ROM programming supply G9
VSS GND Ground A1, A18, A21, A27,
A4, A7, AA1, AA18,
AA21, AA26, AA4,
AD26, AG1, AG27,
C2, C23, D26, E6,
F15, F16, F17, F2,
F21, G1, G10, G12,
G14, G16, G17, G20,
G3, G5, G8, H14, H4,
H7, J12, J15, J17,
J19, J26, J3, J5, J9,
K1, K13, K15, K17,
K19, L10, L11, L13,
L14, L16, L18, M1,
M11, M14, M16, M18,
M7, M8, N12, N15,
N17, N26, N9, P10,
P13, P15, P17, P19,
P5, P7, R1, R10,
R14, R16, R18, R19,
R4, R7, R8, T10, T12,
T14, T16, T18, T26,
U11, U13, U15, U18,
U19, U3, U7, U9, V1,
V11, V13, V15, V20,
V4, V7, V9, W12,
W14, W17, W20, W5,
W8, Y10, Y14, Y18,
Y7, Y8

(1) This pin must always be connected via a 1-μF capacitor to VSS.
5.3.22 Reserved
Table 5-58. Reserved Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
RSVD0 N/A Reserved, must be left unconnected E9
RSVD1 N/A Reserved, must be left unconnected AA19
RSVD2 N/A Reserved, must be left unconnected AB7
RSVD3 N/A Reserved, must be left unconnected AC5
RSVD4 N/A Reserved, must be left unconnected AB10
RSVD5 N/A Reserved, must be left unconnected AA12
RSVD6 N/A Reserved, must be left unconnected AB12
RSVD7 N/A Reserved, must be left unconnected AB13

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Table 5-58. Reserved Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
RSVD8 N/A Reserved, must be left unconnected AA15
RSVD9 N/A Reserved, must be left unconnected AA14
RSVD10 N/A Reserved, must be left unconnected L5
RSVD11 N/A Reserved, must be left unconnected M6
RSVD12 N/A Reserved, must be left unconnected AB16
RSVD13 N/A Reserved, must be left unconnected AB18
RSVD14 N/A Reserved, must be left unconnected C6
RSVD15 N/A Reserved, must be left unconnected F8
RSVD16 N/A Reserved, must be left unconnected B6
RSVD17 N/A Reserved, must be left unconnected C17
RSVD18 N/A Reserved, must be left unconnected D16
RSVD19 N/A Reserved, must be left unconnected D14
RSVD20 N/A Reserved, must be left unconnected D13
RSVD21 N/A Reserved, must be left unconnected M2

5.3.23 SERDES
5.3.23.1 MAIN Domain
Table 5-59. PCIE0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
PCIE0_CLKREQn IOD PCIE Clock Request Signal F25

Table 5-60. SERDES0 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] ((2)) DESCRIPTION [3] AMW PIN [4]
[2]
SERDES0_REXT (1) A SERDES PHY External Calibration Resistor E15
SERDES0_REFCLK0N IO SERDES PHY Reference Clock Input/Output (negative) A17
SERDES0_REFCLK0P IO SERDES PHY Reference Clock Input/Output (positive) A16
SERDES0_RX0_N I SERDES PHY Differential Receive Data (negative) A20
SERDES0_RX0_P I SERDES PHY Differential Receive Data (positive) A19
SERDES0_TX0_N O SERDES PHY Differential Transmit Data (negative) B19
SERDES0_TX0_P O SERDES PHY Differential Transmit Data (positive) B18

(1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.
(2) The functionality of these pins is controlled by SERDES0_LN0_CTRL.

Table 5-61. SERDES1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] ((2)) DESCRIPTION [3] AMW PIN [4]
[2]
SERDES1_REXT (1) A SERDES PHY External Calibration Resistor F14
SERDES1_REFCLK0N IO SERDES PHY Reference Clock Input/Output (negative) B15
SERDES1_REFCLK0P IO SERDES PHY Reference Clock Input/Output (positive) B16
SERDES1_RX0_N I SERDES PHY Differential Receive Data (negative) C14
SERDES1_RX0_P I SERDES PHY Differential Receive Data (positive) C15
SERDES1_TX0_N O SERDES PHY Differential Transmit Data (negative) A13
SERDES1_TX0_P O SERDES PHY Differential Transmit Data (positive) A14

(1) An external 3.01 kΩ ±1% resistor must be connected between this pin and VSS. No external voltage should be applied to this pin.

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(2) The functionality of these pins is controlled by SERDES1_LN0_CTRL.

5.3.24 System and Miscellaneous
5.3.24.1 Boot Mode Configuration
5.3.24.1.1 MAIN Domain
Table 5-62. Sysboot Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
BOOTMODE00 I Bootmode pin 0 R22
BOOTMODE01 I Bootmode pin 1 R23
BOOTMODE02 I Bootmode pin 2 R26
BOOTMODE03 I Bootmode pin 3 T27
BOOTMODE04 I Bootmode pin 4 T25
BOOTMODE05 I Bootmode pin 5 T24
BOOTMODE06 I Bootmode pin 6 T21
BOOTMODE07 I Bootmode pin 7 T22
BOOTMODE08 I Bootmode pin 8 U27
BOOTMODE09 I Bootmode pin 9 U26
BOOTMODE10 I Bootmode pin 10 V27
BOOTMODE11 I Bootmode pin 11 V25
BOOTMODE12 I Bootmode pin 12 V26
BOOTMODE13 I Bootmode pin 13 V24
BOOTMODE14 I Bootmode pin 14 V22
BOOTMODE15 I Bootmode pin 15 V23

5.3.24.2 Clock
5.3.24.2.1 MCU Domain
Table 5-63. MCU Clock Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_OSC0_XI I High frequency oscillator input A5
MCU_OSC0_XO O High frequency oscillator output A6

5.3.24.2.2 WKUP Domain

Table 5-64. WKUP Clock Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
WKUP_LFOSC0_XI I Low frequency (32.768 KHz) oscillator input A3
WKUP_LFOSC0_XO O Low frequency (32.768 KHz) oscillator output A2

5.3.24.3 System
5.3.24.3.1 MAIN Domain
Table 5-65. System Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
AUDIO_EXT_REFCLK0 IO External clock input to McASP or output from McASP E22, F23, W23
AUDIO_EXT_REFCLK1 IO External clock input to McASP or output from McASP B21, C26, N24
AUDIO_EXT_REFCLK2 IO External clock input to McASP or output from McASP W26

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Table 5-65. System Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
CLKOUT0 O RMII Clock Output (50 MHz). This pin is used for clock A23, AA22, AF24
source to the external RMII PHY and must also be routed
back to the respective RMII[x]_REF_CLK pin for proper
device operation.
EXTINTn I External Interrupt B23
EXT_REFCLK1 I External clock input to Main Domain A23
MAIN_ERRORn IO Error signal output from MAIN Domain ESM B25, C20, N25
OBSCLK0 O Main Domain Observation clock output for test and V27
debug purposes only
OBSCLK1 O Main Domain Observation clock output for test and D23
debug purposes only
PORz_OUT O Main Domain POR status output D27
RESETSTATz O Main Domain warm reset status output E27
RESET_REQz I Main Domain external warm reset request input E26
SYNC0_OUT O CPTS Time Stamp Generator Bit 0 Output from Time D23
Sync Router
SYNC1_OUT O CPTS Time Stamp Generator Bit 1 Output from Time A23
Sync Router
SYNC2_OUT O CPTS Time Stamp Generator Bit 2 Output from Time D22
Sync Router
SYNC3_OUT O CPTS Time Stamp Generator Bit 3 Output from Time C22
Sync Router
SYSCLKOUT0 O Main Domain system clock output (divided by 4) for test A23
and debug purposes only

5.3.24.3.2 MCU Domain

Table 5-66. MCU System Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_ERRORn IO Error signal output from MCU Domain ESM B7
MCU_EXT_REFCLK0 I External input to MCU Domain A10, C1
MCU_OBSCLK0 O MCU Domain Observation clock output for test and A10
debug purposes only
MCU_PORz I MCU and Main Domain cold reset E8
MCU_RESETSTATz O MCU Domain warm reset status output E13
MCU_RESETz I MCU and Main Domain warm reset D10
MCU_SYSCLKOUT0 O MCU Domain system clock output (divided by 4) for test A10
and debug purposes only

5.3.24.3.3 WKUP Domain

Table 5-67. WKUP System Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
PMIC_LPM_EN0 O Dual-function PMIC control output, Low Power Mode A8
(active low) or PMIC Enable (active high)
WKUP_CLKOUT0 O WKUP Domain CLKOUT0 output F12

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5.3.24.4 VMON
Table 5-68. VMON Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
VMON_1P8_SOC A Voltage monitor input for 1.8 V SoC power supply J7
VMON_3P3_SOC A Voltage monitor input for 3.3 V SoC power supply K7
VMON_ER_VSYS A Voltage monitor input, fixed 0.45 V (+/-3%) threshold. G7
Use with external precision voltage divider to monitor a
higher voltage rail such as the PMIC input supply.

5.3.25 TIMER
5.3.25.1 MAIN Domain
Table 5-69. TIMER Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
TIMER_IO0 IO Timer Inputs and Outputs (not tied to single timer C24, H25
instance)
TIMER_IO1 IO Timer Inputs and Outputs (not tied to single timer A22, J23
instance)
TIMER_IO2 IO Timer Inputs and Outputs (not tied to single timer D22, H20
instance)
TIMER_IO3 IO Timer Inputs and Outputs (not tied to single timer C22, H23
instance)
TIMER_IO4 IO Timer Inputs and Outputs (not tied to single timer A23, H24
instance)
TIMER_IO5 IO Timer Inputs and Outputs (not tied to single timer B22, H22
instance)
TIMER_IO6 I Timer Inputs and Outputs (not tied to single timer B24, E22
instance)
TIMER_IO7 IO Timer Inputs and Outputs (not tied to single timer A24, B21
instance)

5.3.25.2 MCU Domain

Table 5-70. MCU_TIMER Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_TIMER_IO0 IO Timer Inputs and Outputs (not tied to single timer B5, D8
instance)
MCU_TIMER_IO1 IO Timer Inputs and Outputs (not tied to single timer A10, C5
instance)
MCU_TIMER_IO2 IO Timer Inputs and Outputs (not tied to single timer C1
instance)
MCU_TIMER_IO3 IO Timer Inputs and Outputs (not tied to single timer B1
instance)

5.3.25.3 WKUP Domain

Table 5-71. WKUP_TIMER Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
WKUP_TIMER_IO0 IO Timer Inputs and Outputs (not tied to single timer B2, C4
instance)

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Table 5-71. WKUP_TIMER Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
WKUP_TIMER_IO1 IO Timer Inputs and Outputs (not tied to single timer C12, C3
instance)

5.3.26 UART
5.3.26.1 MAIN Domain
Table 5-72. UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
UART0_CTSn I UART Clear to Send (active low) E22
UART0_RTSn O UART Request to Send (active low) B21
UART0_RXD I UART Receive Data F19
UART0_TXD O UART Transmit Data F20

Table 5-73. UART1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
UART1_CTSn I UART Clear to Send (active low) A25
UART1_DCDn I UART Clear to Send (active low) D23
UART1_DSRn I UART Data Set Ready (active low) B22
UART1_DTRn O UART Data Terminal Ready (active low) D22
UART1_RIn I UART Ring Indicator C22
UART1_RTSn O UART Request to Send (active low) A26
UART1_RXD I UART Receive Data C24, C27
UART1_TXD O UART Transmit Data A22, F24

Table 5-74. UART2 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
UART2_CTSn I UART Clear to Send (active low) AC26, H23, V22
UART2_RTSn IO UART Request to Send (active low) AB23, H20, V23
UART2_RXD I UART Receive Data E22, H25, U27, W27
UART2_TXD IO UART Transmit Data B21, J23, U26, W25

Table 5-75. UART3 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
UART3_CTSn I UART Clear to Send (active low) A24, AC27
UART3_RTSn I UART Request to Send (active low) AB24, B24
UART3_RXD I UART Receive Data H24, V27, W24
UART3_TXD IO UART Transmit Data H22, V25, W23

Table 5-76. UART4 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
UART4_CTSn I UART Clear to Send (active low) AB27
UART4_RTSn O UART Request to Send (active low) AB26
UART4_RXD I UART Receive Data F26, P22, V26, W22

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Table 5-76. UART4 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
UART4_TXD O UART Transmit Data H21, P23, V24, W21

Table 5-77. UART5 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
UART5_CTSn I UART Clear to Send (active low) AA22, L22
UART5_RTSn O UART Request to Send (active low) AA23, L23
UART5_RXD I UART Receive Data D22, J27, K22, V22,
Y26
UART5_TXD O UART Transmit Data C22, H27, J22, V23,
Y27

Table 5-78. UART6 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
UART6_CTSn I UART Clear to Send (active low) AB25, M27
UART6_RTSn O UART Request to Send (active low) AA25, N27
UART6_RXD I UART Receive Data A25, AA24, B24, H26,
L21, W26
UART6_TXD O UART Transmit Data A24, A26, AA27, F27,
M26, N24

5.3.26.2 MCU Domain

Table 5-79. MCU_UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
MCU_UART0_CTSn I UART Clear to Send (active low) B5
MCU_UART0_RTSn O UART Request to Send (active low) C5
MCU_UART0_RXD I UART Receive Data B8
MCU_UART0_TXD O UART Transmit Data B4

5.3.26.3 WKUP Domain

Table 5-80. WKUP_UART0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
WKUP_UART0_CTSn I UART Clear to Send (active low) C4
WKUP_UART0_RTSn O UART Request to Send (active low) C3
WKUP_UART0_RXD I UART Receive Data B3
WKUP_UART0_TXD O UART Transmit Data C8

5.3.27 USB
5.3.27.1 MAIN Domain
Table 5-81. USB0 Signal Descriptions
PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
USB0_DM IO USB 2.0 Differential Data (negative) AB5
USB0_DP IO USB 2.0 Differential Data (positive) AA6

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Table 5-81. USB0 Signal Descriptions (continued)

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
USB0_DRVVBUS O USB VBUS control output (active high) E25
USB0_RCALIB (1) A Pin to connect to calibration resistor AA8
USB0_VBUS (2) A USB Level-shifted VBUS Input W7

(1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
(2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.2.3, USB
VBUS Design Guidelines.

Table 5-82. USB1 Signal Descriptions

PIN TYPE
SIGNAL NAME [1] DESCRIPTION [3] AMW PIN [4]
[2]
USB1_DM IO USB 2.0 Differential Data (negative) E17
USB1_DP IO USB 2.0 Differential Data (positive) D17
USB1_DRVVBUS O USB VBUS control output (active high) B27
USB1_RCALIB (1) A Pin to connect to calibration resistor E18
USB1_VBUS (2) A USB Level-shifted VBUS Input F18

(1) An external 499 Ω ±1% resistor must be connected between this pin and VSS and the maximum power dissipation for the resistor is
7.2mW. No external voltage should be applied to this pin.
(2) An external resistor divider is required to limit the voltage applied to the device pin. For more information, see Section 8.2.3, USB
VBUS Design Guidelines.
5.4 Pin Connectivity Requirements
This section describes connectivity requirements for package balls that have specific connectivity requirements
and unused package balls.

Note
All power pins must be supplied with the voltages specified in Recommended Operating Conditions,
unless otherwise specified.

Note
For additional clarification, "leave unconnected" or "no connect" (NC) means no signal traces can be
connected to these device ball numbers.

Table 5-83. Connectivity Requirements

AMW
BALL BALL NAME CONNECTION REQUIREMENTS
NUMBER
Each of these balls must be connected to VSS through separate external pull
resistors to ensure these balls are held to a valid logic-low level if a PCB signal
B10 TRSTn trace is connected and not actively driven by an attached device. The internal
pull-down can be used to hold a valid logic-low level if no PCB signal trace is
connected to the ball.
Each of these balls must be connected to the corresponding power supply(1)
A11 TCK through separate external pull resistors to ensure the inputs associated with
E12 TDI these balls are held to a valid logic-high level if a PCB signal trace is connected
F11 TMS and not actively driven by an attached device. The internal pull-up can be used
to hold a valid logic-high level if no PCB signal trace is connected to the ball.

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Table 5-83. Connectivity Requirements (continued)

AMW
BALL BALL NAME CONNECTION REQUIREMENTS
NUMBER
C9 EMU0
F9 EMU1
D10 MCU_RESETz
E26 RESET_REQz
E8 MCU_PORz
B23 EXTINTN
Each of these balls must be connected to the corresponding power supply(1)
B13 MCU_I2C0_SCL
through separate external pull resistors to ensure the inputs associated with
E11 MCU_I2C0_SDA
these balls are held to a valid logic-high level, if unused.
B9 WKUP_I2C0_SCL
D11 WKUP_I2C0_SDA
F1 DDR0_DQS0_n
J1 DDR0_DQS1_n
U1 DDR0_DQS2_n
T1 DDR0_DQS3_n
R22 GPMC0_AD0
R23 GPMC0_AD1
R26 GPMC0_AD2
T27 GPMC0_AD3
T25 GPMC0_AD4
T24 GPMC0_AD5
T21 GPMC0_AD6 Each of these balls must be connected to the corresponding power supply(1)
T22 GPMC0_AD7 or VSS through separate external pull resistors to ensure the inputs associated
U27 GPMC0_AD8 with these balls are held to a valid logic-high or logic-low level as appropriate to
U26 GPMC0_AD9 select the desired device boot mode.
V27 GPMC0_AD10
V25 GPMC0_AD11
V26 GPMC0_AD12
V24 GPMC0_AD13
V22 GPMC0_AD14
V23 GPMC0_AD15
E1 DDR0_DQS0
H1 DDR0_DQS1
T1 DDR0_DQS2
W1 DDR0_DQS3 Each of these balls must be connected to VSS through separate external pull
G7 VMON_ER_VSYS resistors to ensure these balls are held to a valid logic-low level, if unused.
J7 VMON_1P8_SOC
K7 VMON_3P3_SOC
A3 WKUP_LFOSC0_XI
E15 SERDES0_REXT
F14 SERDES1_REXT
AB8 CSI0_RXRCALIB
Each of these balls must be connected to VSS through an appropriate external
AA10 CSI1_RXRCALIB
pull resistor to ensure these balls are held to a valid logic-low level, if unused.
AB14 CSI2_RXRCALIB
Refer to Signal Descriptions footnote for appropriate value of pull resistor for
AB15 CSI3_RXRCALIB
each signal.
AA16 DSI0_TXRCALIB
AA8 USB0_RCALIB
E18 USB1_RCALIB
G9 VPP
Each of these balls must be left unconnected, if unused.
AC1 MMC0_CALPAD

(1) To determine which power supply is associated with any IO, see the POWER column of the Pin Attributes table.

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Note
All other unused signal balls with a Pad Configuration Register can be left unconnected with their
multiplexing mode set to GPIO input and internal pull-down resistor enabled. Unused balls are defined
as those which only connect to a PCB solder pad. This is the only use case where internal pull
resistors are allowed as the only source/sink to hold a valid logic level. Any balls connected to a via,
test point, or PCB trace are consider used and must not depend on the internal pull resistor to hold a
valid logic level.
Internal pull resistors are weak and may not source enough current to maintain a valid logic level
for some operating conditions. This can be the case when connected to components with leakage
to the opposite logic level, or when external noise sources couple to signal traces attached to balls
which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors are
recommended to hold a valid logic level on balls with external connections.
Many of the device IOs are turned off by default and external pull resistors may be required to hold
inputs of any attached device in a valid logic state until software initializes the respective IOs. The
state of configurable device IOs are defined in the BALL STATE DURING RESET RX/TX/PULL and
BALL STATE AFTER RESET RX/TX/PULL columns of the Pin Attributes table. Any IO with its input
buffer (RX) turned off is allowed to float without damaging the device. However, any IO with its input
buffer (RX) turned on shall never be allowed to float to any potential between VILSS and VIHSS. The
input buffer can enter a high-current state which could damage the IO cell if allowed to float between
these levels.

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6 Specifications
Note
All specifications listed are preliminary and may change during device characterization.

6.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)(1) (2)
PARAMETER MIN MAX UNIT
VDD_CORE Core supply -0.3 1.05 V
VDDR_CORE RAM core supply -0.3 1.05 V
VDD_CANUART CANUART core supply -0.3 1.05 V
VDDA_CORE_CSI_DSI CSIRX0 and DSITX0 core supply -0.3 1.05 V
VDDA_CORE_CSI_DSI_CLK CSIRX0 and DSITX0 clock core supply -0.3 1.05 V
VDDA_CORE_USB0
USB0 and USB1 core supply -0.3 1.05 V
VDDA_CORE_USB1
VDDA_DDR_PLL0 DDR deskew PLL supply -0.3 1.05 V
VDD_MMC0 MMC0 PHY core supply -0.3 1.05 V
VDDA_0P85_DLL_MMC0 MMC0 DLL analog supply -0.3 1.05 V
VDDA_0P85_SERDES
SERDES analog supply -0.3 1.05 V
VDDA_0P85_SERDES_C
VDDS_DDR DDR PHY IO supply -0.3 1.57 V
VDDS_DDR_C DDR clock IO supply -0.3 1.57 V
VDDA_1P8_SERDES SERDES PHY IO supply -0.3 1.98 V
VDDS_MMC0 MMC0 PHY IO supply -0.3 1.98 V
VDDS_OSC0 MCU_OSC0 and WKUP_LFOSC0 supply -0.3 1.98 V
VDDA_MCU RCOSC, POR, POK, and MCU PLL analog supply -0.3 1.98 V
VDDA_PLL0 SMS PLL analog supply -0.3 1.98 V
VDDA_PLL1 MAIN PLL, PER0 PLL, and PER1 PLL analog supply -0.3 1.98 V
VDDA_PLL2 DDR PLL and ARM0 PLL analog supply -0.3 1.98 V
VDDA_PLL3 VIDEO PLL and GPU PLL analog supply -0.3 1.98 V
VDDA_PLL4 DSS PLL0, DSS PLL1, and DSS PLL2 analog supply -0.3 1.98 V
VDDA_PLL5 C7x PLL analog supply -0.3 1.98 V
VDDA_1P8_CSI_DSI CSIRX0 and DSITX0 1.8 V analog supply -0.3 1.98 V
VDDA_1P8_OLDI0 OLDI0 1.8 V analog supply -0.3 1.98 V
VDDA_1P8_USB0
USB0 and USB1 1.8 V analog supply -0.3 1.98 V
VDDA_1P8_USB1
VDDA_TEMP0 TEMP0 analog supply -0.3 1.98 V
VDDA_TEMP1 TEMP1 analog supply -0.3 1.98 V
VDDA_TEMP2 TEMP2 analog supply -0.3 1.98 V
VPP eFuse ROM programming supply -0.3 1.98 V
VDDSHV_MCU IO supply for IO group MCU -0.3 3.63 V
VDDSHV_CANUART IO supply for IO group CANUART -0.3 3.63 V
VDDSHV0 IO supply for IO group 0 -0.3 3.63 V
VDDSHV1 IO supply for IO group 1 -0.3 3.63 V
VDDSHV2 IO supply for IO group 2 -0.3 3.63 V
VDDSHV3 IO supply for IO group 3 -0.3 3.63 V
VDDSHV5 IO supply for IO group 5 -0.3 3.63 V
VDDSHV6 IO supply for IO group 6 -0.3 3.63 V

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over operating junction temperature range (unless otherwise noted)(1) (2)

PARAMETER MIN MAX UNIT
VDDA_3P3_USB0
USB0 and USB1 3.3 V analog supply -0.3 3.63 V
VDDA_3P3_USB1
MCU_PORz -0.3 3.63 V
MCU_I2C0_SCL, MCU_I2C0_SDA,
WKUP_I2C0_SCL, WKUP_I2C0_SDA,
-0.3 1.98(3) V
EXTINTn
When operating at 1.8V
MCU_I2C0_SCL, MCU_I2C0_SDA,
Steady-state max voltage at all fail-safe IO pins WKUP_I2C0_SCL, WKUP_I2C0_SDA,
-0.3 3.63(3)
EXTINTn
When operating at 3.3V
VMON_1P8_SOC -0.3 1.98 V
VMON_3P3_SOC -0.3 3.63 V
VMON_VSYS(4) -0.3 1.98 V
USB0_VBUS, USB1_VBUS(6) -0.3 3.6 V
Steady-state max voltage at all other IO pins(5) IO supply
All other IO pins -0.3 V
voltage + 0.3
20% of IO supply voltage for up to 20%
Transient overshoot and undershoot at IO pin 0.2 × VDD(7) V
of the signal period (see Figure 6-1)
I-Test -100 100 mA
Latch-up performance(8)
Over-Voltage (OV) Test 1.5 x VDD(7) V
TSTG Storage temperature -55 +150 °C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) The absolute maximum ratings for these fail-safe pins depends on their IO supply operating voltage. Therefore, this value is also
defined by the maximum VIH value found in the I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics section, where
the electrical characteristics table has separate parameter values for 1.8-V mode and 3.3-V mode.
(4) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see System Power Supply Monitor
Design Guidelines.
(5) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For
example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be
–0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used
to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range,
including power supply ramp-up and ramp-down sequences.
(6) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see the USB VBUS Design
Guidelines.
(7) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(8) For current pulse injection (I-Test):
• Pins stressed per JEDEC JESD78 (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times
maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.

For over-voltage performance (Over-Voltage (OV) Test):

• Supplies stressed per JEDEC JESD78 (Class II) and passed specified voltage injection.

Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply
voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO
power supplies are turned off. The MCU_I2C0_SCL, MCU_I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA,
EXTINTn, VMON_1P8_SOC, VMON_3P3_SOC, and MCU_PORz are the only fail-safe IO terminals. All other IO
terminals are not fail-safe and the voltage applied to them should be limited to the value defined by the Steady
State Max. Voltage at all IO pins parameter in Section 6.1.

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Overshoot = 20% of nominal

IO supply voltage
Tovershoot

Tperiod

Tundershoot

Undershoot = 20% of nominal

IO supply voltage

A. Tovershoot + Tundershoot < 20% of Tperiod

Figure 6-1. IO Transient Voltage Ranges

6.2 ESD Ratings for Devices which are not AEC - Q100 Qualified
VALUE UNIT

Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000

V(ESD) V
(ESD) Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) ±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Power-On Hours (POH)
POWER ON HOURS (POH)(1) (2) (3)
JUNCTION TEMPERATURE RANGE (TJ)(4) LIFETIME (POH)
–40°C to 105°C 100000
–40°C to 125°C 20000(5)

(1) This information is provided solely for your convenience and does not extend or modify the
warranty provided under TI's standard terms and conditions for TI semiconductor products.
(2) Unless specified in the table above, all voltage domains and operating conditions are supported in
the device at the noted temperatures.
(3) POH is a function of voltage, temperature and time. Usage at higher voltages and temperatures will
result in a reduction in POH.
(4) Either –40 to 105C or –40 to 125C profile should be chosen and applied through the lifetime of
the application. Mixing of these profiles for the purposes of extending temperature and/or POH may
result in increased reliability failure risk and is not recommended.
(5) The –40 to 125C profile is defined as 20000 power on hours with a junction temperature as follows:
5%@–40°C, 65%@70°C, 20%@110°C, and 10%@125°C.

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6.4 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
SUPPLY NAME DESCRIPTION MIN(1) NOM MAX(1) UNIT
VDD_CORE(2) 0.75-V operation 0.715 0.75 0.79 V
VDDA_CORE_CSI_DSI(2) Core supply
VDDA_CORE_CSI_DSI_C CSIRX0 and DSITX0 core supply
LK(2) DSITX0 clock core supply
VDDA_CORE_USB0(2) USB0 and USB1 core supply 0.85-V operation 0.81 0.85 0.895 V
VDDA_CORE_USB1(2) DDR deskew PLL supply
VDDA_DDR_PLL0(2)
0.75-V operation 0.715 0.75 0.79 V
VDD_CANUART(3) CANUART core supply
0.85-V operation 0.81 0.85 0.895 V
VDDR_CORE RAM core supply 0.81 0.85 0.895 V
VDD_MMC0(4)
MMC0 PHY core supply
VDDA_0P85_DLL_MMC0 0.81 0.85 0.895 V
(4) MMC0 DLL analog supply

VDDA_0P85_SERDES SERDES PHY core supply

0.81 0.85 0.895 V
VDDA_0P85_SERDES_C SERDES analog supply
VDDS_DDR(5) DDR PHY IO supply
1.1-V operation 1.06 1.1 1.17 V
VDDS_DDR_C(5) DDR clock IO supply
VDDA_1P8_SERDES SERDES analog supply 1.71 1.8 1.89 V
VDDS_MMC0 MMC0 PHY IO supply 1.71 1.8 1.89 V
VDDS_OSC0 MCU_OSC0 and WKUP_LFOSC0 supply 1.71 1.8 1.89 V
VDDA_MCU RCOSC, POR, POK, and MCU PLL analog supply 1.71 1.8 1.89 V
VDDA_PLL0 SMS PLL analog supply 1.71 1.8 1.89 V
VDDA_PLL1 MAIN PLL, PER0 PLL, and PER1 PLL analog supply 1.71 1.8 1.89 V
VDDA_PLL2 DDR PLL and ARM0 PLL analog supply 1.71 1.8 1.89 V
VDDA_PLL3 VIDEO PLL and GPU PLL analog supply 1.71 1.8 1.89 V
VDDA_PLL4 DSS PLL0, DSS PLL1, and DSS PLL2 analog supply 1.71 1.8 1.89 V
VDDA_PLL5 C7x PLL analog supply 1.71 1.8 1.89 V
VDDA_1P8_CSI_DSI CSIRX0 and DSITX0 1.8 V analog supply 1.71 1.8 1.89 V
VDDA_1P8_OLDI0 OLDI0 1.8 V analog supply 1.71 1.8 1.89 V
VDDA_1P8_USB0
USB0 and USB1 1.8 V analog supply 1.71 1.8 1.89 V
VDDA_1P8_USB1
VDDA_TEMP0 TEMP0 analog supply 1.71 1.8 1.89 V
VDDA_TEMP1 TEMP1 analog supply 1.71 1.8 1.89 V
VDDA_TEMP2 TEMP2 analog supply 1.71 1.8 1.89 V
VPP eFuse ROM programming supply see(6) see(6) see(6) V
VMON_1P8_SOC Voltage monitor for 1.8 V SoC power supply 1.71 1.8 1.89 V
VDDA_3P3_USB0 USB0 3.3 V analog supply 3.135 3.3 3.465 V
VDDA_3P3_USB1 USB1 3.3 V analog supply
VMON_3P3_SOC Voltage monitor for 3.3 V SoC power supply 3.135 3.3 3.465 V
VMON_ER_VSYS Voltage monitor for system power supply 0 see(7) 1 V
USB0_VBUS USB0 Level-shifted VBUS Input 0 see(8) 3.465 V
USB1_VBUS USB1 Level-shifted VBUS Input 0 see(8) 3.465 V

Dual-voltage IO supply for IO group 1.8-V operation 1.71 1.8 1.89 V

VDDSHV_CANUART(9)
CANUART 3.3-V operation 3.135 3.3 3.465 V
1.8-V operation 1.71 1.8 1.89 V
VDDSHV_MCU Dual-voltage IO supply for IO group MCU
3.3-V operation 3.135 3.3 3.465 V

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over operating junction temperature range (unless otherwise noted)

SUPPLY NAME DESCRIPTION MIN(1) NOM MAX(1) UNIT
1.8-V operation 1.71 1.8 1.89 V
VDDSHV0 Dual-voltage IO supply for IO group 0
3.3-V operation 3.135 3.3 3.465 V
1.8-V operation 1.71 1.8 1.89 V
VDDSHV1 Dual-voltage IO supply for IO group 1
3.3-V operation 3.135 3.3 3.465 V
1.8-V operation 1.71 1.8 1.89 V
VDDSHV2 Dual-voltage IO supply for IO group 2
3.3-V operation 3.135 3.3 3.465 V
1.8-V operation 1.71 1.8 1.89 V
VDDSHV3 Dual-voltage IO supply for IO group 3
3.3-V operation 3.135 3.3 3.465 V
1.8-V operation 1.71 1.8 1.89 V
VDDSHV5 Dual-voltage IO supply for IO group 5
3.3-V operation 3.135 3.3 3.465 V
1.8-V operation 1.71 1.8 1.89 V
VDDSHV6 Dual-voltage IO supply for IO group 6
3.3-V operation 3.135 3.3 3.465 V
125°C Industrial and
TJ Operating junction temperature range -40 125 °C
Automotive

(1) The voltage at the device ball must never drop below the MIN voltage or rise above the MAX voltage for any amount of time during
normal device operation.
(2) VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK, VDDA_CORE_USB, and VDDA_DDR_PLL0 shall be sourced from
the same power source. Care should be taken to ensure that voltage differential between VDD_CORE and VDDA_CORE_USB is
within +/- 1%.
(3) VDD_CANUART shall be connected to an always on power source when using Partial IO or IO Only + DDR Self-refresh low power
modes. VDD_CANUART shall be connected to the same power source as VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_USB,
and VDDA_DDR_PLL0 when not using Partial IO or IO Only + DDR Self-refresh low power modes.
(4) VDD_MMC0 and VDDA_0P85_DLL_MMC0 must be connected to the same power source as VDD_CORE when MMC0 is not used. In
this case, VDD_MMC0 and VDDA_0P85_DLL_MMC0 may be operated at a nominal voltage of 0.75 or 0.85.
(5) VDDS_DDR and VDDS_DDR_C shall be sourced from the same power source.
(6) Refer to the Recommended Operating Conditions for OTP eFuse Programming table for VPP supply voltages based on eFuse usage.
(7) The VMON_VSYS pin provides a way to monitor the system power supply. For more information, see System Power Supply Monitor
Design Guidelines.
(8) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see USB VBUS Design
Guidelines.
(9) VDDSHV_CANUART shall be connected to an always on power source when using Partial IO or IO Only + DDR Self-refresh low
power modes. VDDSHV_CANUART shall be connected to any valid IO power source when not using Partial IO or IO Only + DDR
Self-refresh low power modes.

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6.5 Operating Performance Points

Table 6-1 defines the maximum operating frequency of the clocks for each device speed grade and Table 6-2
defines the only valid Operating Performance Points (OPPs) for the device subsystem and core clocks..
Table 6-1. Device Speed Grades
MAXIMUM
MAXIMUM OPERATING FREQUNCY (MHz) DATA RATE
(MT/s)(2)
Speed VDD_CORE
Grade (V)(1) DEVICE
A53SS MAIN MCU
MCU DEVICE MGR
(Cortex- C7/MMA R5FSS0 DOMAIN DOMAIN HSM GPU VPAC DMPAC VPU LPDDR4
R5F MGR R5F DOMAIN
A53x) SYSCLK SYSCLK
CLK
J 0.75 1250 912.5 720 3200 to 3733
800 500 800 400 800 400 400 600 428.5 500
K 0.85 1400 1000 800 3466 to 4000

(1) Nominal operating voltage, see Section 6.4.

(2) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
Refer to LPDDR4 Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency. It
is recommended that software uses the minimum required LPDDR4 transfer rate that satisfies the performance requirements of the
system.
Table 6-2. Device Operating Performance Points
FIXED OPERATING FREQUENCY OPTIONS (MHz)(2) MT/s(3)
DEVICE
OPP A53SS(1) C7/MMA MAIN MCU
DEVICE MGR
R5FSS0 DOMAIN MCU R5F DOMAIN HSM GPU VPAC DMPAC VPU LPDDR4
MGR R5F DOMAIN
SYSCLK SYSCLK
CLK

High From From 800 500 800 400 800 400 400 500, From
PLL BP PLL BP Speed 400, PLL BP
to Speed to Speed Grade 600 428.5 200, to Speed
Grade Grade Max or Grade
Low Max Max 400 250 400 200 400 133 133 100 Max

(1) Default operating frequency, set by software at boot. Supports Dynamic Frequency Scaling after boot.
(2) Fixed operating frequency, set by software at boot.
(3) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
Refer to LPDDR4 Board Design and Layout Guidelines for the proper PCB implementation to achieve maximum DDR frequency.

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6.6 Electrical Characteristics

Note
The interfaces or signals described in Section 6.6 correspond to the interfaces or signals available in
multiplexing mode 0 (Primary Signal Function).
All interfaces or signals multiplexed on the balls described in these tables have the same DC electrical
characteristics, unless multiplexing involves a PHY and GPIO combination, in which case different DC
electrical characteristics are specified for the different multiplexing modes (Functions).

6.6.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1.8V MODE
(1)
VIL Input Low Voltage 0.3 × VDD V
(1)
VILSS Input Low Voltage Steady State 0.3 × VDD V
(1)
VIH Input High Voltage 0.7 × VDD 1.98(2) V
(1)
VIHSS Input High Voltage Steady State 0.7 × VDD V
(1)
VHYS Input Hysteresis Voltage 0.1 × VDD mV
VI = 1.8V
IIN Input Leakage Current. or ±10 µA
VI = 0V
(1)
VOL Output Low Voltage 0.2 × VDD V
IOL (3) Low Level Output Current VOL(MAX) 10 mA
18f(4)
SRI (5) Input Slew Rate or V/s
1.8E+6
(6)
3.3V MODE
(1)
VIL Input Low Voltage 0.3 × VDD V
(1)
VILSS Input Low Voltage Steady State 0.25 × VDD V
(1)
VIH Input High Voltage 0.7 × VDD 3.63(2) V
(1)
VIHSS Input High Voltage Steady State 0.7 × VDD V
(1)
VHYS Input Hysteresis Voltage 0.05 × VDD mV
VI = 3.3V
IIN Input Leakage Current. or ±10 µA
VI = 0V
VOL Output Low Voltage 0.4 V
IOL (3) Low Level Output Current VOL(MAX) 10 mA
33f(4)
SRI (5) Input Slew Rate or 8E+7 V/s
3.3E+6

(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
(2) This value also defines the Absolute Maximum Ratings value the IO.
(3) The IOL parameter defines the minimum Low Level Output Current for which the device is able to maintain the specified VOL value.
The value defined by this parameter should be considered the maximum current available to a system implementation which needs to
maintain the specified VOL value for attached components.
(4) f = toggle frequency of the input signal in Hz.
(5) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
(6) I2C Hs-mode is not supported when operating the IO in 3.3V mode.

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6.6.2 Fail-Safe Reset (FS RESET) Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.3 ×
VIL Input Low Voltage V
VDDS_OSC0
0.3 ×
VILSS Input Low Voltage Steady State V
VDDS_OSC0
0.7 ×
VIH Input High Voltage V
VDDS_OSC0
0.7 ×
VIHSS Input High Voltage Steady State V
VDDS_OSC0
VHYS Input Hysteresis Voltage 200 mV
VI = 1.8V
IIN Input Leakage Current. or ±10 µA
VI = 0V
18f(1)
SRI (2) Input Slew Rate or V/s
1.8E+6

(1) f = toggle frequency of the input signal in Hz.

(2) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.
6.6.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.35 ×
VIL Input Low Voltage V
VDDS_OSC0
0.65 ×
VIH Input High Voltage V
VDDS_OSC0
VHYS Input Hysteresis Voltage 49 mV
VI = 1.8V
IIN Input Leakage Current. or ±10 µA
VI = 0.0V

6.6.4 Low-Frequency Oscillator (LFXOSC) Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0.30 ×
VIL Input Low Voltage V
VDDS_OSC0
0.70 ×
VIH Input High Voltage V
VDDS_OSC0
Active Mode 85 mV
VHYS Input Hysteresis Voltage
Bypass Mode 324 mV
VI = 1.8V
IIN Input Leakage Current. or ±10 µA
VI = 0.0V

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6.6.5 SDIO Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1.8V MODE
VIL Input Low Voltage 0.58 V
VILSS Input Low Voltage Steady State 0.58 V
VIH Input High Voltage 1.27 V
VIHSS Input High Voltage Steady State 1.7 V
VHYS Input Hysteresis Voltage 150 mV
VI = 1.8V
IIN Input Leakage Current. or ±10 µA
VI = 0V
RPU Pull-up Resistor 40 50 60 kΩ
RPD Pull-down Resistor 40 50 60 kΩ
VOL Output Low Voltage 0.45 V
VOH Output High Voltage VDD(1) - 0.45 V
IOL (2) Low Level Output Current VOL(MAX) 4 mA
IOH (2) High Level Output Current VOH(MIN) 4 mA
18f(3)
SRI (4) Input Slew Rate or V/s
1.8E+6
3.3V MODE
VIL Input Low Voltage 0.25 × VDD(1) V
VILSS Input Low Voltage Steady State 0.15 × VDD(1) V
0.625 ×
VIH Input High Voltage V
VDD(1)
0.625 ×
VIHSS Input High Voltage Steady State V
VDD(1)
VHYS Input Hysteresis Voltage 150 mV
VI = 3.3V
IIN Input Leakage Current. or ±10 µA
VI = 0V
RPU Pull-up Resistor 40 50 60 kΩ
RPD Pull-down Resistor 40 50 60 kΩ
0.125 ×
VOL Output Low Voltage V
VDD(1)
VOH Output High Voltage 0.75 × VDD(1) V
IOL (2) Low Level Output Current VOL(MAX) 6 mA
IOH (2) High Level Output Current VOH(MIN) 10 mA
33f(3)
SRI (4) Input Slew Rate or V/s
3.3E+6

(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
(2) The IOL and IOH parameters define the minimum Low Level Output Current and High Level Output Current for which the device is
able to maintain the specified VOL and VOH values. Values defined by these parameters should be considered the maximum current
available to a system implementation which needs to maintain the specified VOL and VOH values for attached components.
(3) f = toggle frequency of the input signal in Hz.
(4) This MIN parameter only applies to input signal functions which are not defined in their respective Timing and Switching
Characteristics sections. Select the MIN parameter which results in the largest value.

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6.6.6 LVCMOS Electrical Characteristics

over recommended operating conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
1.8V MODE
VIL Input Low Voltage 0.35 × VDD(1) V
VILSS Input Low Voltage Steady State 0.3 × VDD(1) V
VIH Input High Voltage 0.65 × VDD(1) V
VIHSS Input High Voltage Steady State 0.85 × VDD(1) V
VHYS Input Hysteresis Voltage 150 mV
VI = 1.8V
IIN Input Leakage Current. or ±10 µA
VI = 0.0V
RPU Pull-up Resistor 15 22 30 kΩ
RPD Pull-down Resistor 15 22 30 kΩ
VOL Output Low Voltage 0.45 V
VOH Output High Voltage VDD(1) - 0.45 V
IOL (2) Low Level Output Current VOL(MAX) 3 mA
IOH (2) High Level Output Current VOH(MIN) 3 mA
18f(3)
SRI (4) Input Slew Rate or V/s
1.8E+6
3.3V MODE
VIL Input Low Voltage 0.8 V
VILSS Input Low Voltage Steady State 0.6 V
VIH Input High Voltage 2.0 V
VIHSS Input High Voltage Steady State 2.0 V
VHYS Input Hysteresis Voltage 150 mV
VI = 3.3V
IIN Input Leakage Current. or ±10 µA
VI = 0.0V
RPU Pull-up Resistor 15 22 30 kΩ
RPD Pull-down Resistor 15 22 30 kΩ
VOL Output Low Voltage 0.4 V
VOH Output High Voltage 2.4 V
IOL (2) Low Level Output Current VOL(MAX) 5 mA
IOH (2) High Level Output Current VOH(MIN) 9 mA
33f(3)
SRI (4) Input Slew Rate or V/s
3.3E+6

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6.6.7 CSI-2 (D-PHY) Electrical Characteristics

Note
CSIRX0 is compliant with MIPI DPHY v1.2 dated August 1, 2014, including ECNs and Errata as
applicable.

6.6.8 USB2PHY Electrical Characteristics

Note
The USB0 and USB1 interfaces are compliant with Universal Serial Bus Revision 2.0 Specification
dated April 27, 2000 including ECNs and Errata as applicable.

6.6.9 DDR Electrical Characteristics

Note
The DDR interface is compatible with LPDDR4 devices that are JESD209-4B standard-compliant

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6.7 VPP Specifications for One-Time Programmable (OTP) eFuses

This section specifies the operating conditions required for programming the OTP eFuses .
6.7.1 Recommended Operating Conditions for OTP eFuse Programming
over operating junction temperature range (unless otherwise noted)
PARAMETER DESCRIPTION MIN NOM MAX UNIT
VDD_CORE Supply voltage range for the core domain during OTP See Recommended Operating V
operation; OPP NOM (BOOT) Conditions
VPP Supply voltage range for the eFuse ROM domain during NC(1) V
normal operation without hardware support to program
eFuse ROM
Supply voltage range for the eFuse ROM domain during 0 V
normal operation with hardware support to program eFuse
ROM
Supply voltage range for the eFuse ROM domain during 1.71 1.8 1.89 V
OTP programming(2)
I(VPP) VPP current 400 mA
SR(VPP) VPP Power-up Slew Rate 6E + 4 V/s
Tj Operating junction temperature range while programming 0 25 85 °C
eFuse ROM.

(1) NC indicates No Connect.

(2) Supply voltage range includes DC errors and peak-to-peak noise.
6.7.2 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
• The VPP power supply must be disabled when not programming OTP registers.
• The VPP power supply must be ramped up after the proper device power-up sequence (for more details, see
Section 6.9.2.2, Power Supply Sequencing).
6.7.3 Programming Sequence
Programming sequence for OTP eFuses:
• Power on the board per the power-up sequencing. No voltage should be applied on the VPP terminal during
power up and normal operation.
• Load the OTP write software required to program the eFuse (contact your local TI representative for the OTP
software package).
• Apply the voltage on the VPP terminal according to the specification in Section 6.7.1.
• Run the software that programs the OTP registers.
• After validating the content of the OTP registers, remove the voltage from the VPP terminal.
6.7.4 Impact to Your Hardware Warranty
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge that
the e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a sequence
step. Further the TI Device may fail to secure boot if the error code correction check fails for the Production
Keys or if the image is not signed and optionally encrypted with the current active Production Keys. These
types of situations will render the TI Device inoperable and TI will be unable to confirm whether the TI Devices
conformed to their specifications prior to the attempted e-Fuse. CONSEQUENTLY, TI WILL HAVE NO LIABILITY
(WARRANTY OR OTHERWISE) FOR ANY TI DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.

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6.8 Thermal Resistance Characteristics

This section provides the thermal resistance characteristics used on this device.
For reliability and operability concerns, the maximum junction temperature of the device has to be at or below
the TJ value identified in Recommended Operating Conditions.

6.8.1 Thermal Resistance Characteristics for AMW Package TBD

It is recommended to perform thermal simulations at the system level with the worst case device power consumption.
AMW PACKAGE
NO. PARAMETER DESCRIPTION AIR FLOW
°C/W(1) (3)
(m/s)(2)
T1 RΘJC Junction-to-case 0.50 N/A
T2 RΘJB Junction-to-board 2.4 N/A
T3 Junction-to-free air 12.6 0
T4 8.0 1
RΘJA
T5 Junction-to-moving air 6.9 2
T6 6.4 3
T7 0.25 0
T8 0.26 1
ΨJT Junction-to-package top
T9 0.27 2
T10 0.27 3
T11 2.3 0
T12 2.0 1
ΨJB Junction-to-board
T13 1.9 2
T14 1.9 3

(1) These values are based on a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] value, which is based on
a JEDEC defined 1S0P system) and will change based on environment as well as application. For more information, see these
EIA/JEDEC standards:
• JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-6, Integrated Circuit Thermal Test Method Environmental Conditions - Forced Convection (Moving Air)
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second.
(3) °C/W = degrees Celsius per watt.

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6.9 Timing and Switching Characteristics

Note
The Timing Requirements and Switching Characteristics values may change following the silicon
characterization result.

Note
The default SLEWRATE settings in each pad configuration register must be used to ensure timings,
unless specific instructions are given otherwise.

6.9.1 Timing Parameters and Information

The timing parameter symbols used in Section 6.9, Timing and Switching Characteristics are created in
accordance with JEDEC Standard 100. To shorten the symbols, some pin names and other related terminologies
have been abbreviated in Table 6-3:
Table 6-3. Timing Parameters Subscripts
SYMBOL PARAMETER
c Cycle time (period)
d Delay time
dis Disable time
en Enable time
h Hold time
su Setup time
START Start bit
t Transition time
v Valid time
w Pulse duration (width)
X Unknown, changing, or don't care level
F Fall time
H High
L Low
R Rise time
V Valid
IV Invalid
AE Active Edge
FE First Edge
LE Last Edge
Z High impedance

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6.9.2 Power Supply Requirements

This section describes the power supply requirements to ensure proper device operation.

Note
All power balls must be supplied with the voltages specified in the Recommended Operating
Conditions section, unless otherwise specified in Signal Descriptions and Pin Connectivity
Requirements.

6.9.2.1 Power Supply Slew Rate Requirement

To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the
maximum slew rate of supplies to be less than 18mV/µs. For instance, as shown in Figure 6-2, TI recommends
having the supply ramp slew for a 1.8V supply of more than 100µs.
Figure 6-2 describes the Power Supply Slew Rate Requirement in the device.

Supply value

t
slew rate < 18 mV/μs
slew > (supply value) / (18 mV/μs)
or
supply value × 55.6 μs/V

SPRT740_ELCH_06

Figure 6-2. Power Supply Slew and Slew Rate

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6.9.2.2 Power Supply Sequencing

This section describes power sequence requirements using power sequence diagrams and associated notes.
Each power sequence diagram demonstrates the sequential order expected for each device power rail. This
is done by assigning each device power rail to one or more waveform. A dual-voltage power rail may be
associated with more than one waveform and the associated note will describe which waveform is applicable.
Each waveform defines a transition region for the associated power rails and shows its sequential relationship
to the transition regions of other power rails. The notes associated with the power sequence diagram provides
further detail of these requirements. See the Power-up Sequence section for details on power-up requirements,
and the Power-down Sequence section for details on power-down requirements.
Two types of power supply transition regions are used to simplify the power supply sequencing diagrams. The
legends shown in Figure 6-3 and Figure 6-4 along with their descriptions are provided to clarify what each
transition regions represents.
Figure 6-3 defines a transition region with multiple power rails which may be sourced from multiple power
supplies or a single power supply. Transitions shown within the transition region represent a use case where
multiple power supplies are used to source power rails associated with this waveform, and these power
supplies are allowed to ramp at different times within the region since they do not have any specific sequence
requirement relative to each other.

Figure 6-3. Multiple Power Supply Transition Legend

Figure 6-4 defines a transition region with one or more power rails which must be sourced from a single common
power supply. No transitions are shown within the region to represent a single ramp within the transition region.

Figure 6-4. Single Common Power Supply Transition Legend

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6.9.2.2.1 Power-Up Sequencing

Table 6-4 and Figure 6-5 describes the device power-up sequencing.

Note
The power supply sequencing requirements defined in this section does not include entry or exit
from low power modes. See the Partial IO Power Sequencing section for more information on the
requirements for entering or exiting from Partial IO low power mode.

Note
All power rails must be turned off and decay below 300mV before initiating a new power-up
sequence anytime a power rail drops below the minimum value defined in Recommended
Operating Conditions. The only exception is when entering/exiting Partial IO low power mode with
VDDSHV_CANUART and VDD_CANUART sourced from an always on power source. For this use
case the VDDSHV_CANUART and VDD_CANUART power rails are allowed to remain on.

Table 6-4. Power-Up Sequencing – Supply / Signal Assignments

See: Figure 6-5
WAVEFORM SUPPLY / SIGNAL NAME
A VSYS(1), VMON_VSYS(2)
VDDSHV_CANUART(3), VDDSHV_MCU(3), VDDSHV0(3), VDDSHV1(3), VDDSHV2(3), VDDSHV3(3), VDDA_3P3_USB,
B
VMON_3P3_SOC(4)
VDDSHV_CANUART(5), VDDSHV_MCU(5), VDDSHV0(5), VDDSHV1(5), VDDSHV2(5), VDDSHV3(5), VDDS_MMC0,
C VDDA_MCU, VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSI_DSI, VDDA_1P8_OLDI0,
VDDA_1P8_USB, VDDA_TEMP0, VDDA_TEMP1, VMON_1P8_SOC(6)
D VDDSHV5(7), VDDSHV6(7)
E VDDS_DDR(8), VDDS_DDR_C(8)
F VDD_CANUART(9)
VDD_CANUART(10), VDD_CORE(10) (12), VDDA_CORE_CSI_DSI(10), VDDA_CORE_DSI_CLK(10),
G
VDDA_CORE_USB0(10), VDDA_DDR_PLL0(10)
VDD_CANUART(11), VDD_CORE(11) (12), VDDA_CORE_CSI_DSI(11), VDDA_CORE_DSI_CLK(11),
H
VDDA_CORE_USB0(11), VDDA_DDR_PLL0(11), VDDR_CORE(12), VDD_MMC0, VDDA_0P85_DLL_MMC0
I VPP(13)
J MCU_PORz
K MCU_OSC0_XI, MCU_OSC0_XO

(1) VSYS represents the name of a supply which sources power to the entire system. This supply is expected to be a pre-regulated supply
that sources power management devices which source all other supplies.
(2) VMON_VSYS input is used to monitor VSYS via an external resistor divider circuit. For more information, see the Section 8.2.4,
System Power Supply Monitor Design Guidelines.
(3) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V
depending on the application requirements.
VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any
valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power
source and is operating at 3.3V, it shall be ramped up with other 3.3V supplies during the 3.3V ramp period defined by this waveform.
When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 3.3V, they shall be ramped up with other 3.3V
supplies during the 3.3V ramp period defined by this waveform.
(4) The VMON_3P3_SOC input is used to monitor supply voltage and shall be connected to the respective 3.3V supply source.
(5) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] are dual voltage IO supplies which can be operated at 1.8V or 3.3V
depending on the application requirements.
VDDSHV_CANUART shall be connected to an always-on power source when using Partial IO low power mode, or connected to any
valid IO power source when not using Partial IO low power mode. When VDDSHV_CANUART is not connected to an always-on power
source and is operating at 1.8V, it shall be ramped up with other 1.8V supplies during the 1.8V ramp period defined by this waveform.
When any of the VDDSHV_MCU and VDDSHVx [x=0-3] IO supplies are operating at 1.8V, they shall be ramped up with other 1.8V
supplies during the 1.8V ramp period defined by this waveform.

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(6) The VMON_1P8_SOC input is used to monitor supply voltage and shall be connected to the respective 1.8V supply source.
(7) VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic voltage change without any dependency on
other power rails. This capability is required to support UHS-I SD Cards.
(8) VDDS_DDR and VDDS_DDR_C are expected to be powered by the same source such that they ramp together.
(9) VDD_CANUART shall be connected to an always-on power source when using Partial IO low power mode.
When VDD_CANUART is connected to an always-on power source, the potential applied to VDD_CORE must never be greater than
the potential applied to VDD_CANUART + 0.18V during power-up or power-down. This requires VDD_CANUART to ramp up before
and ramp down after VDD_CORE. VDD_CANUART does not have any ramp requirements beyond the one defined for VDD_CORE.
(10) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK,
VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.
VDD_CANUART, VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK, VDDA_CORE_USB, and VDDA_DDR_PLL0 can
be operated at 0.75V or 0.85V. When these supplies are operating at 0.75V, they shall be ramped up prior to VDDR_CORE as defined
by this waveform.
(11) VDD_CANUART shall be connected to the same power source as VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK,
VDDA_CORE_USB, and VDDA_DDR_PLL0 when not using Partial IO low power mode.
VDD_CANUART, VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK, VDDA_CORE_USB, and VDDA_DDR_PLL0 can
be operated at 0.75V or 0.85V. When these supplies are operating at 0.85V, they shall be powered from the same source as
VDDR_CORE and ramped during the 0.85V ramp period defined by this waveform.
(12) The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE + 0.18V during power-up or
power-down. This requires VDD_CORE to ramp up before and ramp down after VDDR_CORE when VDD_CORE is operating at
0.75V. VDD_CORE does not have any ramp requirements beyond the one defined for VDDR_CORE.
VDD_CORE and VDDR_CORE are expected to be powered by the same source so they ramp together when VDD_CORE is
operating at 0.85V.
(13) VPP is the 1.8V eFuse programming supply, which shall be left floating (HiZ) or grounded during power-up/down sequences and
during normal device operation. This supply shall only be sourced while programming eFuse.

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VSYS
Waveform A VMON_VSYS

Waveform B

Waveform C

Waveform D

Waveform E

Waveform F

Waveform G

Waveform H

Waveform I Hi-Z

Waveform J

Waveform K

AM62Ax_ELCH_01

Figure 6-5. Power-Up Sequencing

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6.9.2.2.2 Power-Down Sequencing

Table 6-5 and Figure 6-6 describes the device power-down sequencing.

Table 6-5. Power-Down Sequencing – Supply / Signal Assignments

See: Figure 6-6
WAVEFORM SUPPLY / SIGNAL NAME
A VSYS, VMON_VSYS
VDDSHV_CANUART(1), VDDSHV_MCU(1), VDDSHV0(1), VDDSHV1(1), VDDSHV2(1), VDDSHV3(1), VDDA_3P3_USB,
B
VMON_3P3_SOC
VDDSHV_CANUART(2), VDDSHV_MCU(2), VDDSHV0(2), VDDSHV1(2), VDDSHV2(2), VDDSHV3(2), VDDS_MMC0,
C VDDA_MCU, VDDS_OSC0, VDDA_PLL0, VDDA_PLL1, VDDA_PLL2, VDDA_1P8_CSI_DSI, VDDA_1P8_OLDI0,
VDDA_1P8_USB, VDDA_TEMP0, VDDA_TEMP1, VMON_1P8_SOC
D VDDSHV5(3), VDDSHV6(3)
E VDDS_DDR, VDDS_DDR_C
F VDD_CANUART(4)
VDD_CANUART(5), VDD_CORE(5), VDDA_CORE_CSI_DSI(5), , VDDA_CORE_DSI_CLK(5), VDDA_CORE_USB0(5),
G
VDDA_DDR_PLL0(5)
VDD_CANUART(6), VDD_CORE(6), VDDA_CORE_CSI_DSI(6), , VDDA_CORE_DSI_CLK(6), VDDA_CORE_USB0(6),
H
VDDA_DDR_PLL0(6), VDDR_CORE, VDD_MMC0, VDDA_0P85_DLL_MMC0
I VPP
J MCU_PORz
K MCU_OSC0_XI, MCU_OSC0_XO

(1) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] when operating at 3.3V.

(2) VDDSHV_CANUART, VDDSHV_MCU, and VDDSHVx [x=0-3] when operating at 1.8V.
(3) VDDSHV5, and VDDSHV6 were designed to support power-up, power-down, or dynamic voltage change without any dependency on
other power rails. This capability is required to support UHS-I SD Cards.
(4) VDD_CANUART when connected to an always-on power source for Partial IO low power mode.
(5) VDD_CANUART, VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK, VDDA_CORE_USB0, and VDDA_DDR_PLL0
when operating at 0.75V
(6) VDD_CANUART, VDD_CORE, VDDA_CORE_CSI_DSI, VDDA_CORE_DSI_CLK, VDDA_CORE_USB0, and VDDA_DDR_PLL0
when operating at 0.85V

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VSYS
Horizontal dashed lines represent a use case where the system power remains turned “on”
Waveform A VMON_VSYS while the device power management solution is turned “off”.

Waveform B

Waveform C

Waveform D

Waveform E

Waveform F

Waveform G

Waveform H

Waveform I Hi-Z

Waveform J

Waveform K

AM62Ax_ELCH_02

Figure 6-6. Power-Down Sequencing

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6.9.2.2.3 Partial IO Power Sequencing

This section describes power supply sequence requirements when entering or exiting low power modes.
For more information on low power modes supported by this device and the names assigned to each low power
mode, see the Power Modes section in the Device Configuration chapter of the Technical Reference Manual.
Partial IO is the only low power mode that requires power supply changes to the device power rails. All power
supply rails except VDD_CANUART and VDDSHV_CANUART are turned off when operating in Partial IO mode.
The power sequence required to enter Partial IO is the same sequence defined in Section 6.9.2.2.2, Power-
Down Sequencing with the exception of VDD_CANUART and VDDSHV_CANUART, which remain powered.
The power sequence required to exit Partial IO is the same sequence defined in Section 6.9.2.2.1, Power-Up
Sequencing with the exception of VDD_CANUART and VDDSHV_CANUART, which are already powered.

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6.9.3 System Timing

For more details about features and additional description information on the subsystem multiplexing signals,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
6.9.3.1 Reset Timing
Tables and figures provided in this section define timing conditions, timing requirements, and switching
characteristics for reset related signals.
Table 6-6. Reset Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
VDD(1) = 1.8V 0.0018 V/ns
SRI Input slew rate
VDD(1) = 3.3V 0.0033 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 30 pF

(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
Table 6-7. MCU_PORz Timing Requirements
see Figure 6-7
NO. PARAMETER MIN MAX UNIT
Hold time, MCU_PORz active (low) at Power-up
RST1 9500000 ns
after supplies valid (using external crystal circuit)
th(SUPPLIES_VALID - MCU_PORz) Hold time, MCU_PORz active (low) at Power-up
RST2 after supplies valid and external clock stable (using 1200 ns
external LVCMOS clock source)
Pulse Width, MCU_PORz low after Power-up
RST3 tw(MCU_PORzL) (without removal of Power or system reference 1200 ns
clock MCU_OSC0_XI/XO)

Figure 6-7. MCU_PORz Timing Requirements

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Table 6-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics

see Figure 6-8
NO. PARAMETER MIN MAX UNIT
Delay time, MCU_PORz active (low) to
RST4 td(MCU_PORzL-MCU_RESETSTATzL) 0 ns
MCU_RESETSTATz active (low)
Delay time, MCU_PORz inactive (high) to
RST5 td(MCU_PORzH-MCU_RESETSTATzH) 6120*S(1) ns
MCU_RESETSTATz inactive (high)
Delay time, MCU_PORz active (low) to
RST6 td(MCU_PORzL-RESETSTATzL) 0 ns
RESETSTATz active (low)
Delay time, MCU_PORz inactive (high) to
RST7 td(MCU_PORzH-RESETSTATzH) 9195*S(1) ns
RESETSTATz inactive (high)
Pulse Width, MCU_RESETSTATz low
RST8 tw(MCU_RESETSTATzL) 966*S(1) ns
(SW_MCU_WARMRST)
Pulse Width, RESETSTATz low
RST9 tw(RESETSTATzL) (SW_MCU_WARMRST, SW_MAIN_PORz, or 4040*S ns
SW_MAIN_WARMRST)

(1) S = MCU_OSC0_XI/XO clock period in ns.

Figure 6-8. MCU_RESETSTATz, and RESETSTATz Switching Characteristics

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Table 6-9. MCU_RESETz Timing Requirements

see Figure 6-9
NO. PARAMETER MIN MAX UNIT
RST10 tw(MCU_RESETzL) (1) Pulse Width, MCU_RESETz active (low) 1200 ns

(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 6-10. MCU_RESETSTATz, and RESETSTATz Switching Characteristics
see Figure 6-9
NO. PARAMETER MIN MAX UNIT
Delay time, MCU_RESETz active (low) to
RST11 td(MCU_RESETzL-MCU_RESETSTATzL) 0 ns
MCU_RESETSTATz active (low)
Delay time, MCU_RESETz inactive (high) to
RST12 td(MCU_RESETzH-MCU_RESETSTATzH) 966*S(1) ns
MCU_RESETSTATz inactive (high)
RST13 td(MCU_RESETzL-RESETSTATzL) Delay time, MCU_RESETz active (low) to
960 ns
RESETSTATz active (low)
RST14 td(MCU_RESETzH-RESETSTATzH) Delay time, MCU_RESETz inactive (high) to
4040*S(1) ns
RESETSTATz inactive (high)

(1) S = MCU_OSC0_XI/XO clock period in ns.

Figure 6-9. MCU_RESETz, MCU_RESETSTATz, and RESETSTATz Timing Requirements and Switching
Characteristics

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Table 6-11. RESET_REQz Timing Requirements

see Figure 6-10
NO. PARAMETER MIN MAX UNIT
RST15 tw(RESET_REQzL) (1) Pulse Width, RESET_REQz active (low) 1200 ns

(1) This timing parameter is valid only after all supplies are valid and MCU_PORz has been asserted for the specified time.
Table 6-12. RESETSTATz Switching Characteristics
see Figure 6-10
NO. PARAMETER MIN MAX UNIT
Delay time, RESET_REQz active (low) to
RST16 td(RESET_REQzL-RESETSTATzL) 900*T(1) ns
RESETSTATz active (low)
Delay time, RESET_REQz inactive (high) to
RST17 td(RESET_REQzH-RESETSTATzH) 4040*S(2) ns
RESETSTATz inactive (high)

(1) T = Reset Isolation Time (Software Dependent)

(2) S = MCU_OSC0_XI/XO clock period in ns.

Figure 6-10. RESET_REQz and RESETSTATz Timing Requirements and Switching Characteristics

Table 6-13. EMUx Timing Requirements

see Figure 6-11
NO. PARAMETER MIN MAX UNIT
Setup time, EMU[1:0] before MCU_PORz inactive
RST18 tsu(EMUx-MCU_PORz) 3*S(1) ns
(high)
Hold time, EMU[1:0] after MCU_PORz inactive
RST19 th(MCU_PORz - EMUx) 10 ns
(high)

(1) S = MCU_OSC0_XI/XO clock period in ns.

Figure 6-11. EMUx Timing Requirements

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Table 6-14. BOOTMODE Timing Requirements

see Figure 6-12
NO. PARAMETER MIN MAX UNIT
Setup time, BOOTMODE[15:00] valid before
RST23 tsu(BOOTMODE-PORz_OUT) PORz_OUT high (External MCU PORz event or 3*S(1) ns
Software SW_MAIN_PORz)
Hold time, BOOTMODE[15:00] valid after
RST24 th(PORz_OUT - BOOTMODE) PORz_OUT high (External MCU PORz event, or 0 ns
Software SW_MAIN_PORz)

(1) S = MCU_OSC0_XI/XO clock period in ns.

Table 6-15. PORz_OUT Switching Characteristics
see Figure 6-12
NO. PARAMETER MIN MAX UNIT
Delay time, MCU_PORz active (low) to
RST25 td(MCU_PORzL-PORz_OUT) 0 ns
PORz_OUT active (low)
Delay time, MCU_PORz inactive (high) to
RST26 td(MCU_PORzH-PORz_OUT) 1840 ns
PORz_OUT inactive (high)
Pulse Width, PORz_OUT low (MCU_PORz or
RST27 tw(PORz_OUTL) 1200 ns
SW_MAIN_PORz)

Figure 6-12. BOOTMODE Timing Requirements and PORz_OUT Switching Characteristics

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6.9.3.2 Error Signal Timing

Tables and figures provided in this section define timing conditions and switching characteristics for
MCU_ERRORn.
Table 6-16. Error Signal Timing Conditions
PARAMETER MIN MAX UNIT
OUTPUT CONDITIONS
CL Output load capacitance 30 pF

Table 6-17. MCU_ERRORn Switching Characteristics

see Figure 6-13
NO. PARAMETER MIN MAX UNIT
Cycle time minimum, MCU_ERRORn (PWM
ERR1 tc(MCU_ERRORn) (P*H)+(P*L)(1) (3) (4) ns
mode enabled)
Pulse width minimum, MCU_ERRORn active
ERR2 tw(MCU_ERRORn) P*R(1) (2) ns
(PWM mode disabled)(5)
td (ERROR_CONDITION- Delay time, ERROR CONDITION to
ERR3 50*P(1) ns
MCU_ERRORnL) MCU_ERRORn active(5)

(1) P = ESM functional clock period in ns.

(2) R = Error Pin Counter Pre-Load Register count value.
(3) H = Error Pin PWM High Pre-Load Register count value.
(4) L = Error Pin PWM Low Pre-Load Register count value.
(5) When PWM mode is enabled, MCU_ERRORn stops toggling after ERR3 and will maintain its value (either high or low) until the error is
cleared. When PWM mode is disabled, MCU_ERRORn is active low.
Internal Error Condition
(Active High)

ERR1

MCU_ERRORn
(PWM Mode Enabled)

ERR2
ERR3
MCU_ERRORn
(PWM Mode Disabled)

Figure 6-13. MCU_ERRORn Timing Requirements and Switching Characteristics

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6.9.3.3 Clock Timing

Tables and figures provided in this section define timing conditions, timing requirements, and switching
characteristics for clock signals.
Table 6-18. Clock Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.5 V/ns
OUTPUT CONDITIONS
5ns ≤ tc < 8ns 5 pF
CL Output load capacitance 8ns ≤ tc < 20ns 10 pF
20ns ≤ tc 30 pF

Table 6-19. Clock Timing Requirements

see Figure 6-14
NO. MIN MAX UNIT
CLK1 tc(EXT_REFCLK1) Cycle time minimum, EXT_REFCLK1 10 ns
CLK2 tw(EXT_REFCLK1H) Pulse Duration, EXT_REFCLK1 high E*0.45(1) E*0.55(1) ns
CLK3 tw(EXT_REFCLK1L) Pulse Duration, EXT_REFCLK1 low E*0.45(1) E*0.55(1) ns
CLK1 tc(MCU_EXT_REFCLK0) Cycle time minimum, MCU_EXT_REFCLK0 10 ns
CLK2 tw(MCU_EXT_REFCLK0H) Pulse Duration, MCU_EXT_REFCLK0 high F*0.45(2) F*0.55(2) ns
CLK3 tw(MCU_EXT_REFCLK0L) Pulse Duration, MCU_EXT_REFCLK0 low F*0.45(2) F*0.55(2) ns
CLK1 tc(AUDIO_EXT_REFCLK0) Cycle time minimum, AUDIO_EXT_REFCLK0 20 ns
CLK2 tw(AUDIO_EXT_REFCLK0H) Pulse Duration, AUDIO_EXT_REFCLK0 high G*0.45(3) G*0.55(3) ns
CLK3 tw(AUDIO_EXT_REFCLK0L) Pulse Duration, AUDIO_EXT_REFCLK0 low G*0.45(3) G*0.55(3) ns
CLK1 tc(AUDIO_EXT_REFCLK1) Cycle time minimum, AUDIO_EXT_REFCLK1 20 ns
CLK2 tw(AUDIO_EXT_REFCLK1H) Pulse Duration, AUDIO_EXT_REFCLK1 high H*0.45(4) H*0.55(4) ns
CLK3 tw(AUDIO_EXT_REFCLK1L) Pulse Duration, AUDIO_EXT_REFCLK1 low H*0.45(4) H*0.55(4) ns

(1) E = EXT_REFCLK1 cycle time in ns.

(2) F = MCU_EXT_REFCLK0 cycle time in ns.
(3) G = AUDIO_EXT_REFCLK0 cycle time in ns.
(4) H = AUDIO_EXT_REFCLK1 cycle time in ns.
CLK1
CLK2 CLK3

Input Clock

Figure 6-14. Clock Timing Requirements

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Table 6-20. Clock Switching Characteristics

see Figure 6-15
NO. PARAMETER MIN MAX UNIT
CLK4 tc(SYSCLKOUT0) Cycle time minimum,SYSCLKOUT0 8 ns
CLK5 tw(SYSCLKOUT0H) Pulse Duration, SYSCLKOUT0 high A*0.4(1) A*0.6(1) ns
CLK6 tw(SYSCLKOUT0L) Pulse Duration, SYSCLKOUT0 low A*0.4(1) A*0.6(1) ns
CLK4 tc(OBSCLK0) Cycle time minimum, OBSCLK0 5 ns
CLK5 tw(OBSCLK0H) Pulse Duration, OBSCLK0 high B*0.45(2) B*0.55(2) ns
CLK6 tw(OBSCLK0L) Pulse Duration, OBSCLK0 low B*0.45(2) B*0.55(2) ns
CLK4 tc(OBSCLK1) Cycle time minimum, OBSCLK1 5 ns
CLK5 tw(OBSCLK1H) Pulse Duration, OBSCLK1 high F*0.45(3) F*0.55(3) ns
CLK6 tw(OBSCLK1L) Pulse Duration, OBSCLK1 low F*0.45(3) F*0.55(3) ns
CLK4 tc(CLKOUT0) Cycle time minimum, CLKOUT0 20 ns
CLK5 tw(CLKOUT0H) Pulse Duration, CLKOUT0 high C*0.4(4) C*0.6(4) ns
CLK6 tw(CLKOUT0L) Pulse Duration, CLKOUT0 low C*0.4(4) C*0.6(4) ns
CLK4 tc(MCU_SYSCLKOUT0) Cycle time minimum, MCU_SYSCLKOUT0 10 ns
CLK5 tw(MCU_SYSCLKOUT0H) Pulse Duration, MCU_SYSCLKOUT0 high E*0.4(5) E*0.6(5) ns
CLK6 tw(MCU_SYSCLKOUT0L) Pulse Duration, MCU_SYSCLKOUT0 low E*0.4(5) E*0.6(5) ns
CLK4 tc(MCU_OBSCLK0) Cycle time minimum, MCU_OBSCLK0 5 ns
CLK5 tw(MCU_OBSCLK0H) Pulse Duration, MCU_OBSCLK0 high D*0.45(6) D*0.55(6) ns
CLK6 tw(MCU_OBSCLK0L) Pulse Duration, MCU_OBSCLK0 low D*0.45(6) D*0.55(6) ns
CLK4 tc(WKUP_CLKOUT0) Cycle time minimum, WKUP_CLKOUT0 5 ns
CLK5 tw(WKUP_CLKOUT0H) Pulse Duration, WKUP_CLKOUT0 high W*0.4(7) W*0.6(7) ns
CLK6 tw(WKUP_CLKOUT0L) Pulse Duration, WKUP_CLKOUT0 low W*0.4(7) W*0.6(7) ns
Cycle time minimum, AUDIO_EXT_REFCLK0
20 ns
(McASP Clock Source)
CLK4 tc(AUDIO_EXT_REFCLK0 )
Cycle time minimum, AUDIO_EXT_REFCLK0
10 ns
(PLL Clock Source)
CLK5 tw(AUDIO_EXT_REFCLK0 H) Pulse Duration, AUDIO_EXT_REFCLK0 high G*0.4(8) G*0.6(8) ns
CLK6 tw(AUDIO_EXT_REFCLK0 L) Pulse Duration, AUDIO_EXT_REFCLK0 low G*0.4(8) G*0.6(8) ns
Cycle time minimum, AUDIO_EXT_REFCLK1
20 ns
(McASP Clock Source)
CLK4 tc(AUDIO_EXT_REFCLK1 )
Cycle time minimum, AUDIO_EXT_REFCLK1
10 ns
(PLL Clock Source)
CLK5 tw(AUDIO_EXT_REFCLK1 H) Pulse Duration, AUDIO_EXT_REFCLK1 high J*0.4(9) J*0.6(9) ns
CLK6 tw(AUDIO_EXT_REFCLK1 L) Pulse Duration, AUDIO_EXT_REFCLK1 low J*0.4(9) J*0.6(9) ns

(1) A = SYSCLKOUT0 cycle time in ns.

(2) B = OBSCLK0 cycle time in ns.
(3) F = OBSCLK1 cycle time in ns.
(4) C = CLKOUT0 cycle time in ns.
(5) E = MCU_SYSCLKOUT0 cycle time in ns.
(6) D = MCU_OBSCLK0 cycle time in ns.
(7) W = WKUP_CLKOUT0 cycle time in ns.
(8) G = AUDIO_EXT_REFCLK0 cycle time in ns.
(9) J = AUDIO_EXT_REFCLK1 cycle time in ns.
CLK4
CLK5 CLK6

Output Clock

Figure 6-15. Clock Switching Characteristics

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6.9.4 Clock Specifications

6.9.4.1 Input Clocks / Oscillators
Various external clock inputs/outputs are needed to drive the device. Summary of these input clock signals is as
follows:
• MCU_OSC0_XO/MCU_OSC0_XI — external main crystal interface pins connected to the internal high-
frequency oscillator (MCU_HFOSC0), which is the default clock source for internal reference clock
HFOSC0_CLKOUT.
• WKUP_LFOSC0_XO/WKUP_LFOSC0_XI — external crystal interface pins connected to internal low-
frequency oscillator (WKUP_LFOSC0), which sources optional 32768Hz reference clock.
• General purpose clock inputs
– MCU_EXT_REFCLK0 — optional external system clock.
– EXT_REFCLK1 — optional external system clock.
• External CPTS reference clock input
– CP_GEMAC_CPTS0_RFT_CLK — optional reference clock input for CPTS_RFT_CLK.
• External audio reference clock inputs/outputs
– AUDIO_EXT_REFCLK[1:0] — optional McASP high-frequency input clocks when configured to operate as
an input.
For more information about Input clock interfaces, see Clocking section in Device Configuration chapter in the
device TRM.

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6.9.4.1.1 MCU_OSC0 Internal Oscillator Clock Source

Figure 6-16 shows the recommended crystal circuit. All discrete components used to implement the oscillator
circuit must be placed as close as possible to the MCU_OSC0_XI and MCU_OSC0_XO pins.

Device

MCU_OSC0_XI MCU_OSC0_XO

Crystal

CL1 CL2

PCB Ground
AM65x_MCU_OSC_INT_01

Figure 6-16. MCU_OSC0 Crystal Implementation

The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-21 summarizes the
required electrical constraints.
Table 6-21. MCU_OSC0 Crystal Circuit Requirements
PARAMETER MIN TYP MAX UNIT
Fxtal Crystal Parallel Resonance Frequency 25 MHz
Fxtal Crystal Frequency Stability and Tolerance Ethernet RGMII and RMII ±100 ppm
not used
Ethernet RGMII and RMII ±50
using derived clock
CL1+PCBXI Capacitance of CL1 + CPCBXI 12 24 pF
CL2+PCBXO Capacitance of CL2 + CPCBXO 12 24 pF
CL Crystal Load Capacitance 6 12 pF
Cshunt Crystal Circuit Shunt Capacitance ESRxtal = 30Ω 25MHz 7 pF
ESRxtal = 40Ω 25MHz 5 pF
ESRxtal = 50Ω 25MHz 5 pF
ESRxtal Crystal Effective Series Resistance (1) Ω

(1) The maximum ESR of the crystal is a function of the crystal frequency and shunt capacitance. See the Cshunt parameter.

When selecting a crystal, the system design must consider temperature and aging characteristics of the crystal
based on worst case environment and expected life expectancy of the system.
Table 6-22 details the switching characteristics of the oscillator.
Table 6-22. MCU_OSC0 Switching Characteristics - Crystal Mode
PARAMETER MIN TYP MAX UNIT
CXI XI Capacitance 2.04 pF
CXO XO Capacitance 1.91 pF
CXIXO XI to XO Mutual Capacitance 0.01 pF

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Table 6-22. MCU_OSC0 Switching Characteristics - Crystal Mode (continued)

PARAMETER MIN TYP MAX UNIT
ts Start-up Time 4 ms

VDD_CORE (min.)
VDD_CORE
VSS
Voltage

VDDS_OSC0 (min.) VDDS_OSC0

VSS MCU_OSC0_XO

tsX

Time

AM65x_MCU_OSC_STARTUP_02

Figure 6-17. MCU_OSC0 Start-up Time

6.9.4.1.1.1 Load Capacitance

The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined
by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors
CL1, CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to
MCU_OSC0_XI and MCU_OSC0_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the
PCB designer should be able to extract parasitic capacitance for each signal trace. The MCU_OSC0 circuits
and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic
capacitance values are defined in Table 6-22.

Device
Crystal Circuit PCB
Components Signal Traces
MCU_OSC0_XI

CL1 CPCBXI CXI

CL2 CPCBXO CXO

MCU_OSC0_XO

AM65x_MCU_OSC_CC_05

Figure 6-18. Load Capacitance

Load capacitors, CL1 and CL2 in Figure 6-16, should be chosen such that the below equation is satisfied. CL in
the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]

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To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the
combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to
determine the value of CL2. For example, if CL = 10pF, CPCBXI = 2.9pF, CXI = 0.5pF,CPCBXO = 3.7pF, CXO = 0.5pF,
the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10pF) - 2.9pF - 0.5pF)] = 16.6pF and CL2 = [(2CL) - (CPCBXO +
CXO)] = [(2 × 10pF) - 3.7pF - 0.5pF)] = 15.8pF
6.9.4.1.1.2 Shunt Capacitance
The crystal circuit must also be designed such that it does not exceed the maximum shunt capacitance for
MCU_OSC0 operating conditions defined in Table 6-21. Shunt capacitance, Cshunt, of the crystal circuit is a
combination of crystal shunt capacitance and parasitic contributions. PCB signal traces which connect crystal
circuit components to MCU_OSC0 have mutual parasitic capacitance to each other, CPCBXIXO, where the PCB
designer should be able to extract mutual parasitic capacitance between these signal traces. The device
package also has mutual parasitic capacitance, CXIXO, where this mutual parasitic capacitance value is defined
in Table 6-22.
PCB routing should be designed to minimize mutual capacitance between XI and XO signal traces. This is
typically done by keeping signal traces short and not routing them in close proximity. Mutual capacitance can
also be minimized by placing a ground trace between these signals when the layout requires them to be routed
in close proximity. It is important to minimize the mutual capacitance on the PCB to provide as much margin as
possible when selecting a crystal.

Device
Crystal Circuit PCB
Components Signal Traces
MCU_OSC0_XI

CPCBXIXO CXIXO
CO

MCU_OSC0_XO

AM65x_MCU_OSC_SC_06

Figure 6-19. Shunt Capacitance

A crystal should be chosen such that the below equation is satisfied. CO in the equation is the maximum shunt
capacitance specified by the crystal manufacturer.
Cshunt ≥ CO + CPCBXIXO + CXIXO
For example, the equation would be satisfied when the crystal being used is 25MHz with an ESR = 30Ω,
CPCBXIXO = 0.04pF, CXIXO = 0.01pF, and shunt capacitance of the crystal is less than or equal to 6.95pF.

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6.9.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source

Figure 6-20 shows the recommended oscillator connections when MCU_OSC0_XI is connected to a 1.8V
LVCMOS square-wave digital clock source.

Note
1. A DC steady-state condition is not allowed on MCU_OSC0_XI when the oscillator is powered up.
This is not allowed because MCU_OSC0_XI is internally AC coupled to a comparator that can
enter an unknown state when DC is applied to the input. Therefore, application software must
power down MCU_OSC0 any time MCU_OSC0_XI is not toggling between logic states.

2. The LVCMOS clock signal sourcing the MCU_OSC0_XI input must have monotonic transitions.
The clock source should be connected to MCU_OSC0_XI with a point-to-point connection,
via a series termination resistor placed near the clock source. The series termination resistor
value should match the clock source output impedance to the transmission line impedance. For
example, the series termination resistor value needs to be 20 ohms if the clock source has an
output impedance of 30 ohms and the PCB signal trace has a characteristic impedance of 50
ohms. This allows the reflection that returns from the far end of the un-terminated transmission
line to be completely absorbed such that is does not introduce any non-monotonic events on the
signal.

3. The PCB trace length connecting the LVCMOS clock source to MCU_OSC0_XI should be
minimized. This reduces capacitive loading and decreases probability of external noise sources
coupling into the clock signal. Reduced capacitive loading improves rise/fall times of the clock
signal which reduces the probability of jitter being introduced in the system.

Device

MCU_OSC0_XI MCU_OSC0_XO

PCB Ground

AM65x_MCU_OSC_EXT_CLK_03

Figure 6-20. 1.8V LVCMOS-Compatible Clock Input

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Table 6-23. MCU_OSC0 LVCMOS Digital Clock Source Requirements

PARAMETER MIN TYP MAX UNIT
Frequency 25 MHz
Ethernet RGMII and RMII
±100
Fxtal not used
Frequency Stability and Tolerance ppm
Ethernet RGMII and RMII
±50
using derived clock
DC Duty Cycle 45 55 %
tR/F Rise/Fall Time (10%-90% rise, 90%-10% fall) 4(1) ns
JPeriod(RMS) Period Jitter, RMS (100k samples) 20 ps
JPeriod(PK-PK) Period Jitter, Peak to Peak (100k samples) 300 ps
JPhase(RMS) Phase Jitter, RMS (BW 100Hz to 1MHz) 10(2) ps

(1) Most LVCMOS oscillator datasheets define their maximum Output Rise/Fall times with a capacitive load much larger than the actual
load that will be applied by the combined PCB trace capacitance and MCU_OSC0_XI input capacitance. It should not be difficult to
find a LVCMOS oscillator that meets this requirement. However, the system designer must confirm the LVCMOS oscillator selected will
provide the appropriate rise/fall time to MCU_OSC0_XI input.
(2) Most LVCMOS oscillator datasheets define their max RMS Phase Jitter using a larger bandwidth integration range than required by
this device. To get a more appropriate value, it may be necessary to contact the LVCMOS oscillator manufacture and ask them to
provide a maximum RMS Phase Jitter using the same bandwidth integration range that has been defined for this parameter.

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6.9.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source

Figure 6-21 shows the recommended crystal circuit. It is recommended that preproduction printed-circuit board
(PCB) designs include the two optional resistors Rbias and Rd in case they are required for proper oscillator
operation when combined with production crystal circuit components. In most cases, Rbias is not required and
Rd is a 0-Ω resistor. These resistors may be removed from production PCB designs after evaluating oscillator
performance with production crystal circuit components installed on preproduction PCBs.

Device

WKUP_LFOSC0_XI WKUP_LFOSC0_XO

Rd
Crystal (Optional)

(Optional) Rbias

Cf1 Cf2

PCB Ground

J7ES_LF_OSC_INT_12

Figure 6-21. WKUP_LFOSC0 Crystal Implementation

Table 6-24 presents LFXOSC modes of operation.

Table 6-24. LFXOSC Modes of Operation
MODE BP_C PD_C XI XO CLK_OUT DESCRIPTION
ACTIVE 0 0 XTAL XTAL CLK_OUT Active oscillator mode providing 32kHz
PWRDN 0 1 X PD LOW Output will be pulled down to LOW. PAD to be tri-stated. Active mode
disabled
BYPASS 1 0 CLK PD CLK XI is driven by external clock source. XO is pulled down to LOW. Due to ESD
diode to supply, XI should not be driven unless oscillator supply is present.

Note
User should set CTRLMMR_WKUP_LFXOSC_TRIM[18:16] i_mult = 3b’001 for CL in the range 6pf to
9.5pf. CTRLMMR_WKUP_LFXOSC_TRIM [18:16] i_mult = 3b’010 for CL in the range 8.5pf to 12pf.
Default setting is 3b’010.

Note
The load capacitors, Cf1 and Cf2 in Figure 6-22, should be chosen such that the below equation is
satisfied. CL in the equation is the load specified by the crystal manufacturer. All discrete components
used to implement the oscillator circuit should be placed as close as possible to the associated
oscillator WKUP_LFOSC0_XI, WKUP_LFOSC0_XO, and VSS pins.

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Cf1Cf2
CL=
(Cf1+Cf2)
J7ES_CL_MATH_03

Figure 6-22. Load Capacitance Equation

The crystal must be in the fundamental mode of operation and parallel resonant. Table 6-25 summarizes the
required electrical constraints.
Table 6-25. WKUP_LFOSC0 Crystal Electrical Characteristics
NAME DESCRIPTION MIN TYP MAX UNIT
Parallel resonance crystal frequency 32768 Hz
fp
Crystal Frequency Stability and Tolerance ±100 PPM
Cf1 Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF
Cf2 Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2 12 24 pF
ESRxtal – 40 kΩ 4 pF
ESRxtal – 60 kΩ 3 pF
Cshunt Shunt capacitance
ESRxtal – 80 kΩ 2 pF
ESRxtal – 100 kΩ 1 pF
ESR Crystal effective series resistance (1) Ω

(1) The maximum ESR of the crystal is a function of the crystal frequency and shunt capacitance. See the Cshunt parameter.

When selecting a crystal, the system design must consider the temperature and aging characteristics of a based
on the worst case environment and expected life expectancy of the system.
Table 6-26 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 6-26. WKUP_LFOSC0 Switching Characteristics – Crystal Mode
NAME DESCRIPTION MIN TYP MAX UNIT
fxtal Oscillation frequency 32768 Hz
tsX Start-up time 96.5 ms

VDD_CORE (min.)
VDD_CORE
VSS
Voltage

VDDS_OSC0 (min.) VDDS_OSC0

WKUP_LFOSC0_XO
VSS
tsX

Time
LFXOSC_STARTUP_02

Figure 6-23. WKUP_LFOSC0 Start-up Time

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6.9.4.1.4 WKUP_LFOSC0 LVCMOS Digital Clock Source

Figure 6-24 shows the recommended oscillator connections when WKUP_LFOSC0_XI is connected to a 1.8V
LVCMOS square-wave digital clock source.

Device

WKUP_LFOSC0_XI WKUP_LFOSC0_XO

PCB Ground

AM62x_MCU_OSC_EXT_CLK_03

Figure 6-24. 1.8V LVCMOS-Compatible Clock Input

6.9.4.1.5 WKUP_LFOSC0 Not Used

Figure 6-25 shows the recommended oscillator connections when WKUP_LFOSC0 is not used.

Device

WKUP_LFOSC0_XI WKUP_LFOSC0_XO

NC
PCB Ground

Figure 6-25. WKUP_LFOSC0 Not Used

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6.9.4.2 Output Clocks

The device provides several system clock outputs. Summary of these output clocks are as follows:
• MCU_SYSCLKOUT0
– MCU_PLL0_HSDIV0_CLKOUT (MCU_SYSCLKOUT0) divided by 4 and sent out of the device as
MCU_SYSCLKOUT0. This clock output is provided for test and debug purposes only.
• MCU_OBSCLK0
– Observation clock output for test and debug purposes only.
• WKUP_CLKOUT0
– WKUP domain CLKOUT0 output.
• SYSCLKOUT0
– MAIN_PLL0_HSDIV0_CLKOUT (SYSCLKOUT0) divided by 4 and then sent out of the device as
SYSCLKOUT0. This clock output is provided for test and debug purposes only.
• CLKOUT0
– CLKOUT0 is the Ethernet subsystem clock (MAIN_PLL2_HSDIV1_CLKOUT) divided-by-5 or divided-
by-10. This clock output was provided as an optional source to the external PHY. When configured
to operate as the RMII Clock source (50MHz) the signal must also be routed back to the respective
RMII[x]_REF_CLK pin for proper device operation.
• OBSCLK[1:0]
– Observation clock outputs for test and debug purposes only.
• AUDIO_EXT_REFCLK[1:0]
– Option of sourcing one of six McASP high-frequency audio reference clocks,
MAIN_PLL1_HSDIV6_CLKOUT, or MAIN_PLL2_HSDIV8_CLKOUT when configured to operate as an
output.
6.9.4.3 PLLs
Power is supplied to the Phase-Locked Loop circuits (PLLs) by internal regulators that derive their power from
off-chip power-sources.
There is one PLL in the MCU domain:
• MCU PLL
There are nine PLLs in the MAIN domain:
• MAIN PLL
• PER0 PLL
• PER1 PLL
• GPU PLL
• ARM0 PLL
• DDR PLL
• SMS PLL
• DSS PLL0
• DSS PLL1
• DSS PLL2
The system designer should consider the reference clock source start-up time and the PLL lock requirements
before configuring and using any of the PLL outputs as clock sources. The device reference clock input
requirements are defined in Section 6.9.4.1, Input Clocks / Oscillators. PLL configuration details are described in
the device TRM.
For more information on PLLs, see the PLL subsection in the Clocking subsection of the Device Configuration
section in the device TRM.

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6.9.4.4 Recommended System Precautions for Clock and Control Signal Transitions
All clock and strobe signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner.
Monotonic transitions are more likely to occur with fast signal transitions. It is easy for noise to create non-
monotonic events on a signal with slow transitions. Therefore, avoid slow signal transitions on all clock and
control signals since they are more likely to generate glitches inside the device.

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6.9.5 Peripherals
6.9.5.1 ATL
The device contains ATL module that can be used for asynchronous sample rate conversion of audio. The ATL
calculates the error between two time bases, such as audio syncs, and optionally generates an averaged clock
using cycle stealing via software.

Note
For more information about ATL, see Audio Tracking Logic (ATL) section in Peripherals chapter in the
device TRM.

Table 6-27 represents ATL timing conditions.

Table 6-27. ATL Timing Conditions
PARAMETER MODE MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate External reference CLK 0.5 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance Internal reference CLK 1 10 pF

Section 6.9.5.1.1, Section 6.9.5.1.2, Section 6.9.5.1.3, and Section 6.9.5.1.4 present timing requirements and
switching characteristics for ATL.
6.9.5.1.1 ATL_PCLK Timing Requirements

NO. PARAMETER MODE MIN MAX UNIT

External reference
D1 tc(pclk) Cycle time, ATL_PCLK 5 ns
CLK
External reference
D2 tw(pclkL) Pulse Duration, ATL_PCLK low 0.45 × M(1) + 2.5 ns
CLK
External reference
D3 tw(pclkH) Pulse Duration, ATL_PCLK high 0.45 × M(1) + 2.5 ns
CLK

(1) M = ATL_CLK[x] period

6.9.5.1.2 ATL_AWS[x] Timing Requirements

NO. MODE MIN MAX UNIT

External reference
D4 tc(aws) Cycle Time, ATL_AWS[x](3) 2 × M(1) ns
CLK
External reference
D5 tw(awsL) Pulse Duration, ATL_AWS[x](3) low 0.45 × A(2) + 2.5 ns
CLK
External reference
D6 tw(awsH) Pulse Duration, ATL_AWS[x](3) high 0.45 × A(2) + 2.5 ns
CLK

(1) M = ATL_CLK[x] period

(2) A = ATL_AWS[x] period
(3) x = 0 to 3
6.9.5.1.3 ATL_BWS[x] Timing Requirements

NO. MODE MIN MAX UNIT

External reference
D7 tc(bws) Cycle Time, ATL_BWS[x](3) 2 × M(1) ns
clock
External reference
D8 tw(bwsL) Pulse Duration, ATL_BWS[x] low(3) 0.45 × B(2) + 2.5 ns
clock

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NO. MODE MIN MAX UNIT

External reference
D9 tw(bwsH) Pulse Duration, ATL_BWS[x] high(3) 0.45 × B(2) + 2.5 ns
clock

(1) M = ATL_CLK[x] period

(2) B = ATL_BWS[x] period
(3) x = 0 to 3
6.9.5.1.4 ATCLK[x] Switching Characteristics

NO. PARAMETER MODE MIN MAX UNIT

Internal reference
D10 tc(atclk) Cycle time, ATCLK[x](3) 20 ns
CLK
Internal reference
D11 tw(atclkL) Pulse Duration, ATCLK[x] low(3) 0.45 × P(2) - M(1) - 0.3 ns
CLK
Internal reference
D12 tw(atclkH) Pulse Duration, ATCLK[x] high(3) 0.45 × P(2) - M(1) - 0.3 ns
CLK

(1) M = ATL_CLK[x] period

(2) P = ATCLK[x] period
(3) x = 0 to 3
D10

D12

ATCLK[x]
D11
atl_01

Figure 6-26. ATCLK[x] Timing

6.9.5.2 CPSW3G
For more details about features and additional description information on the device Gigabit Ethernet MAC, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
6.9.5.2.1 CPSW3G MDIO Timing
Table 6-28, Table 6-29, Table 6-30, and Figure 6-27 present timing conditions, timing requirements, and
switching characteristics for CPSW3G MDIO.
Table 6-28. CPSW3G MDIO Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.9 3.6 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 10 470 pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay) Propagation delay of each trace 0 5 ns
td(Trace Mismatch Delay) Propagation delay mismatch across all traces 1 ns

Table 6-29. CPSW3G MDIO Timing Requirements

see Figure 6-27
NO. PARAMETER MIN MAX UNIT
MDIO1 tsu(MDIO_MDC) Setup time, MDIO[x]_MDIO valid before MDIO[x]_MDC high 45 ns
MDIO2 th(MDC_MDIO) Hold time, MDIO[x]_MDIO valid after MDIO[x]_MDC high 0 ns

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Table 6-30. CPSW3G MDIO Switching Characteristics

see Figure 6-27
NO. PARAMETER MIN MAX UNIT
MDIO3 tc(MDC) Cycle time, MDIO[x]_MDC 400 ns
MDIO4 tw(MDCH) Pulse Duration, MDIO[x]_MDC high 160 ns
MDIO5 tw(MDCL) Pulse Duration, MDIO[x]_MDC low 160 ns
MDIO7 td(MDC_MDIO) Delay time, MDIO[x]_MDC low to MDIO[x]_MDIO valid -10 10 ns

MDIO3
MDIO4
MDIO5
MDIO[x]_MDC

MDIO1

MDIO2

MDIO[x]_MDIO
(input)

MDIO7

MDIO[x]_MDIO
(output)
CPSW2G_MDIO_TIMING_01

Figure 6-27. CPSW3G MDIO Timing Requirements and Switching Characteristics

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6.9.5.2.2 CPSW3G RMII Timing

Table 6-31, Table 6-32, Figure 6-28, Table 6-33, Figure 6-29, Table 6-34, and Figure 6-30 present timing
conditions, timing requirements, and switching characteristics for CPSW3G RMII.
Table 6-31. CPSW3G RMII Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
VDD(1) = 1.8V 0.18 0.54 V/ns
SRI Input slew rate
VDD(1) = 3.3V 0.4 1.2 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 3 25 pF

(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.
Table 6-32. RMII[x]_REF_CLK Timing Requirements – RMII Mode
see Figure 6-28
NO. PARAMETER DESCRIPTION MIN MAX UNIT
RMII1 tc(REF_CLK) Cycle time, RMII[x]_REF_CLK 19.999 20.001 ns
RMII2 tw(REF_CLKH) Pulse Duration, RMII[x]_REF_CLK High 7 13 ns
RMII3 tw(REF_CLKL) Pulse Duration, RMII[x]_REF_CLK Low 7 13 ns

RMII1

RMII2

RMII[x]_REF_CLK

RMII3

Figure 6-28. CPSW3G RMII[x]_REF_CLK Timing Requirements – RMII Mode

Table 6-33. RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RX_ER Timing Requirements – RMII Mode
see Figure 6-29
NO. PARAMETER DESCRIPTION MIN MAX UNIT
RMII4 tsu(RXD-REF_CLK) Setup time, RMII[x]_RXD[1:0] valid before RMII[x]_REF_CLK 4 ns
tsu(CRS_DV-REF_CLK) Setup time, RMII[x]_CRS_DV valid before RMII[x]_REF_CLK 4 ns
tsu(RX_ER-REF_CLK) Setup time, RMII[x]_RX_ER valid before RMII[x]_REF_CLK 4 ns
RMII5 th(REF_CLK-RXD) Hold time RMII[x]_RXD[1:0] valid after RMII[x]_REF_CLK 2 ns
th(REF_CLK-CRS_DV) Hold time, RMII[x]_CRS_DV valid after RMII[x]_REF_CLK 2 ns
th(REF_CLK-RX_ER) Hold time, RMII[x]_RX_ER valid after RMII[x]_REF_CLK 2 ns

RMII4

RMII5

RMII[x]_REF_CLK

RMII[x]_RXD[1:0], RMII[x]_CRS_DV,
RMII[x]_RX_ER

Figure 6-29. CPSW3G RMII[x]_RXD[1:0], RMII[x]_CRS_DV, RMII[x]_RX_ER Timing Requirements – RMII

Mode

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Table 6-34. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode

see Figure 6-30
NO. PARAMETER DESCRIPTION MIN MAX UNIT
RMII6 td(REF_CLK-TXD) Delay time, RMII[x]_REF_CLK High to RMII[x]_ 2 10 ns
TXD[1:0] valid
td(REF_CLK-TX_EN) Delay time, RMII[x]_REF_CLK to RMII[x]_TX_EN 2 10 ns
valid

RMII6

RMII[x]_REF_CLK

RMII[x]_TXD[1:0], RMII[x]_TX_EN

Figure 6-30. RMII[x]_TXD[1:0], and RMII[x]_TX_EN Switching Characteristics – RMII Mode

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6.9.5.2.3 CPSW3G RGMII Timing

Table 6-35, Table 6-36, Table 6-37, Figure 6-31, Table 6-38, Table 6-39, and Figure 6-32 present timing
conditions, timing requirements, and switching characteristics for CPSW3G RGMII.
Table 6-35. CPSW3G RGMII Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
VDD(1) = 1.8V 1.44 5
SRI Input slew rate V/ns
VDD(1) = 3.3V 2.64 5
OUTPUT CONDITIONS
CL Output load capacitance 2 20 pF
PCB CONNECTIVITY REQUIREMENTS
RGMII[x]_RXC,
RGMII[x]_RD[3:0], 50 ps
td(Trace Mismatch RGMII[x]_RX_CTL
Propagation delay mismatch across all traces
Delay) RGMII[x]_TXC,
RGMII[x]_TD[3:0], 50 ps
RGMII[x]_TX_CTL

(1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball(s), see
POWER column of the Pin Attributes table.

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Table 6-36. RGMII[x]_RXC Timing Requirements – RGMII Mode

see Figure 6-31
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
RGMII1 tc(RXC) Cycle time, RGMII[x]_RXC 10Mbps 360 440 ns
100Mbps 36 44 ns
1000Mbps 7.2 8.8 ns
RGMII2 tw(RXCH) Pulse duration, RGMII[x]_RXC high 10Mbps 160 240 ns
100Mbps 16 24 ns
1000Mbps 3.6 4.4 ns
RGMII3 tw(RXCL) Pulse duration, RGMII[x]_RXC low 10Mbps 160 240 ns
100Mbps 16 24 ns
1000Mbps 3.6 4.4 ns

Table 6-37. RGMII[x]_RD[3:0], and RGMII[x]_RX_CTL Timing Requirements – RGMII Mode

see Figure 6-31
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
RGMII4 tsu(RD-RXC) Setup time, RGMII[x]_RD[3:0] valid before RGMII[x]_RXC 10Mbps 1 ns
high/low
100Mbps 1 ns
1000Mbps 1 ns
tsu(RX_CTL-RXC) Setup time, RGMII[x]_RX_CTL valid before RGMII[x]_RXC 10Mbps 1 ns
high/low
100Mbps 1 ns
1000Mbps 1 ns
RGMII5 th(RXC-RD) Hold time, RGMII[x]_RD[3:0] valid after RGMII[x]_RXC 10Mbps 1 ns
high/low
100Mbps 1 ns
1000Mbps 1 ns
th(RXC-RX_CTL) Hold time, RGMII[x]_RX_CTL valid after RGMII[x]_RXC 10Mbps 1 ns
high/low
100Mbps 1 ns
1000Mbps 1 ns

RGMII1

RGMII2
RGMII3
(A)
RGMII[x]_RXC

RGMII4

RGMII5
(B)
RGMII[x]_RD[3:0] 1st Half-byte 2nd Half-byte

(B)
RGMII[x]_RX_CTL RXDV RXERR

A. RGMII[x]_RXC must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. RGMII[x]_RD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_RXC and data bits 7-4 on the falling edge of RGMII[x]_RXC. Similarly, RGMII[x]_RX_CTL carries RXDV on rising edge of
RGMII[x]_RXC and RXERR on falling edge of RGMII[x]_RXC.

Figure 6-31. CPSW3G RGMII[x]_RXC, RGMII[x]_RD[3:0], RGMII[x]_RX_CTL Timing Requirements - RGMII

Mode

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Table 6-38. RGMII[x]_TXC Switching Characteristics – RGMII Mode

see Figure 6-32
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
RGMII6 tc(TXC) Cycle time, RGMII[x]_TXC 10Mbps 360 440 ns
100Mbps 36 44 ns
1000Mbps 7.2 8.8 ns
RGMII7 tw(TXCH) Pulse duration, RGMII[x]_TXC high 10Mbps 160 240 ns
100Mbps 16 24 ns
1000Mbps 3.6 4.4 ns
RGMII8 tw(TXCL) Pulse duration, RGMII[x]_TXC low 10Mbps 160 240 ns
100Mbps 16 24 ns
1000Mbps 3.6 4.4 ns

Table 6-39. RGMII[x]_TD[3:0] and RGMII[x]_TX_CTL Switching Characteristics – RGMII Mode

see Figure 6-32
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
RGMII9 tosu(TD-TXC) Output setup time(1), RGMII[x]_TD[3:0] valid to 10Mbps 1.2 ns
RGMII[x]_TXC high/low
100Mbps 1.2 ns
1000Mbps 1.2 ns
tosu(TX_CTL-TXC) Output setup time(1),
RGMII[x]_TX_CTL valid to 10Mbps 1.2 ns
RGMII[x]_TXC high/low
100Mbps 1.2 ns
1000Mbps 1.2 ns
RGMII10 toh(TXC-TD) Output hold time(1), RGMII[x]_TD[3:0] valid after 10Mbps 1.2 ns
RGMII[x]_TXC high/low
100Mbps 1.2 ns
1000Mbps 1.2 ns
toh(TXC-TX_CTL) Output hold time(1),
RGMII[x]_TX_CTL valid after 10Mbps 1.2 ns
RGMII[x]_TXC high/low
100Mbps 1.2 ns
1000Mbps 1.2 ns

(1) Output setup/hold times are defining a delay relationship of the transmit data and control outputs relative to the transmit clock output,
but this output relationship is being presented as the minimum setup/hold times provided to the attached receiver. This approach
matches how the output timing relationships are defined in the RGMII specification.
RGMII6

RGMII7
RGMII8
(A)
RGMII[x]_TXC

RGMII9
(B)
RGMII[x]_TD[3:0] 1st Half-byte 2nd Half-byte

RGMII10
(B)
RGMII[x]_TX_CTL TXEN TXERR

A. TXC is delayed internally before being driven to the RGMII[x]_TXC pin. This internal delay is always enabled.
B. Data and control information is received using both edges of the clocks. RGMII[x]_TD[3:0] carries data bits 3-0 on the rising edge of
RGMII[x]_TXC and data bits 7-4 on the falling edge of RGMII[x]_TXC. Similarly, RGMII[x]_TX_CTL carries TXEN on rising edge of
RGMII[x]_TXC and TXERR on falling edge of RGMII[x]_TXC.

Figure 6-32. CPSW3G RGMII[x]_TXC, RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL Switching Characteristics

- RGMII Mode

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6.9.5.3 CPTS
Table 6-40, Table 6-41, Figure 6-33, Table 6-42, and Figure 6-34 present timing conditions, timing requirements,
and switching characteristics for CPTS.
Table 6-40. CPTS Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.5 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 2 10 pF

Table 6-41. CPTS Timing Requirements

see Figure 6-33
NO. PARAMETER DESCRIPTION MIN MAX UNIT
T1 tw(HWTSPUSHH) Pulse duration, HWnTSPUSH high 12P(1) + 2 ns
T2 tw(HWTSPUSHL) Pulse duration, HWnTSPUSH low 12P(1) +2 ns
T3 tc(RFT_CLK) Cycle time, RFT_CLK 5 8 ns
T4 tw(RFT_CLKH) Pulse duration, RFT_CLK high 0.45T(2) ns
T5 tw(RFT_CLKL) Pulse duration, RFT_CLK low 0.45T(2) ns

(1) P = functional clock period in ns.

(2) T = RFT_CLK cycle time in ns.
T1 T2

HWn_TSPUSH

T3 T4 T5
RFT_CLK

Figure 6-33. CPTS Timing Requirements

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Table 6-42. CPTS Switching Characteristics

see Figure 6-34
NO. PARAMETER DESCRIPTION SOURCE MIN MAX UNIT
T6 tw(TS_COMPH) Pulse duration, TS_COMP high 36P(1) - 2 ns
T7 tw(TS_COMPL) Pulse duration, TS_COMP low 36P(1) -2 ns
T8 tw(TS_SYNCH) Pulse duration, TS_SYNC high 36P(1) - 2 ns
T9 tw(TS_SYNCL) Pulse duration, TS_SYNC low 36P(1) -2 ns
T10 tw(SYNC_OUTH) Pulse duration, SYNCn_OUT high TS_SYNC 36P(1) - 2 ns
GENF 5P(1) - 2 ns
T11 tw(SYNC_OUTL) Pulse duration, SYNCn_OUT low TS_SYNC 36P(1) -2 ns
GENF 5P(1) - 2 ns

(1) P = functional clock period in ns.

T6 T7

TS_COMP

T8 T9

TS_SYNC

T10 T11

SYNCn_OUT

Figure 6-34. CPTS Switching Characteristics

For more information, see Data Movement Architecture (DMA) chapter in the device TRM.
6.9.5.4 CSI-2

Note
For more information, see the Camera Serial Interface Receiver (CSI_RX_IF) section in the device
TRM. The CSI_RX_IF is connected to device port instances named CSIRXn, where n is the instance
number.

The CSI_RX_IF and associated D-PHY implements a CSI-2 port (CSIRX0) compliant with the MIPI D-PHY
specification v1.2 and the MIPI CSI-2 specification v1.3, with 4 differential data lanes plus 1 differential clock
lane operating in synchronous double data rate mode. For CSI-2 timing details, see the respective MIPI
specifications mentioned above.
• Support for 1-, 2-, 3- or 4-lane data transfer modes up to 1.5Gbps
6.9.5.5 CSI-2 TX
TBD

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6.9.5.6 DDRSS
For more details about features and additional description information on the device LPDDR4 Memory Interface,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 6-43 and Figure 6-35 present switching characteristics for DDRSS.
Table 6-43. DDRSS Switching Characteristics
see Figure 1-1
NO. PARAMETER DDR TYPE CORE VOLTAGE MIN MAX UNIT

tc(DDR_CKP/ 0.75-V Operation 0.536(1) 20 ns

1 Cycle time, DDR_CKP and DDR_CKN LPDDR
DDR_CKN) 0.85-V Operation .500(1) 20 ns

(1) Maximum DDR Frequency will be limited based on the specific memory type (vendor) used in a system and by PCB implementation.
TI strongly recommends all designs to follow the TI LPDDR4 EVM PCB layout exactly in every detail (routing, spacing, vias/backdrill,
PCB material, etc.) in order to achieve the full specified clock frequency. Refer to the Jacinto 7 LPDDR4 Board Design and Layout
Guidelines for details.
1

DDR0_CKP

DDR0_CKN

Figure 6-35. DDRSS Switching Characteristics

For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.

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6.9.5.7 DSS
Table 6-44, Table 6-45, Figure 6-36, Table 6-46 and Figure 6-37 present timing conditions, timing requirements,
and switching characteristics for DSS.
Table 6-44. DSS Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1.44 26.4 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 1.5 5 pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps

Table 6-45. DSS External Pixel Clock Timing Requirements

see Figure 6-36
NO. MIN MAX UNIT
D6 tc(extpclkin) Cycle time, VOUT(x)_EXTPCLKIN(2) 6.06 ns
D7 tw(extpclkinL) Pulse duration, VOUT(x)_EXTPCLKIN(2) low 0.475P(1) ns
D8 tw(extpclkinH) Pulse duration, VOUT(x)_EXTPCLKIN(2) high 0.475P(1) ns

(1) P = VOUT(x)_EXTPCLKIN cycle time in ns

(2) x in VOUT(x) = 0
D7

D6 D8
Falling-edge Clock Reference

VOUT(x)_EXTPCLKIN
Rising-edge Clock Reference

VOUT(x)_EXTPCLKIN
DPI_TIMING_02

Figure 6-36. DSS External Pixel Clock Timing Requirements

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Table 6-46. DSS Switching Characteristics

see Figure 6-37
NO. PARAMETER MODE MIN MAX UNIT
D1 tc(pclk) Cycle time, VOUT(x)_PCLK(2) 6.06 ns
Internal PLL 0.475P(1) - 0.3 ns
D2 tw(pclkL) Pulse duration, VOUT(x)_PCLK(2) low
EXTPCLKIN Y(3) - 0.45 ns
Internal PLL 0.475P(1) -0.3 ns
D3 tw(pclkH) Pulse duration, VOUT(x)_PCLK(2) high
EXTPCLKIN Z(4) - 0.45 ns

Delay time, VOUT(x)_PCLK(2) transition to Internal PLL -0.68 1.78 ns

D4 td(pclkV-dataV)
VOUT(x)_DATA[23:0](2) transition EXTPCLKIN -0.68 1.78 ns
Delay time, VOUT(x)_PCLK(2) transition to control signals Internal PLL -0.68 1.78 ns
D5 td(pclkV-ctrlL) VOUT(x)_VSYNC(2), VOUT(x)_HSYNC(2), VOUT(x)_DE(2)
falling edge EXTPCLKIN -0.68 1.78 ns

(1) P = VOUT(x)_PCLK cycle time in ns

(2) x in VOUT(x) = 0
(3) Y = tw(extpclkinL), parameter D7 from Table 6-45, DSS External Pixel Clock Timing Requirements
(4) Z = tw(extpclkinH), parameter D8 from Table 6-45, DSS External Pixel Clock Timing Requirements
D2

D1 D3
Falling-edge Clock Reference

VOUT(x)_PCLK
Rising-edge Clock Reference

VOUT(x)_PCLK

D5
VOUT(x)_VSYNC

VOUT(x)_HSYNC
D4

VOUT(x)_DATA[23:0] data_1 data_2 data_n

VOUT(x)_DE
DPI_TIMING_01

A. The assertion of data can be programmed to occur on the falling or rising edge of the pixel clock. Refer to Display Subsystem (DSS)
section in Peripherals chapter in the device TRM.
B. The polarity and pulse width of VOUT(x)_HSYNC and VOUT(x)_VSYNC are programmable, refer to Display Subsystem (DSS) section
in Peripherals chapter in the device TRM.
C. The VOUT(x)_PCLK frequency is configurable, refer to Display Subsystem section in Peripherals chapter in the device TRM.

Figure 6-37. DSS Switching Characteristics

For more information, see Display Subsystem (DSS) and Peripherals section in Peripherals chapter of the
device TRM.

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6.9.5.8 ECAP
Table 6-47, Table 6-48, Figure 6-38, Table 6-49, and Figure 6-39 present timing conditions, timing requirements,
and switching characteristics for ECAP.
Table 6-47. ECAP Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1 4 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 2 7 pF

Table 6-48. ECAP Timing Requirements

see Figure 6-38
NO. PARAMETER DESCRIPTION MIN MAX UNIT
CAP1 tw(CAP) Pulse duration, CAP (asynchronous) 2P(1) + 2 ns

(1) P = sysclk period in ns.

CAP1

CAP

EPERIPHERALS_TIMNG_01

Figure 6-38. ECAP Timings Requirements

Table 6-49. ECAP Switching Characteristics

see Figure 6-39
NO. PARAMETER DESCRIPTION MIN MAX UNIT
CAP2 tw(APWM) Pulse duration, APWMx high/low 2P(1) - 2 ns

(1) P = sysclk period in ns.

CAP2

APWM

EPERIPHERALS_TIMNG_02

Figure 6-39. ECAP Switching Characteristics

For more information, see Enhanced Capture (ECAP) Module section in Peripherals chapter in the device TRM.

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6.9.5.9 Emulation and Debug

For more details about features and additional description information on the device Trace and JTAG interfaces,
see the corresponding subsections within Signal Descriptions and Detailed Description sections.
6.9.5.9.1 Trace
Table 6-50. Trace Timing Conditions
PARAMETER MIN MAX UNIT
OUTPUT CONDITIONS
CL Output load capacitance 2 5 pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Mismatch) Propagation delay mismatch across all traces 200 ps

Table 6-51. Trace Switching Characteristics

NO. PARAMETER MIN MAX UNIT
1.8V Mode
DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 6.83 ns
DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 2.66 ns
DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 2.66 ns
tosu(TRC_DATAV-
DBTR4 Output setup time, TRC_DATA valid to TRC_CLK edge 0.85 ns
TRC_CLK)

DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 0.85 ns
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 0.85 ns
DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 0.85 ns
3.3V Mode
DBTR1 tc(TRC_CLK) Cycle time, TRC_CLK 8.78 ns
DBTR2 tw(TRC_CLKH) Pulse width, TRC_CLK high 3.64 ns
DBTR3 tw(TRC_CLKL) Pulse width, TRC_CLK low 3.64 ns
tosu(TRC_DATAV-
DBTR4 Output setup time, TRC_DATA valid to TRC_CLK edge 1.10 ns
TRC_CLK)

DBTR5 toh(TRC_CLK-TRC_DATAI) Output hold time, TRC_CLK edge to TRC_DATA invalid 1.10 ns
DBTR6 tosu(TRC_CTLV-TRC_CLK) Output setup time, TRC_CTL valid to TRC_CLK edge 1.10 ns
DBTR7 toh(TRC_CLK-TRC_CTLI) Output hold time, TRC_CLK edge to TRC_CTL invalid 1.10 ns

DBTR1
DBTR2 DBTR3

TRC_CLK
(Worst Case 1)
(Ideal)
(Worst Case 2)
DBTR4 DBTR5 DBTR4 DBTR5
DBTR6 DBTR7 DBTR6 DBTR7

TRC_DATA
TRC_CTL

SPRSP08_Debug_01

Figure 6-40. Trace Switching Characteristics

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6.9.5.9.2 JTAG
Table 6-52. JTAG Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.5 2.0 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 5 15 pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay) Propagation delay of each trace 83.5 1000(1) ps
td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps

(1) Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It
may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the
additional trace delay.
Table 6-53. JTAG Timing Requirements
see Figure 6-41
NO. MIN MAX UNIT
J1 tc(TCK) Cycle time minimum, TCK 40(1) ns
J2 tw(TCKH) Pulse width minimum, TCK high 0.4P(2) ns
J3 tw(TCKL) Pulse width minimum, TCK low 0.4P(2) ns
tsu(TDI-TCK) Input setup time minimum, TDI valid to TCK high 2 ns
J4
tsu(TMS-TCK) Input setup time minimum, TMS valid to TCK high 2 ns
th(TCK-TDI) Input hold time minimum, TDI valid from TCK high 3 ns
J5
th(TCK-TMS) Input hold time minimum, TMS valid from TCK high 3 ns

(1) The maximum TCK operating frequency assumes the following timing requirements and switching characteristis for the attached
debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these
assumptions.
• Minimum TDO setup time of 2ns relative to the rising edge of TCK
• TDI and TMS output delay in the range of -12.9ns to 13.9ns relative to the falling edge of TCK
(2) P = TCK cycle time in ns
Table 6-54. JTAG Switching Characteristics
see Figure 6-41
NO. PARAMETER MIN MAX UNIT
J6 td(TCKL-TDOI) Delay time minimum, TCK low to TDO invalid 0 ns
J7 td(TCKL-TDOV) Delay time maximum, TCK low to TDO valid 12 ns

J1
J2 J3

TCK
J4 J5 J4 J5

TDI / TMS

J7
J6

TDO

Figure 6-41. JTAG Timing Requirements and Switching Characteristics

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6.9.5.10 EPWM
Table 6-55, Table 6-56, Figure 6-42, Table 6-57, Figure 6-43, Figure 6-44, and Figure 6-45 present timing
conditions, timing requirements, and switching characteristics for EPWM.
Table 6-55. EPWM Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1 4 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 2 7 pF

Table 6-56. EPWM Timing Requirements

see Figure 6-42
NO. PARAMETER DESCRIPTION MIN MAX UNIT
PWM6 tw(SYNCIN) Pulse duration, EHRPWM_SYNCI 2P(1) + 2 ns
PWM7 tw(TZ) Pulse duration, EHRPWM_TZn_IN low 3P(1) +2 ns

(1) P = sysclk period in ns.

PWM6

EHRPWM_SYNCI

PWM7

EHRPWM_TZn_IN

EPERIPHERALS_TIMNG_07

Figure 6-42. EPWM Timing Requirements

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Table 6-57. EPWM Switching Characteristics

see Figure 6-43, Figure 6-44, and Figure 6-45
NO. PARAMETER DESCRIPTION MIN MAX UNIT
PWM1 tw(PWM) Pulse duration, EHRPWM_A/B high/low P(1) - 3 ns
PWM2 tw(SYNCOUT) Pulse duration, EHRPWM_SYNCO P(1) -3 ns
PWM3 td(TZ-PWM) Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B forced 11 ns
high/low
PWM4 td(TZ-PWMZ) Delay time, EHRPWM_TZn_IN active to EHRPWM_A/B Hi-Z 11 ns
PWM5 tw(SOC) Pulse duration, EHRPWM_SOCA/B output P(1) - 3 ns

(1) P = sysclk period in ns.

PWM1

EHRPWM_A/B

PWM1
PWM2

EHRPWM_SYNCO

PWM5

EHRPWM_SOCA/B

EPERIPHERALS_TIMNG_04

Figure 6-43. EHRPWM Switching Characteristics

PWM3

EHRPWM_A/B

EHRPWM_TZn_IN
EPERIPHERALS_TIMING_05

Figure 6-44. EHRPWM_TZn_IN to EHRPWM_A/B Forced Switching Characteristics

PWM4

EHRPWM_A/B

EHRPWM_TZn_IN

Figure 6-45. EHRPWM_TZn_IN to EHRPWM_A/B Hi-Z Switching Characteristics

For more information, see Enhanced Pulse Width Modulation (EPWM) Module section in Peripherals chapter in
the device TRM.

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6.9.5.11 EQEP
Table 6-58, Table 6-59, Figure 6-46, and Table 6-60 present timing conditions, timing requirements, and
switching characteristics for EQEP.
Table 6-58. EQEP Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1 4 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 2 7 pF

Table 6-59. EQEP Timing Requirements

see Figure 6-46
NO. PARAMETER DESCRIPTION MIN MAX UNIT
QEP1 tw(QEP) Pulse duration, QEP_A/B 2P(1) + 2 ns
QEP2 tw(QEPIH) Pulse duration, QEP_I high 2P(1) +2 ns
QEP3 tw(QEPIL) Pulse duration, QEP_I low 2P(1) + 2 ns
QEP4 tw(QEPSH) Pulse duration, QEP_S high 2P(1) +2 ns
QEP5 tw(QEPSL) Pulse duration, QEP_S low 2P(1) + 2 ns

(1) P = sysclk period in ns

QEP1

QEP_A/B

QEP2

QEP_I

QEP3
QEP4

QEP_S

QEP5 EPERIPHERALS_TIMNG_03

Figure 6-46. EQEP Timing Requirements

Table 6-60. EQEP Switching Characteristics

NO. PARAMETER DESCRIPTION MIN MAX UNIT
QEP6 td(QEP-CNTR) Delay time, external clock to counter increment 24 ns

For more information, see Enhanced Quadrature Encoder Pulse (EQEP) Module section in Peripherals chapter
in the device TRM.

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6.9.5.12 GPIO
Table 6-61, Table 6-62, and Table 6-63 present timing conditions, timing requirements, and switching
characteristics for GPIO.
The device has three instances of the GPIO module.
• MCU_GPIO0
• GPIO0
• GPIO1

Note
GPIOn_x is generic name used to describe a GPIO signal, where n represents the specific GPIO
module and x represents one of the input/output signals associated with the module.
For additional description information on the device GPIO, see the corresponding subsections within
Signal Descriptions and Detailed Description sections.

Table 6-61. GPIO Timing Conditions

PARAMETER BUFFER TYPE MIN MAX UNIT
INPUT CONDITIONS
LVCMOS
0.0018 6.6 V/ns
(VDD(1) = 1.8V)
LVCMOS
0.0033 6.6 V/ns
(VDD(1) = 3.3V)
SRI Input slew rate
I2C OD FS
0.0018 6.6 V/ns
(VDD(1) = 1.8V)
I2C OD FS
0.0033 0.08 V/ns
(VDD(1) = 3.3V)
OUTPUT CONDITIONS
LVCMOS 3 10 pF
CL Output load capacitance
I2C OD FS 3 100 pF

(1) P = functional clock period in ns.

Table 6-63. GPIO Switching Characteristics
NO. PARAMETER DESCRIPTION BUFFER TYPE MIN MAX UNIT
0.975P(1) -
LVCMOS ns
GPIO2 tw(GPIO_OUT) Pulse width, GPIOn_x 3.6
I2C OD FS 160 ns

(1) P = functional clock period in ns.

For more information, see General-Purpose Interface (GPIO) section in Peripherals chapter in the device TRM.

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6.9.5.13 GPMC
For more details about features and additional description information on the device General-Purpose Memory
Controller, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 6-64 presents timing conditions for GPMC.
Table 6-64. GPMC Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1.65 4 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 2 20 pF
PCB CONNECTIVITY REQUIREMENTS
133MHz Synchronous Mode 140 360 ps
td(Trace Delay) Propagation delay of each trace
All other modes 140 720 ps
td(Trace Mismatch
Propagation delay mismatch across all traces 200 ps
Delay)

For more information, see General-Purpose Memory Controller (GPMC) section in Peripherals chapter in the
device TRM.
6.9.5.13.1 GPMC and NOR Flash — Synchronous Mode
Table 6-65 and Table 6-66 present timing requirements and switching characteristics for GPMC and NOR Flash -
Synchronous Mode.
Table 6-65. GPMC and NOR Flash Timing Requirements — Synchronous Mode
see Figure 6-47, Figure 6-48, and Figure 6-51
MIN MAX MIN MAX
NO. PARAMETER DESCRIPTION MODE(4) GPMC_FCLK = GPMC_FCLK = UNIT
100MHz(1) 133MHz(1)
F12 tsu(dV-clkH) Setup time, input data div_by_1_mode; 1.61 0.92 ns
GPMC_AD[15:0] valid before output GPMC_FCLK_MUX;
clock GPMC_CLK high TIMEPARAGRANULARITY_X1
not_div_by_1_mode; 0.86 3.41 ns
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F13 th(clkH-dV) Hold time, input data div_by_1_mode; 2.09 2.09 ns
GPMC_AD[15:0] valid after output GPMC_FCLK_MUX;
clock GPMC_CLK high TIMEPARAGRANULARITY_X1
not_div_by_1_mode; 2.09 2.09 ns
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F21 tsu(waitV-clkH) Setup time, input wait div_by_1_mode; 1.61 0.92 ns
GPMC_WAIT[j](2) (3) valid before GPMC_FCLK_MUX;
output clock GPMC_CLK high TIMEPARAGRANULARITY_X1
not_div_by_1_mode; 0.86 3.41 ns
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F22 th(clkH-waitV) Hold time, input wait div_by_1_mode; 2.09 2.09 ns
GPMC_WAIT[j](2) (3) valid after GPMC_FCLK_MUX;
output clock GPMC_CLK high TIMEPARAGRANULARITY_X1
not_div_by_1_mode; 2.09 2.09 ns
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1

(1) GPMC_FCLK select

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• gpmc_fclk_sel[1:0] = 2b01 to select the 100MHz GPMC_FCLK

• gpmc_fclk_sel[1:0] = 2b00 to select the 133MHz GPMC_FCLK
(2) In GPMC_WAIT[j], j is equal to 0 or 1.
(3) Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-
Purpose Memory Controller (GPMC) section in the device TRM.
(4) For div_by_1_mode:
• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency

For not_div_by_1_mode:
• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 1h to 3h:
– GPMC_CLK frequency = GPMC_FCLK frequency / (2 to 4)

For GPMC_FCLK_MUX:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For TIMEPARAGRANULARITY_X1:
• GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Table 6-66. GPMC and NOR Flash Switching Characteristics – Synchronous Mode
see Figure 6-47, Figure 6-48, Figure 6-49, Figure 6-50, and Figure 6-51
NO. MIN MAX MIN MAX
(2) PARAMETER DESCRIPTION MODE(16) UNIT
100MHz 133MHz
F0 1 / tc(clk) Period, output clock GPMC_CLK(15) div_by_1_mode; 10.00 7.52 ns
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
F1 tw(clkH) Typical pulse duration, output clock div_by_1_mode; 0.475P 0.475P ns
GPMC_CLK high GPMC_FCLK_MUX; - 0.3(14) - 0.3(14)
TIMEPARAGRANULARITY_X1
F1 tw(clkL) Typical pulse duration, output clock div_by_1_mode; 0.475P 0.475P ns
GPMC_CLK low GPMC_FCLK_MUX; - 0.3(14) - 0.3(14)
TIMEPARAGRANULARITY_X1
F2 td(clkH-csnV) Delay time, output clock GPMC_CLK div_by_1_mode; F - 2.2 F+ F - 2.2 F+ ns
rising edge to output chip select GPMC_FCLK_MUX; (5) 3.75 (5) 3.75
GPMC_CSn[i] transition(13) TIMEPARAGRANULARITY_X1;
no extra_delay
F3 td(clkH-CSn[i]V) Delay time, output clock GPMC_CLK div_by_1_mode; E - 2.2 E+ E - 2.2 E + 4.5 ns
rising edge to output chip select GPMC_FCLK_MUX; (4) 3.18 (4)

GPMC_CSn[i] invalid(13) TIMEPARAGRANULARITY_X1;

no extra_delay
F4 td(aV-clk) Delay time, output address div_by_1_mode; B - 2.3 B + 4.5 B - 2.3 B + 4.5 ns
GPMC_A[27:1] valid to output clock GPMC_FCLK_MUX; (2) (2)

GPMC_CLK first edge TIMEPARAGRANULARITY_X1

F5 td(clkH-aIV) Delay time, output clock GPMC_CLK div_by_1_mode; -2.3 4.5 -2.3 4.5 ns
rising edge to output address GPMC_FCLK_MUX;
GPMC_A[27:1] invalid TIMEPARAGRANULARITY_X1
F6 td(be[x]nV-clk) Delay time, output lower byte div_by_1_mode; B - 2.3 B + 1.9 B - 2.3 B + 1.9 ns
enable and command latch enable GPMC_FCLK_MUX; (2) (2)

GPMC_BE0n_CLE, output upper byte TIMEPARAGRANULARITY_X1

enable GPMC_BE1n valid to output
clock GPMC_CLK first edge
F7 td(clkH-be[x]nIV) Delay time, output clock GPMC_CLK div_by_1_mode; D - D + 1.9 D - 2.3 D + 1.9 ns
rising edge to output lower byte GPMC_FCLK_MUX; 2.3(3) (3)

enable and command latch enable TIMEPARAGRANULARITY_X1

GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n invalid(10)

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Table 6-66. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued)
see Figure 6-47, Figure 6-48, Figure 6-49, Figure 6-50, and Figure 6-51
NO. MIN MAX MIN MAX
(2) PARAMETER DESCRIPTION MODE(16) UNIT
100MHz 133MHz
F7 td(clkL-be[x]nIV) Delay time, GPMC_CLK falling edge div_by_1_mode; D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns
to GPMC_BE0n_CLE, GPMC_BE1n GPMC_FCLK_MUX; (3) (3)

invalid(11) TIMEPARAGRANULARITY_X1
F7 td(clkL-be[x]nIV). Delay time, GPMC_CLK falling edge div_by_1_mode; D - 2.3 D + 1.9 D - 2.3 D + 1.9 ns
to GPMC_BE0n_CLE, GPMC_BE1n GPMC_FCLK_MUX; (3) (3)

invalid(12) TIMEPARAGRANULARITY_X1
F8 td(clkH-advn) Delay time, output clock GPMC_CLK div_by_1_mode; G - G + 4.5 G - 2.3 G + 4.5 ns
rising edge to output address GPMC_FCLK_MUX; 2.3(6) (6)

valid and address latch enable TIMEPARAGRANULARITY_X1;

GPMC_ADVn_ALE transition no extra_delay
F9 td(clkH-advnIV) Delay time, output clock GPMC_CLK div_by_1_mode; D - 2.3 D + 4.5 D - 2.3 D + 4.5 ns
rising edge to output address GPMC_FCLK_MUX; (3) (3)

valid and address latch enable TIMEPARAGRANULARITY_X1;

GPMC_ADVn_ALE invalid no extra_delay
F10 td(clkH-oen) Delay time, output clock GPMC_CLK div_by_1_mode; H - 2.3 H + 3.5 H - 2.3 H + 3.5 ns
rising edge to output enable GPMC_FCLK_MUX; (7) (7)

GPMC_OEn_REn transition TIMEPARAGRANULARITY_X1;

no extra_delay
F11 td(clkH-oenIV) Delay time, output clock GPMC_CLK div_by_1_mode; H - 2.3 H + 3.5 H - 2.3 H + 3.5 ns
rising edge to output enable GPMC_FCLK_MUX; (7) (7)

GPMC_OEn_REn invalid TIMEPARAGRANULARITY_X1;

no extra_delay
F14 td(clkH-wen) Delay time, output clock GPMC_CLK div_by_1_mode; I - 2.3 I + 4.5 I - 2.3 I + 4.5 ns
rising edge to output write enable GPMC_FCLK_MUX; (8) (8)

GPMC_WEn transition TIMEPARAGRANULARITY_X1;

no extra_delay
F15 td(clkH-do) Delay time, output clock GPMC_CLK div_by_1_mode; J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns
rising edge to output data GPMC_FCLK_MUX; (9) (9)

GPMC_AD[15:0] transition(10) TIMEPARAGRANULARITY_X1

F15 td(clkL-do) Delay time, GPMC_CLK falling div_by_1_mode; J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns
edge to GPMC_AD[15:0] data bus GPMC_FCLK_MUX; (9) (9)

transition(11) TIMEPARAGRANULARITY_X1
F15 td(clkL-do). Delay time, GPMC_CLK falling div_by_1_mode; J - 2.3 J + 2.7 J - 2.3 J + 2.7 ns
edge to GPMC_AD[15:0] data bus GPMC_FCLK_MUX; (9) (9)

transition(12) TIMEPARAGRANULARITY_X1
F17 td(clkH-be[x]n) Delay time, output clock GPMC_CLK div_by_1_mode; J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns
rising edge to output lower byte GPMC_FCLK_MUX; (9) (9)

enable and command latch enable TIMEPARAGRANULARITY_X1

GPMC_BE0n_CLE transition(10)
F17 td(clkL-be[x]n) Delay time, GPMC_CLK falling edge div_by_1_mode; J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns
to GPMC_BE0n_CLE, GPMC_BE1n GPMC_FCLK_MUX; (9) (9)

transition(11) TIMEPARAGRANULARITY_X1
F17 td(clkL-be[x]n). Delay time, GPMC_CLK falling edge div_by_1_mode; J - 2.3 J + 1.9 J - 2.3 J + 1.9 ns
to GPMC_BE0n_CLE, GPMC_BE1n GPMC_FCLK_MUX; (9) (9)

transition(12) TIMEPARAGRANULARITY_X1
F18 tw(csnV) Pulse duration, output chip select Read A A ns
GPMC_CSn[i](13) low
Write A A ns
F19 tw(be[x]nV) Pulse duration, output lower byte Read C C ns
enable and command latch enable
Write C C ns
GPMC_BE0n_CLE, output upper byte
enable GPMC_BE1n low

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Table 6-66. GPMC and NOR Flash Switching Characteristics – Synchronous Mode (continued)
see Figure 6-47, Figure 6-48, Figure 6-49, Figure 6-50, and Figure 6-51
NO. MIN MAX MIN MAX
(2) PARAMETER DESCRIPTION MODE(16) UNIT
100MHz 133MHz
F20 tw(advnV) Pulse duration, output address Read K K ns
valid and address latch enable
Write K K ns
GPMC_ADVn_ALE low

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
With n being the page burst access number.
(2) B = ClkActivationTime × GPMC_FCLK(14)
(3) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(4) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) For csn falling edge (CS activated):
• Case GPMCFCLKDIVIDER = 0:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(14)
• Case GPMCFCLKDIVIDER = 1:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and
CSOnTime are even)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) otherwise
• Case GPMCFCLKDIVIDER = 2:
– F = 0.5 × CSExtraDelay × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime) is a multiple of 3)
– F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
– F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK(14) if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
(6) For ADV falling edge (ADV activated):
• Case GPMCFCLKDIVIDER = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
• Case GPMCFCLKDIVIDER = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and
ADVOnTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
• Case GPMCFCLKDIVIDER = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Reading mode:

• Case GPMCFCLKDIVIDER = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)
• Case GPMCFCLKDIVIDER = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and
ADVRdOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
• Case GPMCFCLKDIVIDER = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)

For ADV rising edge (ADV deactivated) in Writing mode:

• Case GPMCFCLKDIVIDER = 0:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14)

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• Case GPMCFCLKDIVIDER = 1:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and
ADVWrOffTime are even)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) otherwise
• Case GPMCFCLKDIVIDER = 2:
– G = 0.5 × ADVExtraDelay × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
– G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
– G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK(14) if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
(7) For OE falling edge (OE activated) and IO DIR rising edge (Data Bus input direction):
• Case GPMCFCLKDIVIDER = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
• Case GPMCFCLKDIVIDER = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and
OEOnTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
• Case GPMCFCLKDIVIDER = 2:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime) is a multiple of 3)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)

For OE rising edge (OE deactivated):

• Case GPMCFCLKDIVIDER = 0:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14)
• Case GPMCFCLKDIVIDER = 1:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and
OEOffTime are even)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) otherwise
• Case GPMCFCLKDIVIDER = 2:
– H = 0.5 × OEExtraDelay × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime) is a multiple of 3)
– H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
– H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK(14) if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
(8) For WE falling edge (WE activated):
• Case GPMCFCLKDIVIDER = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(14)
• Case GPMCFCLKDIVIDER = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and
WEOnTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
• Case GPMCFCLKDIVIDER = 2:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)

For WE rising edge (WE deactivated):

• Case GPMCFCLKDIVIDER = 0:
– I = 0.5 × WEExtraDelay × GPMC_FCLK (14)
• Case GPMCFCLKDIVIDER = 1:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and
WEOffTime are even)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) otherwise
• Case GPMCFCLKDIVIDER = 2:
– I = 0.5 × WEExtraDelay × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime) is a multiple of 3)
– I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
– I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK(14) if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
(9) J = GPMC_FCLK(14)
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(10) First transfer only for CLK DIV 1 mode.

(11) Half cycle; for all data after initial transfer for CLK DIV 1 mode.
(12) Half cycle of GPMC_CLKOUT; for all data for modes other than CLK DIV 1 mode. GPMC_CLKOUT divide down from GPMC_FCLK.
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.
(14) P = GPMC_CLK period in ns
(15) Related to the GPMC_CLK output clock maximum and minimum frequencies programmable in the GPMC module by setting the
GPMC_CONFIG1_i configuration register bit field GPMCFCLKDIVIDER.
(16) For div_by_1_mode:
• GPMC_CONFIG1_i register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 01 = PER1_PLL_CLKOUT / 3 = 300 / 3 = 100MHz

For no extra_delay:
• GPMC_CONFIG2_i Register: CSEXTRADELAY = 0h = CSn Timing control signal is not delayed
• GPMC_CONFIG4_i Register: WEEXTRADELAY = 0h = nWE timing control signal is not delayed
• GPMC_CONFIG4_i Register: OEEXTRADELAY = 0h = nOE timing control signal is not delayed
• GPMC_CONFIG3_i Register: ADVEXTRADELAY = 0h = nADV timing control signal is not delayed
F1
F0 F1
GPMC_CLK
F2 F3
F18
GPMC_CSn[i]
F4
GPMC_A[MSB:1] Valid Address
F6 F7
F19
GPMC_BE0n_CLE
F19
GPMC_BE1n
F6 F8 F8
F20 F9
GPMC_ADVn_ALE
F10 F11

GPMC_OEn_REn
F13
F12
GPMC_AD[15:0] D0

GPMC_WAIT[j]
GPMC_01

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-47. GPMC and NOR Flash — Synchronous Single Read (GPMCFCLKDIVIDER = 0)

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F1
F0 F1
GPMC_CLK
F2 F3
GPMC_CSn[i]
F4
GPMCA[MSB:1] Valid Address
F6 F7
GPMC_BE0n_CLE
F7
GPMC_BE1n
F6 F8 F8 F9

GPMC_ADVn_ALE
F10 F11
GPMC_OEn_REn
F13 F13
F12 F12
GPMC_AD[15:0] D0 D1 D2 D3
F21 F22
GPMC_WAIT[j]
GPMC_02

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-48. GPMC and NOR Flash — Synchronous Burst Read — 4x16–bit (GPMCFCLKDIVIDER = 0)

F1
F1 F0
GPMC_CLK
F2 F3
GPMC_CSn[i]
F4
GPMC_A[MSB:1] Valid Address
F17
F6 F17 F17
GPMC_BE0n_CLE
F17
F17 F17
GPMC_BE1n
F6 F8 F8 F9
GPMC_ADVn_ALE
F14 F14
GPMC_WEn
F15 F15 F15
GPMC_AD[15:0] D0 D1 D2 D3
GPMC_WAIT[j]
GPMC_03

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

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B. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-49. GPMC and NOR Flash—Synchronous Burst Write (GPMCFCLKDIVIDER = 0)

F1
F0 F1
GPMC_CLK
F2 F3
GPMC_CSn[i]
F6 F7
GMPC_BE0n_CLE Valid
F6 F7
GPMC_BE1n Valid
F4
GPMC_A[27:17] Address (MSB)
F12
F4 F5 F13 F12
GPMC_AD[15:0] Address (LSB) D0 D1 D2 D3
F8 F8 F9
GPMC_ADVn_ALE
F10 F11
GPMC_OEn_REn

GPMC_WAIT[j]
GPMC_04

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-50. GPMC and Multiplexed NOR Flash — Synchronous Burst Read

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F1
F1 F0
GPMC_CLK
F2 F3
F18
GPMC_CSn[i]
F4
GPMC_A[27:17] Address (MSB)
F17
F6 F17 F17
GPMC_BE1n
F17
F6 F17 F17
BPMC_BE0n_CLE
F8 F8
F20 F9
GPMC_ADVn_ALE

F14 F14
GPMC_WEn
F15 F15 F15
GPMC_AD[15:0] Address (LSB) D0 D1 D2 D3
F22 F21
GPMC_WAIT[j]
GPMC_05

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
B. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-51. GPMC and Multiplexed NOR Flash — Synchronous Burst Write

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6.9.5.13.2 GPMC and NOR Flash — Asynchronous Mode

Table 6-67 and Table 6-68 present timing requirements and switching characteristics for GPMC and NOR Flash
— Asynchronous Mode.
Table 6-67. GPMC and NOR Flash Timing Requirements – Asynchronous Mode
see Figure 6-52, Figure 6-53, Figure 6-54, and Figure 6-56
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
(1) (4)
FA5 tacc(d) Data access time div_by_1_mode; H ns
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
(3)
FA20 tacc1-pgmode(d) Page mode successive data access time div_by_1_mode; P ns
(2)
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
(4)
FA21 tacc2-pgmode(d) Page mode first data access time div_by_1_mode; H ns
(1)
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1

(1) The FA5 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA5 functional clock cycles, input data is internally sampled by active
functional clock edge. FA5 value must be stored inside the AccessTime register bit field.
(2) The FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of
GPMC functional clock cycles. After each access to input page data, next input page data is internally sampled by active functional
clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.
(3) P = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(4) H = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(5)
(5) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
Table 6-68. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
see Figure 6-52, Figure 6-53, Figure 6-54, Figure 6-55, Figure 6-56, and Figure 6-57
(15)
MIN MAX
NO. PARAMETER DESCRIPTION MODE UNIT
133MHz
FA0 tw(be[x]nV) Pulse duration, output lower-byte enable and Read N (12) ns
command latch enable GPMC_BE0n_CLE, output
Write N (12)
upper-byte enable GPMC_BE1n valid time
FA1 tw(csnV) Pulse duration, output chip select GPMC_CSn[i](13) Read A (1) ns
low
Write A (1)
FA3 td(csnV-advnIV) Delay time, output chip select GPMC_CSn[i](13) Read B - 2 (2) B + 2(2) ns
valid to output address valid and address latch
Write B - 2(2) B + 2(2)
enable GPMC_ADVn_ALE invalid
FA4 td(csnV-oenIV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; C - 2(3) C + 2(3) ns
valid to output enable GPMC_OEn_REn invalid GPMC_FCLK_MUX;
(Single read) TIMEPARAGRANULARITY_X1
FA9 td(aV-csnV) Delay time, output address GPMC_A[27:1] valid to div_by_1_mode; J - 2(9) J + 2(9) ns
output chip select GPMC_CSn[i](13) valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA10 td(be[x]nV-csnV) Delay time, output lower-byte enable and div_by_1_mode; J - 2(9) J + 2(9) ns
command latch enable GPMC_BE0n_CLE, output GPMC_FCLK_MUX;
upper-byte enable GPMC_BE1n valid to output TIMEPARAGRANULARITY_X1
chip select GPMC_CSn[i](13) valid
FA12 td(csnV-advnV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; K - 2(10) K + 2(10) ns
valid to output address valid and address latch GPMC_FCLK_MUX;
enable GPMC_ADVn_ALE valid TIMEPARAGRANULARITY_X1
FA13 td(csnV-oenV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; L - 2(11) L + 2(11) ns
valid to output enable GPMC_OEn_REn valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA16 tw(aIV) Pulse duration output address GPMC_A[26:1] div_by_1_mode; G (7) ns
invalid between 2 successive read and write GPMC_FCLK_MUX;
accesses TIMEPARAGRANULARITY_X1

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Table 6-68. GPMC and NOR Flash Switching Characteristics – Asynchronous Mode (continued)
see Figure 6-52, Figure 6-53, Figure 6-54, Figure 6-55, Figure 6-56, and Figure 6-57
(15)
MIN MAX
NO. PARAMETER DESCRIPTION MODE UNIT
133MHz
FA18 td(csnV-oenIV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; I - 2(8) I + 2(8) ns
valid to output enable GPMC_OEn_REn invalid GPMC_FCLK_MUX;
(Burst read) TIMEPARAGRANULARITY_X1
FA20 tw(aV) Pulse duration, output address GPMC_A[27:1] div_by_1_mode; D (4) ns
valid - 2nd, 3rd, and 4th accesses GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA25 td(csnV-wenV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; E - 2(5) E + 2(5) ns
valid to output write enable GPMC_WEn valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA27 td(csnV-wenIV) Delay time, output chip select GPMC_CSn[i](13) div_by_1_mode; F - 2(6) F + 2(6) ns
valid to output write enable GPMC_WEn invalid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA28 td(wenV-dV) Delay time, output write enable GPMC_WEn valid div_by_1_mode; 2 ns
to output data GPMC_AD[15:0] valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA29 td(dV-csnV) Delay time, output data GPMC_AD[15:0] valid to div_by_1_mode; J - 2(9) J + 2(9) ns
output chip select GPMC_CSn[i](13) valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
FA37 td(oenV-aIV) Delay time, output enable GPMC_OEn_REn valid div_by_1_mode; 2 ns
to output address GPMC_AD[15:0] phase end GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1

(1) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)

For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
with n being the page burst access number
(2) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) ×
GPMC_FCLK(14)
(3) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(4) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(5) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(6) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(7) G = Cycle2CycleDelay × GPMC_FCLK(14)
(8) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay))
× GPMC_FCLK(14)
(9) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK(14)
(10) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(11) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK(14)
(12) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK(14)
(13) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(14) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(15) For div_by_1_mode:
• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33MHz

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OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,

WRDATAONADMUXBUS)
GPMC_FCLK
GPMC_CLK
FA5
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1] Valid Address
FA0
FA10
GPMC_BE0n_CLE Valid
FA0
GPMC_BE1n Valid
FA10
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
GPMC_AD[15:0] Data IN 0 Data IN 0

GPMC_WAIT[j]
GPMC_06

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], jis equal to 0 or 1.

B. FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
C. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 6-52. GPMC and NOR Flash — Asynchronous Read — Single Word

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GPMC_FCLK

GPMC_CLK
FA5 FA5
FA1 FA1
GPMC_CSn[i]
FA16
FA9 FA9

GPMC_A[MSB:1] Address 0 Address 1

FA0 FA0
FA10 FA10

GPMC_BE0n_CLE Valid Valid

FA0 FA0
GPMC_BE1n Valid Valid
FA10 FA10

FA3 FA3
FA12 FA12
GPMC_ADCn_ALE
FA4 FA4
FA13 FA13
GPMC_OEn_REn
GPMC_AD[15:0] Data Upper

GPMC_WAIT[j]
GPMC_07

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-53. GPMC and NOR Flash — Asynchronous Read — 32–Bit

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GPMC_FCLK

GPMC_CLK
FA21 FA20 FA20 FA20
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1] Add0 Add1 Add2 Add3 Add4
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA12

GPMC_ADVn_ALE
FA18
FA13
GPMC_OEn_REn
GPMC_AD[15:0] D0 D1 D2 D3 D3

GPMC_WAIT[j]
GPMC_08

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

B. FA21 parameter illustrates amount of time required to internally sample first input page data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, first input page data will be internally sampled by
active functional clock edge. FA21 calculation must be stored inside AccessTime register bits field.
C. FA20 parameter illustrates amount of time required to internally sample successive input page data. It is expressed in number of GPMC
functional clock cycles. After each access to input page data, next input page data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input page data (excluding first
input page data). FA20 value must be stored in PageBurstAccessTime register bits field.
D. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.

Figure 6-54. GPMC and NOR Flash — Asynchronous Read — Page Mode 4x16–Bit

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GPMC_FCLK

GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[MSB:1] Valid Address
FA0
FA10

GPMC_BE0n_CLE
FA0
FA10

GPMC_BE1n
FA3
FA12

GPMC_ADVn_ALE
FA27
FA25

GPMC_WEn
FA29
GPMC_AD[15:0] Data OUT

GPMC_WAIT[j]
GPMC_09

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-55. GPMC and NOR Flash — Asynchronous Write — Single Word

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GPMC_FCLK

GPMC_CLK
FA1
FA5
GPMC_CSn[i]
FA9
GPMC_A[27:17] Address (MSB)
FA0
FA10
GPMC_BE0n_CLE Valid
FA0
FA10
GPMC_BE1n Valid
FA3
FA12
GPMC_ADVn_ALE
FA4
FA13
GPMC_OEn_REn
FA29 FA37
GPMC_AD[15:0] Address (LSB) Data IN Data IN

GPMC_WAIT[j]
GPMC_10

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-56. GPMC and Multiplexed NOR Flash — Asynchronous Read — Single Word

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GPMC_FCLK

GPMC_CLK
FA1
GPMC_CSn[i]
FA9
GPMC_A[27:17] Address (MSB)
FA0
FA10
GPMC_BE0n_CLE
FA0
FA10
GPMC_BE1n
FA3
FA12
GPMC_ADVn_ALE
FA27
FA25
GPMC_WEn
FA29 FA28
GPMC_AD[15:0] Valid Address (LSB) Data OUT

GPMC_WAIT[j]
GPMC_11

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-57. GPMC and Multiplexed NOR Flash — Asynchronous Write — Single Word

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6.9.5.13.3 GPMC and NAND Flash — Asynchronous Mode

Table 6-69 and Table 6-70 present timing requirements and switching characteristics for GPMC and NAND Flash
— Asynchronous Mode.
Table 6-69. GPMC and NAND Flash Timing Requirements – Asynchronous Mode
see Figure 6-60
(4)
MIN MAX
NO. PARAMETER DESCRIPTION MODE UNIT
133MHz
(1) (3) (2)
GNF12 tacc(d) Access time, input data GPMC_AD[15:0] div_by_1_mode; J ns
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1

(1) The GNF12 parameter illustrates the amount of time required to internally sample input data. It is expressed in number of GPMC
functional clock cycles. From start of the read cycle and after GNF12 functional clock cycles, input data is internally sampled by the
active functional clock edge. The GNF12 value must be stored inside AccessTime register bit field.
(2) J = AccessTime × (TimeParaGranularity + 1) × GPMC_FCLK(3)
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33MHz

For TIMEPARAGRANULARITY_X1:
• GPMC_CONFIG1_i Register: TIMEPARAGRANULARITY = 0h = x1 latencies (affecting RD/WRCYCLETIME, RD/
WRACCESSTIME, PAGEBURSTACCESSTIME, CSONTIME, CSRD/WROFFTIME, ADVONTIME, ADVRD/WROFFTIME,
OEONTIME, OEOFFTIME, WEONTIME, WEOFFTIME, CYCLE2CYCLEDELAY, BUSTURNAROUND, TIMEOUTSTARTVALUE,
WRDATAONADMUXBUS)
Table 6-70. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
see Figure 6-58, Figure 6-59, Figure 6-60 and Figure 6-61
(4)
NO. PARAMETER MODE MIN MAX UNIT
GNF0 tw(wenV) Pulse duration, output write enable GPMC_WEn div_by_1_mode; A ns
valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF1 td(csnV-wenV) Delay time, output chip select GPMC_CSn[i](2) div_by_1_mode; B-2 B+2 ns
valid to output write enable GPMC_WEn valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF2 tw(cleH-wenV) Delay time, output lower-byte enable and div_by_1_mode; C-2 C+2 ns
command latch enable GPMC_BE0n_CLE high to GPMC_FCLK_MUX;
output write enable GPMC_WEn valid TIMEPARAGRANULARITY_X1
GNF3 tw(wenV-dV) Delay time, output data GPMC_AD[15:0] valid to div_by_1_mode; D-2 D+2 ns
output write enable GPMC_WEn valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF4 tw(wenIV-dIV) Delay time, output write enable GPMC_WEn div_by_1_mode; E-2 E+2 ns
invalid to output data GPMC_AD[15:0] invalid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF5 tw(wenIV-cleIV) Delay time, output write enable GPMC_WEn div_by_1_mode; F-2 F+2 ns
invalid to output lower-byte enable and command GPMC_FCLK_MUX;
latch enable GPMC_BE0n_CLE invalid TIMEPARAGRANULARITY_X1
GNF6 tw(wenIV-CSn[i]V) Delay time, output write enable GPMC_WEn div_by_1_mode; G-2 G+2 ns
invalid to output chip select GPMC_CSn[i](2) GPMC_FCLK_MUX;
invalid TIMEPARAGRANULARITY_X1
GNF7 tw(aleH-wenV) Delay time, output address valid and address latch div_by_1_mode; C-2 C+2 ns
enable GPMC_ADVn_ALE high to output write GPMC_FCLK_MUX;
enable GPMC_WEn valid TIMEPARAGRANULARITY_X1

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Table 6-70. GPMC and NAND Flash Switching Characteristics – Asynchronous Mode (continued)
see Figure 6-58, Figure 6-59, Figure 6-60 and Figure 6-61
(4)
NO. PARAMETER MODE MIN MAX UNIT
GNF8 tw(wenIV-aleIV) Delay time, output write enable GPMC_WEn div_by_1_mode; F-2 F+2 ns
invalid to output address valid and address latch GPMC_FCLK_MUX;
enable GPMC_ADVn_ALE invalid TIMEPARAGRANULARITY_X1
GNF9 tc(wen) Cycle time, write div_by_1_mode; H ns
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF10 td(csnV-oenV) Delay time, output chip select GPMC_CSn[i](2) div_by_1_mode; I-2 I+2 ns
valid to output enable GPMC_OEn_REn valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF13 tw(oenV) Pulse duration, output enable GPMC_OEn_REn div_by_1_mode; K ns
valid GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF14 tc(oen) Cycle time, read div_by_1_mode; L ns
GPMC_FCLK_MUX;
TIMEPARAGRANULARITY_X1
GNF15 tw(oenIV-CSn[i]V) Delay time, output enable GPMC_OEn_REn div_by_1_mode; M-2 M+2 ns
invalid to output chip select GPMC_CSn[i](2) GPMC_FCLK_MUX;
invalid TIMEPARAGRANULARITY_X1

(1) A = (WEOffTime - WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK(3)

(2) In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.
(3) GPMC_FCLK is general-purpose memory controller internal functional clock period in ns.
(4) For div_by_1_mode:
• GPMC_CONFIG1_i Register: GPMCFCLKDIVIDER = 0h:
– GPMC_CLK frequency = GPMC_FCLK frequency

For GPMC_FCLK_MUX:
• CTRLMMR_GPMC_CLKSEL[1-0] CLK_SEL = 00 = CPSWHSDIV_CLKOUT3 = 2000/15 = 133.33MHz

GPMC_ADCn_ALE

GPMC_OEn_REn
GNF0
GPMC_WEn
GNF3 GNF4
GPMC_AD[15:0] Command
GPMC_12

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 6-58. GPMC and NAND Flash — Command Latch Cycle

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GPMC_FCLK
GNF1 GNF6
GPMC_CSn[i]

GPMC_BE0n_CLE
GNF7 GNF8
GPMC_ADVn_ALE

GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3 GNF4
GPMC_AD[15:0] Address
GPMC_13

A. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 6-59. GPMC and NAND Flash — Address Latch Cycle

GPMC_FCLK
GNF12
GNF10 GNF15
GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADVn_ALE
GNF14
GNF13
GPMC_OEn_REn

GPMC_AD[15:0] DATA

GPMC_WAIT[j]
GPMC_14

A. GNF12 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
B. GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
C. In GPMC_CSn[i], i is equal to 0, 1, 2 or 3. In GPMC_WAIT[j], j is equal to 0 or 1.

Figure 6-60. GPMC and NAND Flash — Data Read Cycle

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GPMC_FCLK
GNF1 GNF6
GPMC_CSn[i]

GPMC_BE0n_CLE

GPMC_ADVn_ALE

GPMC_OEn_REn
GNF9
GNF0
GPMC_WEn
GNF3 GNF4
GPMC_AD[15:0] DATA
GPMC_15

A. `In GPMC_CSn[i], i is equal to 0, 1, 2 or 3.

Figure 6-61. GPMC and NAND Flash — Data Write Cycle

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6.9.5.14 I2C
The device contains six multicontroller Inter-Integrated Circuit (I2C) controllers. Each I2C controller was
designed to be compliant to the Philips I2C-bus™ specification version 2.1. However, the device IOs are not
fully compliant to the I2C electrical specification. The speeds supported and exceptions are described per port
below:
• I2C0, I2C1, I2C2, and I2C3
– Speeds:
• Standard-mode (up to 100Kbits/s)
– 1.8V
– 3.3V
• Fast-mode (up to 400Kbits/s)
– 1.8V
– 3.3V
– Exceptions:
• The IOs associated with these ports are not compliant to the fall time requirements defined in the I2C
specification because they are implemented with higher performance LVCMOS push-pull IOs that were
designed to support other signal functions that could not be implemented with I2C compatible IOs. The
LVCMOS IOs being used on these ports are connected such they emulate open-drain outputs. This
emulation is achieved by forcing a constant low output and disabling the output buffer to enter the Hi-Z
state.
• The I2C specification defines a maximum input voltage VIH of (VDDmax + 0.5V), which exceeds the
absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.
• MCU_I2C0 and WKUP_I2C0
– Speeds:
• Standard-mode (up to 100Kbits/s)
– 1.8V
– 3.3V
• Fast-mode (up to 400Kbits/s)
– 1.8V
– 3.3V
• Hs-mode (up to 3.4Mbits/s)
– 1.8V
– Exceptions:
• The IOs associated with these ports were not design to support Hs-mode while operating at 3.3V. So
Hs-mode is limited to 1.8V operation.
• The rise and fall times of the I2C signals connected to these ports must not exceed a slew rate of
0.08V/ns (or 8E+7V/s) when operating at 3.3V. This limit is more restrictive than the minimum fall time
limits defined in the I2C specification. Therefore, it may be necessary to add additional capacitance to
the I2C signals to slow the rise and fall times such that they do not exceed a slew rate of 0.08V/ns.
• The I2C specification defines a maximum input voltage VIH of (VDDmax + 0.5V), which exceeds the
absolute maximum ratings for the device IOs. The system must be designed to ensure the I2C signals
never exceed the limits defined in the Absolute Maximum Ratings section of this datasheet.

Note
I2C3 has one or more signals which can be multiplexed to more than one pin. Timing is only valid for
specific pin combinations known as IOSETs. Valid pin combinations or IOSETs for this interface are
defined in the SysConfig-PinMux Tool.

Refer to the Philips I2C-bus specification version 2.1 for timing details.
For more details about features and additional description information on the device Inter-Integrated Circuit, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.

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6.9.5.15 MCAN
Table 6-71 and Table 6-72 presents timing conditions and switching characteristics for MCAN.
For more details about features and additional description information on the device Controller Area Network
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.

Note
The device has multiple MCAN modules. MCANn is a generic prefix applied to MCAN signal names,
where n represents the specific MCAN module.

Table 6-71. MCAN Timing Conditions

PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 2 15 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 5 20 pF

Table 6-72. MCAN Switching Characteristics

NO. PARAMETER DESCRIPTION MIN MAX UNIT
MCAN1 td(MCAN_TX) Delay time, transmit shift register to MCANn_TX 10 ns
MCAN2 td(MCAN_RX) Delay time, MCANn_RX to receive shift register 10 ns

For more information, see Controller Area Network (MCAN) section in Peripherals chapter in the device TRM.

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6.9.5.16 MCASP

Note
McASP has one or more signals which can be multiplexed to more than one pin. Timing requirements
and switching characteristics defined in this section are only valid for specific pin combinations known
as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux
Tool.

Table 6-73, Table 6-74, Figure 6-62, Table 6-75, and Figure 6-63 present timing conditions, timing requirements,
and switching characteristics for MCASP.
Table 6-73. MCASP Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.7 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 1 10 pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay) Propagation delay of each trace 100 1100 ps
td(Trace Mismatch Delay) Propagation delay mismatch across all traces 100 ps

Table 6-74. MCASP Timing Requirements

see Figure 6-62
NO. MODE(1) MIN MAX UNIT
ASP1 tc(AHCLKRX) Cycle time, MCASP[x]_AHCLKR/X(4) 20 ns
0.5P(2) - ns
ASP2 tw(AHCLKRX) Pulse duration, MCASP[x]_AHCLKR/X(4) high or low
1.53
ASP3 tc(ACLKRX) Cycle time, MCASP[x]_ACLKR/X(4) 20 ns
0.5R(3)- ns
ASP4 tw(ACLKRX) Pulse duration, MCASP[x]_ACLKR/X(4) high or low
1.53

Setup time, MCASP[x]_AFSR/X(4) input valid before ACLKR/X int 9.29 ns

ASP5 tsu(AFSRX-ACLKRX)
MCASP[x]_ACLKR/X(4) ACLKR/X ext in/out 4

Hold time, MCASP[x]_AFSR/X(4) input valid after ACLKR/X int -1 ns

ASP6 th(ACLKRX-AFSRX)
MCASP[x]_ACLKR/X(4) ACLKR/X ext in/out 1.6

Setup time, MCASP[x]_AXR(4) input valid before ACLKR/X int 9.29 ns

ASP7 tsu(AXR-ACLKRX)
MCASP[x]_ACLKR/X(4) ACLKR/X ext in/out 4

Hold time, MCASP[x]_AXR(4) input valid after ACLKR/X int -1 ns

ASP8 th(ACLKRX-AXR)
MCASP[x]_ACLKR/X(4) ACLKR/X ext in/out 1.6

(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKR/X period in ns. For details on AHCLKR/X clock source options, see the McASP Clocks table in the Multichannel Audio
Serial Port (MCASP) section of the Module Integration chapter found in the Technical Reference Manual.
(3) R = ACLKR/X period in ns.
(4) x in MCASP[x]_* is 0, 1 or 2

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ASP2
ASP1
ASP2
MCASP[x]_AHCLKR/X (Falling Edge Priority)

MCASP[x]_AHCLKR/X (Rising Edge Polarity)

ASP4
ASP3 ASP4
(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)

(B)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)

ASP6
ASP5
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay)

ASP8
ASP7
MCASP[x]_AXR[x] (Data In/Receive)

A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31

A. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).

Figure 6-62. MCASP Timing Requirements

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Table 6-75. MCASP Switching Characteristics

see Figure 6-63
NO. PARAMETER DESCRIPTION MODE(1) MIN MAX UNIT
ASP9 tc(AHCLKRX) Cycle time, MCASP[x]_AHCLKR/X(4) 20 ns
ASP10 tw(AHCLKRX) Pulse duration, MCASP[x]_AHCLKR/X(4) high or low 0.5P(2) -2 ns
ASP11 tc(ACLKRX) Cycle time, MCASP[x]_ACLKR/X(4) 20 ns
ASP12 tw(ACLKRX) Pulse duration, MCASP[x]_ACLKR/X(4) high or low 0.5R(3) -2 ns

Delay time, MCASP[x]_ACLKR/X(4)

transmit edge to ACLKR/X int -1 7.25
ASP13 td(ACLKRX-AFSRX) ns
MCASP[x]_AFSR/X(4) output valid ACLKR/X ext in/out -15.29 12.84

Delay time, MCASP[x]_ACLKX(4) transmit edge to ACLKR/X int -1 7.25

ASP14 td(ACLKX-AXR) ns
MCASP[x]_AXR(4) output valid ACLKR/X ext in/out -15.29 12.84

Disable time, MCASP[x]_ACLKX(4) transmit edge to ACLKR/X int -1 7.25

ASP15 tdis(ACLKX-AXR) ns
MCASP[x]_AXR(4) output high impedance ACLKR/X ext in/out -14.9 14

(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1

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ASP10
ASP9 ASP10

MCASP[x]_AHCLKR/X (Falling Edge Priority)

MCASP[x]_AHCLKR/X (Rising Edge Polarity)

ASP12
ASP11
ASP12
(A)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 1)

(B)
MCASP[x]_ACLKR/X (CLKRP = CLKXP = 0)

ASP13 ASP13
ASP13 ASP13
MCASP[x]_AFSR/X (Bit Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Bit Width, 2 Bit Delay)

ASP13 ASP13 ASP13

MCASP[x]_AFSR/X (Slot Width, 0 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 1 Bit Delay)

MCASP[x]_AFSR/X (Slot Width, 2 Bit Delay) ASP14

ASP15

MCASP[x]_AXR[x] (Data Out/Transmit)

A0 A1 A30 A31 B0 B1 B30 B31 C0 C1 C2 C3 C31

A. For CLKRP = CLKXP = 1, the MCASP transmitter is configured for falling edge (to shift data out) and the MCASP receiver is configured
for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the MCASP transmitter is configured for rising edge (to shift data out) and the MCASP receiver is configured
for falling edge (to shift data in).

Figure 6-63. MCASP Switching Characteristics

For more information, see Multichannel Audio Serial Port (MCASP) section in Peripherals chapter in the device
TRM.

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6.9.5.17 MCSPI

Note
McSPI has one or more signals which can be multiplexed to more than one pin. Timing requirements
and switching characteristics defined in this section are only valid for specific pin combinations known
as IOSETs. Valid pin combinations or IOSETs for this interface are defined in the SysConfig-PinMux
Tool.

For more details about features and additional description information on the device Serial Port Interface, see
the corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 6-76 presents timing conditions for MCSPI.
Table 6-76. MCSPI Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 2 8.5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 6 12 pF

For more information, see Multichannel Serial Peripheral Interface (MCSPI) section in Peripherals chapter in the
device TRM.

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6.9.5.17.1 MCSPI — Controller Mode

Table 6-77, Figure 6-64, Table 6-78, and Figure 6-65 present timing requirements and switching characteristics
for SPI – Controller Mode.
Table 6-77. MCSPI Timing Requirements – Controller Mode
see Figure 6-64
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SM4 tsu(POCI-SPICLK) Setup time, SPIn_D[x] valid before SPIn_CLK active edge 2.8 ns
SM5 th(SPICLK-POCI) Hold time, SPIn_D[x] valid after SPIn_CLK active edge 3 ns

PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8 SM2 SM9
SPI_SCLK (OUT) POL=0

SM1
SM3
SM2
POL=1
SPI_SCLK (OUT)
SM5
SM5

SM4 SM4

SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0

PHA=1
EPOL=1
SPI_CS[i] (OUT)
SM2
SM1
SM8 SM3 SM9
SPI_SCLK (OUT) POL=0
SM1
SM2
SM3
POL=1
SPI_SCLK (OUT)

SM5
SM4
SM4 SM5

SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0

SPRSP08_TIMING_McSPI_02

Figure 6-64. SPI Controller Mode Receive Timing

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Table 6-78. MCSPI Switching Characteristics - Controller Mode

see Figure 6-65
NO. PARAMETER MIN MAX UNIT
SM1 tc(SPICLK) Cycle time, SPIn_CLK 20 ns
(1)
SM2 tw(SPICLKL) Pulse duration, SPIn_CLK low 0.5P - 1 ns
(1)
SM3 tw(SPICLKH) Pulse duration, SPIn_CLK high 0.5P - 1 ns
SM6 td(SPICLK-PICO) Delay time, SPIn_CLK active edge to SPIn_D[x] -3 2.5 ns
SM7 td(CS-PICO) Delay time, SPIn_CSi active edge to SPIn_D[x] 5 ns
(2)
SM8 td(CS-SPICLK) Delay time, SPIn_CSi active to SPIn_CLK first edge PHA = 0 B-4 ns
(3)
PHA = 1 A-4 ns
(4)
SM9 td(SPICLK-CS) Delay time, SPIn_CLK last edge to SPIn_CSi inactive PHA = 0 A-4 ns
(5)
PHA = 1 B-4 ns

(1) P = SPIn_CLK period in ns.

(2) T_ref is the period of the McSPI functional clock in ns. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK
clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the
MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register.
• When Fratio = 1; B = (TCS(i) + 0.5) * T_ref.
• When Fratio ≥ 2 and even value; B = (TCS(i) + 0.5) * Fratio * T_ref.
• When Fratio ≥ 3 and odd value; B = ((TCS(i) * Fratio) + ((Fratio + 1) / 2 )) * T_ref.
(3) T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK
clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the
MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register.
• When Fratio = 1; A = (TCS(i) + 1) * T_ref.
• When Fratio ≥ 2 and even value; A = (TCS(i) + 0.5) * Fratio * T_ref.
• When Fratio ≥ 3 and odd value; A = ((TCS(i) * Fratio) + ((Fratio - 1) / 2 )) * T_ref.
(4) T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK
clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the
MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register.
• When Fratio = 1; A = (TCS(i) + 1) * T_ref.
• When Fratio ≥ 2 and even value; A = (TCS(i) + 0.5) * Fratio * T_ref.
• When Fratio ≥ 3 and odd value; A = ((TCS(i) * Fratio) + ((Fratio + 1) / 2 )) * T_ref.
(5) T_ref is the period of the McSPI functional clock. Fratio is the divide ratio of McSPI functional clock frequency to SPIn_CLK
clock frequency, controlled by the CLKD and CLKG bit fields in the MSPI_CH(i)CONF register and the EXTCLK bit field in the
MSPI_CH(i)CTRL register. TCS(i) is the value programmed into the chip select time control bit field of the MSPI_CH(i)CONF register.
• When Fratio = 1; B = (TCS(i) + 0.5) * T_ref.
• When Fratio ≥ 2 and even value; B = (TCS(i) + 0.5) * Fratio * T_ref.
• When Fratio ≥ 3 and odd value; B = ((TCS(i) * Fratio) + ((Fratio - 1) / 2 )) * T_ref.

172 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

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PHA=0
EPOL=1
SPI_CS[i] (OUT)
SM1
SM3
SM8 SM2 SM9
SPI_SCLK (OUT) POL=0

SM1

SM3
POL=1 SM2
SPI_SCLK (OUT)

SM7 SM6 SM6

SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0

PHA=1
EPOL=1
SPI_CS[i] (OUT)

SM1
SM2
SM8 SM3 SM9
SPI_SCLK (OUT) POL=0

SM1
SM2

POL=1 SM3
SPI_SCLK (OUT)

SM6 SM6 SM6 SM6

SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit0

SPRSP08_TIMING_McSPI_01

Figure 6-65. SPI Controller Mode Transmit Timing

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6.9.5.17.2 MCSPI — Peripheral Mode

Table 6-79, Figure 6-66, Table 6-80, and Figure 6-67 present timing requirements and switching characteristics
for SPI – Peripheral Mode.
Table 6-79. MCSPI Timing Requirements – Peripheral Mode
see Figure 6-66
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SS1 tc(SPICLK) Cycle time, SPIn_CLK 20 ns
(1)
SS2 tw(SPICLKL) Pulse duration, SPIn_CLK low 0.45P ns
(1)
SS3 tw(SPICLKH) Pulse duration, SPIn_CLK high 0.45P ns
SS4 tsu(PICO-SPICLK) Setup time, SPIn_D[x] valid before SPIn_CLK active edge 5 ns
SS5 th(SPICLK-PICO) Hold time, SPIn_D[x] valid after SPIn_CLK active edge 5 ns
SS8 tsu(CS-SPICLK) Setup time, SPIn_CSi valid before SPIn_CLK first edge 5 ns
SS9 th(SPICLK-CS) Hold time, SPIn_CSi valid after SPIn_CLK last edge 5 ns

(1) P = SPIn_CLK period in ns.

PHA=0
EPOL=1
SPI_CS[i] (IN)

SS1
SS2
SS8 SS3 SS9
SPI_SCLK (IN) POL=0

SS1
SS2
POL=1 SS3
SPI_SCLK (IN)

SS5 SS4
SS4 SS5

SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0

PHA=1
EPOL=1
SPI_CS[i] (IN)

SS1
SS2
SS8 SS3 SS9
POL=0
SPI_SCLK (IN)

SS1
SS3
POL=1 SS2
SPI_SCLK (IN)

SS4
SS5
SS4 SS5

SPI_D[x] (IN) Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0

SPRSP08_TIMING_McSPI_04

Figure 6-66. SPI Peripheral Mode Receive Timing

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Table 6-80. MCSPI Switching Characteristics – Peripheral Mode

see Figure 6-67
NO. PARAMETER DESCRIPTION MIN MAX UNIT
SS6 td(SPICLK-POCI) Delay time, SPIn_CLK active edge to SPIn_D[x] 2 17.12 ns
SS7 tsk(CS-POCI) Delay time, SPIn_CSi active edge to SPIn_D[x] 20.95 ns

PHA=0
EPOL=1
SPI_CS[i] (IN)

SS1
SS2
SS8 SS3 SS9
SPI_SCLK (IN) POL=0

SS1
SS2
POL=1 SS3
SPI_SCLK (IN)

SS7 SS6 SS6

SPI_D[x] (OUT) Bit n-1 Bit n-2 Bit n-3 Bit n-4 Bit 0

PHA=1
EPOL=1
SPI_CS[i] (IN)

SS1
SS2
SS8 SS3 SS9
POL=0
SPI_SCLK (IN)

SS1
SS3
POL=1 SS2
SPI_SCLK (IN)

SS6 SS6 SS6 SS6

SPI_D[x] (OUT)
Bit n-1 Bit n-2 Bit n-3 Bit 1 Bit 0

SPRSP08_TIMING_McSPI_03

Figure 6-67. SPI Peripheral Mode Transmit Timing

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6.9.5.18 MMCSD
The MMCSD Host Controller provides an interface to embedded Multi-Media Card (MMC), Secure Digital (SD),
and Secure Digital IO (SDIO) devices. The MMCSD Host Controller deals with MMC/SD/SDIO protocol at
transmission level, data packing, adding cyclic redundancy checks (CRCs), start/end bit insertion, and checking
for syntactical correctness.
For more details about MMCSD interfaces, see the corresponding MMC0, MMC1, and MMC2 subsections within
Signal Descriptions and Detailed Description sections.

Note
Some operating modes require software configuration of the MMC DLL delay settings, as shown in
Table 6-81 and Table 6-99.
The modes which show a value of "Tuning" in the ITAPDLYSEL column of Table 6-81 and Table 6-99
require a tuning algorithm to be used for optimizing input timing. Refer to the MMCSD Programming
Guide in the device TRM for more information on the tuning algorithm and configuration of input
delays required to optimize input timing.

For more information, see Multi-Media Card/Secure Digital (MMCSD) Interface section in Peripherals chapter in
the device TRM.

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6.9.5.18.1 MMC0 - eMMC Interface

MMC0 interface is compliant with the JEDEC eMMC electrical standard v5.1 (JESD84-B51) and it supports the
following eMMC applications:
• Legacy SDR
• High Speed SDR
• High Speed DDR
• HS200
• HS400
Table 6-81 presents the required DLL software configuration settings for MMC0 timing modes.
Table 6-81. MMC0 DLL Delay Mapping for all Timing Modes
MMCSD0_SS_PHY_CTRL_x_REG
REGISTER NAME
x=4 x=5 x=1
BIT FIELD [31:24] [20] [15:12] [8] [4:0] [17:16] [10:8] [2:0] [1]
SELDLYTXCLK
BIT FIELD NAME STRBSEL OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL FRQSEL CLKBUFSEL ENDLL
SELDLYRXCLK
OUTPUT OUTPUT INPUT INPUT DLL DELAY
STROBE DLL REF ENABLE
MODE DESCRIPTION DELAY DELAY DELAY DELAY DELAY CHAIN BUFFER
DELAY FREQUENCY DLL
ENABLE VALUE ENABLE VALUE SELECT DURATION
8-bit PHY
Legacy
operating 1.8V, 0x0 0x1 0x1 0x1 0x10 0x3 NA(1) 0x7 0x0
SDR
25MHz
High 8-bit PHY
Speed operating 1.8V, 0x0 0x1 0x1 0x1 0xA 0x3 NA(1) 0x7 0x0
SDR 50MHz
High 8-bit PHY
Speed operating 1.8V, 0x0 0x1 0x6 0x1 0x3 0x0 0x4 NA(1) 0x1
DDR 50MHz
8-bit PHY
HS200 operating 1.8V, 0x0 0x1 0x8 0x1 Tuning(2) 0x0 0x0 NA(1) 0x1
200MHz
8-bit PHY
HS400 operating 1.8V, 0x77 0x1 0x5 0x1 Tuning(2) 0x0 0x0 NA(1) 0x1
200MHz

(1) NA means Not Applicable

(2) Tuning means this mode requires a tuning algorithm to be used for optimal input timing

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Table 6-82 presents timing conditions for MMC0.

Table 6-82. MMC0 Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
Legacy SDR
0.3 0.9 V/ns
High Speed SDR
SRI Input slew rate
High Speed DDR (CMD) 0.3 0.9 V/ns
High Speed DDR (DAT) 0.45 0.9 V/ns
OUTPUT CONDITIONS
HS400 1 6 pF
CL Output load capacitance
All other modes 1 12 pF
PCB CONNECTIVITY REQUIREMENTS
td(Trace Delay) Propagation delay of each trace All modes 126 756 ps
HS200
8 ps
HS400
td(Trace Mismatch Propagation delay mismatch across all
Delay) traces High Speed DDR 20 ps
All other modes 100 ps

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6.9.5.18.1.1 Legacy SDR Mode

Table 6-83, Figure 6-68, Table 6-84, and Figure 6-69 present timing requirements and switching characteristics
for MMC0 – Legacy SDR Mode.
Table 6-83. MMC0 Timing Requirements – Legacy SDR Mode
see Figure 6-68
IO
NO. Operating MIN MAX UNIT
Voltage
1.8V 4.2 ns
LSDR1 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge
3.3V 2.15 ns
1.8V 0.87 ns
LSDR2 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge
3.3V 1.67 ns
1.8V 4.2 ns
LSDR3 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
3.3V 2.15 ns
1.8V 0.87 ns
LSDR4 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
3.3V 1.67 ns

Figure 6-68. MMC0 – Legacy SDR – Receive Mode

Table 6-84. MMC0 Switching Characteristics – Legacy SDR Mode

see Figure 6-69
IO
NO. PARAMETER Operating MIN MAX UNIT
Voltage
fop(clk) Operating frequency, MMC0_CLK 25 MHz
LSDR5 tc(clk) Cycle time, MMC0_CLK 40 ns
LSDR6 tw(clkH) Pulse duration, MMC0_CLK high 18.7 ns
LSDR7 tw(clkL) Pulse duration, MMC0_CLK low 18.7 ns
1.8V -2.1 2.1 ns
LSDR8 td(clkL-cmdV) Delay time, MMC0_CLK falling edge to MMC0_CMD transition
3.3V -1.8 2.2 ns
1.8V -2.1 2.1 ns
LSDR9 td(clkL-dV) Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
3.3V -1.8 2.2 ns

Figure 6-69. MMC0 – Legacy SDR – Transmit Mode

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6.9.5.18.1.2 High Speed SDR Mode

Table 6-85, Figure 6-70, Table 6-86, and Figure 6-71 present timing requirements and switching characteristics
for MMC0 – High Speed SDR Mode.
Table 6-85. MMC0 Timing Requirements – High Speed SDR Mode
see Figure 6-70
IO
NO. Operating MIN MAX UNIT
Voltage
1.8V 2.15 ns
HSSDR1 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge
3.3V 2.24 ns
1.8V 1.27 ns
HSSDR2 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge
3.3V 1.66 ns
1.8V 2.15 ns
HSSDR3 tsu(dV-clkH) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK rising edge
3.3V 2.24 ns
1.8V 1.27 ns
HSSDR4 th(clkH-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK rising edge
3.3V 1.66 ns

Figure 6-70. MMC0 – High Speed SDR Mode – Receive Mode

Table 6-86. MMC0 Switching Characteristics – High Speed SDR Mode

see Figure 6-71
IO
NO. PARAMETER Operating MIN MAX UNIT
Voltage
fop(clk) Operating frequency, MMC0_CLK 50 MHz
HSSDR5 tc(clk) Cycle time, MMC0_CLK 20 ns
HSSDR6 tw(clkH) Pulse duration, MMC0_CLK high 9.2 ns
HSSDR7 tw(clkL) Pulse duration, MMC0_CLK low 9.2 ns
1.8V -1.55 3.05 ns
HSSDR8 td(clkL-cmdV) Delay time, MMC0_CLK falling edge to MMC0_CMD transition
3.3V -1.8 2.2 ns
1.8V -1.55 3.05 ns
HSSDR9 td(clkL-dV) Delay time, MMC0_CLK falling edge to MMC0_DAT[7:0] transition
3.3V -1.8 2.2 ns

Figure 6-71. MMC0 – High Speed SDR Mode – Transmit Mode

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6.9.5.18.1.3 High Speed DDR Mode

Table 6-87, Figure 6-72, Table 6-88, and Figure 6-73 present timing requirements and switching characteristics
for MMC0 – High Speed DDR Mode.
Table 6-87. MMC0 Timing Requirements – High Speed DDR Mode
see Figure 6-72
NO. MIN MAX UNIT
HSDDR1 tsu(cmdV-clk) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 1.62 ns
HSDDR2 th(clk-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 2.52 ns
HSDDR3 tsu(dV-clk) Setup time, MMC0_DAT[7:0] valid before MMC0_CLK transition 0.83 ns
HSDDR4 th(clk-dV) Hold time, MMC0_DAT[7:0] valid after MMC0_CLK transition 1.76 ns

Figure 6-72. MMC0 – High Speed DDR Mode – Receive Mode

Table 6-88. MMC0 Switching Characteristics – High Speed DDR Mode

see Figure 6-73
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMC0_CLK 50 MHz
HSDDR5 tc(clk) Cycle time, MMC0_CLK 20 ns
HSDDR6 tw(clkH) Pulse duration, MMC0_CLK high 9.2 ns
HSDDR7 tw(clkL) Pulse duration, MMC0_CLK low 9.2 ns
HSDDR8 td(clk-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 3.31 7.65 ns
HSDDR9 td(clk-dV) Delay time, MMC0_CLK transition to MMC0_DAT[7:0] transition 2.81 6.94 ns

Figure 6-73. MMC0 – High Speed DDR Mode – Transmit Mode

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6.9.5.18.1.4 HS200 Mode

Table 6-89 and Figure 6-74 present switching characteristics for MMC0 – HS200 Mode.
Table 6-89. MMC0 Switching Characteristics – HS200 Mode
see Figure 6-74
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMC0_CLK 200 MHz
HS2005 tc(clk) Cycle time, MMC0_CLK 5 ns
HS2006 tw(clkH) Pulse duration, MMC0_CLK high 2.12 ns
HS2007 tw(clkL) Pulse duration, MMC0_CLK low 2.12 ns
HS2008 td(clkL-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 1.07 3.21 ns
HS2009 td(clkL-dV) Delay time, MMC0_CLK rising edge to MMC0_DAT[7:0] transition 1.07 3.21 ns

Figure 6-74. MMC0 – HS200 Mode – Transmit Mode

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6.9.5.18.1.5 HS400 Mode

Table 6-90, Figure 6-75, Table 6-91, and Figure 6-76 present timing requirements and switching characteristics
for MMC0 – HS400 Mode.
Table 6-90. MMC0 Timing Requirements – HS400 Mode
see Figure 6-75
NO. MIN MAX UNIT
HS4000 tDSMPW Pulse width, MMC0_DS 2.0 ns
HS4001 tRQ_DAT Input skew, MMC0_DS to MMC0_DAT valid 475 ps
HS4002 tRQH_DAT Input skew hold, MMC0_DAT invalid to MMC0_DS 475 ps
HS4003 tRQ_CMD Input skew, MMC0_DS to MMC0_CMD valid 475 ps
HS4004 tRQH_CMD Input skew hold, MMC0_CMD invalid to MMC0_DS 475 ps

HS4000

MMC0_DS VT
HS4000

HS4001 HS4002 HS4001 HS4002

VIH
Valid Valid
MMC0_DAT[7-0]
Window Window
VIL

HS4003 HS4004

VIH
Valid
MMC0_CMD
Window
VIL

Figure 6-75. MMC0 – HS400 – Receive Mode

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Table 6-91. MMC0 Switching Characteristics – HS400 Mode

see Figure 6-76
NO. PARAMETER DESCRIPTION MIN MAX UNIT
fop(clk) Operating frequency, MMC0_CLK 200 MHz
HS4005 tc(clkH) Cycle time, MMC0_CLK 5 ns
HS4006 tw(clkH) Pulse duration, MMC0_CLK high 2.24 ns
HS4007 tw(clkL) Pulse duration, MMC0_CLK low 2.24 ns
HS4008 tosu(cmdV-clkH) Output setup time, MMC0_CMD valid to MMC0_CLK rising edge(1) 2.58 ns
HS4009 tosu(dV-clk) Output setup time, MMC0_DAT[7:0] valid to MMC0_CLK rising or 0.60 ns
falling edge(1)
HS40010 toh(clkH-cmdIV) Output hold time, MMC0_CLK rising edge to MMC0_CMD invalid(2) 1.12 ns
HS40011 toh(clk-dIV) Output hold time, MMC0_CLK rising or falling edge to 0.85 ns
MMC0_DAT[7:0] invalid(2)

(1) This parameter defines the output setup time provided to the attached device. This time is relative to the next capture clock edge and
already includes the maximum propagation delay mismatch value defined in the MMC0 Timing Conditions table. The timing references
for this parameter are from mid-supply of the DAT or CMD signal transition to mid-supply of the CLK signal transition. The eMMC
standard defines the setup timing references from VIL or VIH of the DAT or CMD signal transition to mid-supply of the CLK signal
transition. Therefore, the system designer must consider the impact of the DAT signal slew rate when designing the PCB, and ensure
the time it takes for the DAT signal to slew from mid-supply to VIL or VIH does not erode the setup time margin.
(2) This parameter defines the output hold time provided to the attached device. This time is relative to the previous launch clock edge and
already includes the maximum propagation delay mismatch value defined in the MMC0 Timing Conditions table. The timing references
for this parameter are from mid-supply of the CLK signal transition to mid-supply of the DAT or CMD signal transition. The eMMC
standard defines the hold timing references from mid-supply of the CLK signal transition to VIL or VIH of the DAT or CMD signal
transition. Therefore, the system designer must consider the impact of the DAT signal slew rate when designing the PCB, and ensure
the time it takes for the DAT signal to slew from VIL or VIH to mid-supply does not erode the hold time margin.
HS4005
HS4006 HS4007
MMC0_CLK
HS4008 HS40010
MMC0_CMD
HS40011 HS40011
HS4009 HS4009
MMC0_DAT[7:0]

Figure 6-76. eMMC in – HS400 Mode – Transmitter Mode

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6.9.5.18.1.6 UHS–I SDR12 Mode

Table 6-92, Figure 6-77, Table 6-93, and Figure 6-78 present timing requirements and switching characteristics
for MMC0 – UHS-I SDR12 Mode.
Table 6-92. Timing Requirements for MMC0 – UHS-I SDR12 Mode
see Figure 6-77
NO. MIN MAX UNIT
SDR121 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 4.2 ns
SDR122 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 0.87 ns
SDR123 tsu(dV-clkH) Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge 4.2 ns
SDR124 th(clkH-dV) Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge 0.87 ns

MMC[x]_CLK

SDR121 SDR122

MMC[x]_CMD

SDR123 SDR124

MMC[x]_DAT[3:0]

Figure 6-77. MMC0 – UHS-I SDR12 – Receive Mode

Table 6-93. Switching Characteristics for MMC0 – UHS-I SDR12 Mode

see Figure 6-78
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMC0_CLK 25 MHz
SDR125 tc(clk) Cycle time, MMC0_CLK 40 ns
SDR126 tw(clkH) Pulse duration, MMC0_CLK high 18.7 ns
SDR127 tw(clkL) Pulse duration, MMC0_CLK low 18.7 ns
SDR128 td(clkL-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 1.5 8.6 ns
SDR129 td(clkL-dV) Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition 1.5 8.6 ns

SDR125

SDR126 SDR127

MMC[x]_CLK

SDR128 SDR128

MMC[x]_CMD

SDR129 SDR129

MMC[x]_DAT[3:0]

Figure 6-78. MMC0 – UHS-I SDR12 – Transmit Mode

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6.9.5.18.1.7 UHS–I SDR25 Mode

Table 6-94, Figure 6-79, Table 6-95, and Figure 6-80 present timing requirements and switching characteristics
for MMC0 – UHS-I SDR25 Mode.
Table 6-94. Timing Requirements for MMC0 – UHS-I SDR25 Mode
see Figure 6-79
NO. MIN MAX UNIT
SDR251 tsu(cmdV-clkH) Setup time, MMC0_CMD valid before MMC0_CLK rising edge 2.15 ns
SDR252 th(clkH-cmdV) Hold time, MMC0_CMD valid after MMC0_CLK rising edge 1.27 ns
SDR253 tsu(dV-clkH) Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge 2.15 ns
SDR254 th(clkH-dV) Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge 1.27 ns

MMC[x]_CLK

SDR251 SDR252

MMC[x]_CMD

SDR253 SDR254

MMC[x]_DAT[3:0]

Figure 6-79. MMC0 – UHS-I SDR25 – Receive Mode

Table 6-95. Switching Characteristics for MMC0 – UHS-I SDR25 Mode

see Figure 6-80
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMC0_CLK 50 MHz
SDR255 tc(clk) Cycle time, MMC0_CLK 20 ns
SDR256 tw(clkH) Pulse duration, MMC0_CLK high 9.2 ns
SDR257 tw(clkL) Pulse duration, MMC0_CLK low 9.2 ns
SDR258 td(clkL-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 2.4 8.1 ns
SDR259 td(clkL-dV) Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition 2.4 8.1 ns

SDR255

SDR256 SDR257

MMC[x]_CLK

SDR258 SDR258

MMC[x]_CMD

SDR259 SDR259

MMC[x]_DAT[3:0]

Figure 6-80. MMC0 – UHS-I SDR25 – Transmit Mode

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6.9.5.18.1.8 UHS–I SDR50 Mode

Table 6-96 and Figure 6-81 presents switching characteristics for MMC0 – UHS-I SDR50 Mode.
Table 6-96. Switching Characteristics for MMC0 – UHS-I SDR50 Mode
see Figure 6-81
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMC0_CLK 100 MHz
SDR505 tc(clk) Cycle time, MMC0_CLK 10 ns
SDR506 tw(clkH) Pulse duration, MMC0_CLK high 4.45 ns
SDR507 tw(clkL) Pulse duration, MMC0_CLK low 4.45 ns
SDR508 td(clkL-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 1.2 6.35 ns
SDR509 td(clkL-dV) Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition 1.2 6.35 ns

SDR505

SDR506 SDR507

MMC[x]_CLK

SDR508 SDR508

MMC[x]_CMD

SDR509 SDR509

MMC[x]_DAT[3:0]

Figure 6-81. MMC0 – UHS-I SDR50 – Transmit Mode

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6.9.5.18.1.9 UHS–I DDR50 Mode

Table 6-97 and Figure 6-82 present switching characteristics for MMC0 – UHS-I DDR50 Mode.
Table 6-97. Switching Characteristics for MMC0 – UHS-I DDR50 Mode
see Figure 6-82
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMC0_CLK 50 MHz
DDR505 tc(clk) Cycle time, MMC0_CLK 20 ns
DDR506 tw(clkH) Pulse duration, MMC0_CLK high 9.2 ns
DDR507 tw(clkL) Pulse duration, MMC0_CLK low 9.2 ns
DDR508 td(clk-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 1.12 6.43 ns
DDR509 td(clk-dV) Delay time, MMC0_CLK transition to MMC0_DAT[3:0] transition 1.12 6.43 ns

DDR505
DDR506 DDR507
MMC[x]_CLK
DDR508
MMC[x]_CMD

DDR509 DDR509
MMC[x]_DAT[3:0]

Figure 6-82. MMC0 – UHS-I DDR50 – Transmit Mode

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6.9.5.18.1.10 UHS–I SDR104 Mode

Table 6-98 and Figure 6-83 present switching characteristics for MMC0 – UHS-I SDR104 Mode.
Table 6-98. Switching Characteristics for MMC0 – UHS-I SDR104 Mode
see Figure 6-83
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMC0_CLK 200 MHz
SDR1045 tc(clk) Cycle time, MMC0_CLK 5 ns
SDR1046 tw(clkH) Pulse duration, MMC0_CLK high 2.12 ns
SDR1047 tw(clkL) Pulse duration, MMC0_CLK low 2.12 ns
SDR1048 td(clkL-cmdV) Delay time, MMC0_CLK rising edge to MMC0_CMD transition 1.07 3.21 ns
SDR1049 td(clkL-dV) Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition 1.07 3.21 ns

SDR1045

SDR1046 SDR1047

MMC[x]_CLK

SDR1048 SDR1048

MMC[x]_CMD

SDR1049 SDR1049

MMC[x]_DAT[3:0]

Figure 6-83. MMC0 – UHS-I SDR104 – Transmit Mode

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6.9.5.18.2 MMC1/MMC2 - SD/SDIO Interface

MMC1/MMC2 interface is compliant with the SD Host Controller Standard Specification 4.10 and SD Physical
Layer Specification v3.01 as well as SDIO Specification v3.00 and it supports the following SD Card applications:
• Default speed
• High speed
• UHS–I SDR12
• UHS–I SDR25
• UHS–I SDR50
• UHS–I DDR50
• UHS–I SDR104
Table 6-99 presents the required DLL software configuration settings for MMC1/2 timing modes.
Table 6-99. MMC1/MMC2 DLL Delay Mapping for all Timing Modes
MMCSD1_SS_PHY_CTRL_4_REG/ MMCSD1_SS_PHY_CTRL_5_REG/
REGISTER NAME
MMCSD2_SS_PHY_CTRL_4_REG MMCSD2_SS_PHY_CTRL_5_REG
BIT FIELD [20] [15:12] [8] [4:0] [2:0]
BIT FIELD NAME OTAPDLYENA OTAPDLYSEL ITAPDLYENA ITAPDLYSEL CLKBUFSEL
INPUT INPUT DELAY
DELAY DELAY
MODE DESCRIPTION DELAY DELAY BUFFER
ENABLE VALUE
ENABLE VALUE DURATION
Default 4-bit PHY operating
0x1 0x0 0x1 0x0 0x7
Speed 3.3V, 25MHz
High 4-bit PHY operating
0x1 0x0 0x1 0x0 0x7
Speed 3.3V, 50MHz
UHS-I 4-bit PHY operating
0x1 0xF 0x1 0x0 0x7
SDR12 1.8V, 25MHz
UHS-I 4-bit PHY operating
0x1 0xF 0x1 0x0 0x7
SDR25 1.8V, 50MHz
UHS-I 4-bit PHY operating
0x1 0xC 0x1 Tuning(1) 0x7
SDR50 1.8V, 100MHz
UHS-I 4-bit PHY operating
0x1 0x9 0x1 Tuning(1) 0x7
DDR50 1.8V, 50MHz
UHS-I 4-bit PHY operating
0x1 0x6 0x1 Tuning(1) 0x7
SDR104 1.8V, 200MHz

(1) Tuning means this mode requires a tuning algorithm to be used for optimal input timing

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Table 6-100 presents timing conditions for MMC1.

Table 6-100. MMC1/MMC2 Timing Conditions
PARAMETER MIN MAX UNIT
Input Conditions
Default Speed
0.69 2.06 V/ns
High Speed
SRI Input slew rate UHS–I SDR12
0.34 1.34 V/ns
UHS–I SDR25
UHS–I DDR50 1 2 V/ns
Output Conditions
CL Output load capacitance All modes 1 10 pF
PCB Connectivity Requirements
UHS–I DDR50 239 1134 ps
td(Trace Delay) Propagation delay of each trace
All other modes 126 1386 ps
High Speed
8 ps
UHS–I SDR104
td(Trace Mismatch Propagation delay mismatch across all
Delay) traces UHS–I DDR50 20 ps
All other modes 100 ps

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6.9.5.18.2.1 Default Speed Mode

Table 6-101, Figure 6-84, Table 6-102, and Figure 6-85 present timing requirements and switching
characteristics for MMC1/MMC2 – Default Speed Mode.
Table 6-101. Timing Requirements for MMC1/MMC2 – Default Speed Mode
see Figure 6-84
NO. MIN MAX UNIT
DS1 tsu(cmdV-clkH) Setup time, MMCx_CMD valid before MMCx_CLK rising edge 2.15 ns
DS2 th(clkH-cmdV) Hold time, MMCx_CMD valid after MMCx_CLK rising edge 1.67 ns
DS3 tsu(dV-clkH) Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge 2.15 ns
DS4 th(clkH-dV) Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge 1.67 ns

MMC[x]_CLK

DS1 DS2

MMC[x]_CMD

DS3 DS4

MMC[x]_DAT[3:0]

Figure 6-84. MMC1/MMC2 – Default Speed – Receive Mode

Table 6-102. Switching Characteristics for MMC1/MMC2 – Default Speed Mode

see Figure 6-85
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMCx_CLK 25 MHz
DS5 tc(clk) Cycle time, MMCx_CLK 40 ns
DS6 tw(clkH) Pulse duration, MMCx_CLK high 18.7 ns
DS7 tw(clkL) Pulse duration, MMCx_CLK low 18.7 ns
DS8 td(clkL-cmdV) Delay time, MMCx_CLK falling edge to MMCx_CMD transition - 1.8 2.2 ns
DS9 td(clkL-dV) Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition - 1.8 2.2 ns

DS5

DS6 DS7

MMC[x]_CLK

D S8

MMC[x]_CMD

D S9

MMC[x]_DAT[3:0]

Figure 6-85. MMC1/MMC2 – Default Speed – Transmit Mode

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6.9.5.18.2.2 High Speed Mode

Table 6-103, Figure 6-86, Table 6-104, and Figure 6-87 present timing requirements and switching
characteristics for MMC1/MMC2 – High Speed Mode.
Table 6-103. Timing Requirements for MMC1/MMC2 – High Speed Mode
see Figure 6-86
NO. MIN MAX UNIT
HS1 tsu(cmdV-clkH) Setup time, MMCx_CMD valid before MMCx_CLK rising edge 2.24 ns
HS2 th(clkH-cmdV) Hold time, MMCx_CMD valid after MMCx_CLK rising edge 1.66 ns
HS3 tsu(dV-clkH) Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge 2.24 ns
HS4 th(clkH-dV) Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge 1.66 ns

MMC[x]_CLK

HS1 H S2

MMC[x]_CMD

HS3 H S4

MMC[x]_DAT[3:0]

Figure 6-86. MMC1/MMC2 – High Speed – Receive Mode

Table 6-104. Switching Characteristics for MMC1/MMC2 – High Speed Mode

see Figure 6-87
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMCx_CLK 50 MHz
HS5 tc(clk) Cycle time. MMCx_CLK 20 ns
HS6 tw(clkH) Pulse duration, MMCx_CLK high 9.2 ns
HS7 tw(clkL) Pulse duration, MMCx_CLK low 9.2 ns
HS8 td(clkL-cmdV) Delay time, MMCx_CLK falling edge to MMCx_CMD transition - 1.8 2.2 ns
HS9 td(clkL-dV) Delay time, MMCx_CLK falling edge to MMCx_DAT[3:0] transition - 1.8 2.2 ns

HS5

HS6 HS7

MMC[x]_CLK

H S8

MMC[x]_CMD

H S9

MMC[x]_DAT[3:0]

Figure 6-87. MMC1/MMC2 – High Speed – Transmit Mode

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6.9.5.18.2.3 UHS–I SDR12 Mode

Table 6-105, Figure 6-88, Table 6-106, and Figure 6-89 present timing requirements and switching
characteristics for MMC1/MMC2 – UHS-I SDR12 Mode.
Table 6-105. Timing Requirements for MMC1/MMC2 – UHS-I SDR12 Mode
see Figure 6-88
NO. MIN MAX UNIT
SDR121 tsu(cmdV-clkH) Setup time, MMCx_CMD valid before MMCx_CLK rising edge 4.2 ns
SDR122 th(clkH-cmdV) Hold time, MMCx_CMD valid after MMCx_CLK rising edge 0.87 ns
SDR123 tsu(dV-clkH) Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge 4.2 ns
SDR124 th(clkH-dV) Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge 0.87 ns

MMC[x]_CLK

SDR121 SDR122

MMC[x]_CMD

SDR123 SDR124

MMC[x]_DAT[3:0]

Figure 6-88. MMC1/MMC2 – UHS-I SDR12 – Receive Mode

Table 6-106. Switching Characteristics for MMC1/MMC2 – UHS-I SDR12 Mode

see Figure 6-89
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMCx_CLK 25 MHz
SDR125 tc(clk) Cycle time, MMCx_CLK 40 ns
SDR126 tw(clkH) Pulse duration, MMCx_CLK high 18.7 ns
SDR127 tw(clkL) Pulse duration, MMCx_CLK low 18.7 ns
SDR128 td(clkL-cmdV) Delay time, MMCx_CLK rising edge to MMCx_CMD transition 1.5 8.6 ns
SDR129 td(clkL-dV) Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition 1.5 8.6 ns

SDR125

SDR126 SDR127

MMC[x]_CLK

SDR128 SDR128

MMC[x]_CMD

SDR129 SDR129

MMC[x]_DAT[3:0]

Figure 6-89. MMC1/MMC2 – UHS-I SDR12 – Transmit Mode

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6.9.5.18.2.4 UHS–I SDR25 Mode

Table 6-107, Figure 6-90, Table 6-108, and Figure 6-91 present timing requirements and switching
characteristics for MMC1/MMC2 – UHS-I SDR25 Mode.
Table 6-107. Timing Requirements for MMC1/MMC2 – UHS-I SDR25 Mode
see Figure 6-90
NO. MIN MAX UNIT
SDR251 tsu(cmdV-clkH) Setup time, MMCx_CMD valid before MMCx_CLK rising edge 2.15 ns
SDR252 th(clkH-cmdV) Hold time, MMCx_CMD valid after MMCx_CLK rising edge 1.27 ns
SDR253 tsu(dV-clkH) Setup time, MMCx_DAT[3:0] valid before MMCx_CLK rising edge 2.15 ns
SDR254 th(clkH-dV) Hold time, MMCx_DAT[3:0] valid after MMCx_CLK rising edge 1.27 ns

MMC[x]_CLK

SDR251 SDR252

MMC[x]_CMD

SDR253 SDR254

MMC[x]_DAT[3:0]

Figure 6-90. MMC1/MMC2 – UHS-I SDR25 – Receive Mode

Table 6-108. Switching Characteristics for MMC1/MMC2 – UHS-I SDR25 Mode

see Figure 6-91
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMCx_CLK 50 MHz
SDR255 tc(clk) Cycle time, MMCx_CLK 20 ns
SDR256 tw(clkH) Pulse duration, MMCx_CLK high 9.2 ns
SDR257 tw(clkL) Pulse duration, MMCx_CLK low 9.2 ns
SDR258 td(clkL-cmdV) Delay time, MMCx_CLK rising edge to MMCx_CMD transition 2.4 8.1 ns
SDR259 td(clkL-dV) Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition 2.4 8.1 ns

SDR255

SDR256 SDR257

MMC[x]_CLK

SDR258 SDR258

MMC[x]_CMD

SDR259 SDR259

MMC[x]_DAT[3:0]

Figure 6-91. MMC1/MMC2 – UHS-I SDR25 – Transmit Mode

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6.9.5.18.2.5 UHS–I SDR50 Mode

Table 6-109 and Figure 6-92 presents switching characteristics for MMC1/MMC2 – UHS-I SDR50 Mode.
Table 6-109. Switching Characteristics for MMC1/MMC2 – UHS-I SDR50 Mode
see Figure 6-92
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMCx_CLK 100 MHz
SDR505 tc(clk) Cycle time, MMCx_CLK 10 ns
SDR506 tw(clkH) Pulse duration, MMCx_CLK high 4.45 ns
SDR507 tw(clkL) Pulse duration, MMCx_CLK low 4.45 ns
SDR508 td(clkL-cmdV) Delay time, MMCx_CLK rising edge to MMCx_CMD transition 1.2 6.35 ns
SDR509 td(clkL-dV) Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition 1.2 6.35 ns

SDR505

SDR506 SDR507

MMC[x]_CLK

SDR508 SDR508

MMC[x]_CMD

SDR509 SDR509

MMC[x]_DAT[3:0]

Figure 6-92. MMC1/MMC2 – UHS-I SDR50 – Transmit Mode

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6.9.5.18.2.6 UHS–I DDR50 Mode

Table 6-110 and Figure 6-93 present switching characteristics for MMC1/MMC2 – UHS-I DDR50 Mode.
Table 6-110. Switching Characteristics for MMC1/MMC2 – UHS-I DDR50 Mode
see Figure 6-93
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMCx_CLK 50 MHz
DDR505 tc(clk) Cycle time, MMCx_CLK 20 ns
DDR506 tw(clkH) Pulse duration, MMCx_CLK high 9.2 ns
DDR507 tw(clkL) Pulse duration, MMCx_CLK low 9.2 ns
DDR508 td(clk-cmdV) Delay time, MMCx_CLK rising edge to MMCx_CMD transition 1.12 6.43 ns
DDR509 td(clk-dV) Delay time, MMCx_CLK transition to MMCx_DAT[3:0] transition 1.12 6.43 ns

DDR505
DDR506 DDR507
MMC[x]_CLK
DDR508
MMC[x]_CMD

DDR509 DDR509
MMC[x]_DAT[3:0]

Figure 6-93. MMC1/MMC2 – UHS-I DDR50 – Transmit Mode

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6.9.5.18.2.7 UHS–I SDR104 Mode

Table 6-111 and Figure 6-94 present switching characteristics for MMC1/MMC2 – UHS-I SDR104 Mode.
Table 6-111. Switching Characteristics for MMC1/MMC2 – UHS-I SDR104 Mode
see Figure 6-94
NO. PARAMETER MIN MAX UNIT
fop(clk) Operating frequency, MMCx_CLK 200 MHz
SDR1045 tc(clk) Cycle time, MMCx_CLK 5 ns
SDR1046 tw(clkH) Pulse duration, MMCx_CLK high 2.12 ns
SDR1047 tw(clkL) Pulse duration, MMCx_CLK low 2.12 ns
SDR1048 td(clkL-cmdV) Delay time, MMCx_CLK rising edge to MMCx_CMD transition 1.07 3.21 ns
SDR1049 td(clkL-dV) Delay time, MMCx_CLK rising edge to MMCx_DAT[3:0] transition 1.07 3.21 ns

SDR1045

SDR1046 SDR1047

MMC[x]_CLK

SDR1048 SDR1048

MMC[x]_CMD

SDR1049 SDR1049

MMC[x]_DAT[3:0]

Figure 6-94. MMC1/MMC2 – UHS-I SDR104 – Transmit Mode

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6.9.5.19 OSPI
OSPI0 offers two data capture modes, PHY mode and Tap mode.
PHY mode uses an internal reference clock to transmit and receive data via a DLL based PHY, where each
reference clock cycle produces a single cycle of OSPI0_CLK for Single Data Rate (SDR) transfers or a half
cycle of OSPI0_CLK for Double Data Rate (DDR) transfers. PHY mode supports four clocking topologies
for the receive data capture clock. Internal PHY Loopback - uses the internal reference clock as the PHY
receive data capture clock. Internal Pad Loopback - uses OSPI0_LBCLKO looped back into the PHY from the
OSPI0_LBCLKO pin as the PHY receive data capture clock. External Board Loopback - uses OSPI0_LBCLKO
looped back into the PHY from the OSPI0_DQS pin as the PHY receive data capture clock. DQS - uses the DQS
output from the attached device as the PHY receive data capture clock. SDR transfers are not supported when
using the Internal Pad Loopback and DQS clocking topologies. DDR transfers are not supported when using the
Internal PHY Loopback or Internal Pad Loopback clocking topologies.
Tap mode uses an internal reference clock with selectable taps to adjusted data transmit and receive capture
delays relative to OSPI0_CLK, which is a divide by 4 of the internal reference clock for SDR transfers or a divide
by 8 of the internal reference clock for DDR transfers. Tap mode only supports one clocking topology for the
receive data capture clock. No Loopback - uses the internal reference clock as the Tap receive data capture
clock. This clocking topology supports a maximum internal reference clock rate of 200MHz, which produces an
OSPI0_CLK rate up to 50MHz for SDR mode or 25MHz for DDR mode.
For more information, see Octal Serial Peripheral Interface (OSPI) section in Peripherals chapter in the device
TRM.
For more details about features and additional description information on the device Octal Serial Peripheral
Interface, see the corresponding subsections within Signal Descriptions and Detailed Description sections.
Section 6.9.5.19.1 defines timing requirements and switching characteristics associated with PHY mode and
Section 6.9.5.19.2 defines timing requirements and switching characteristics associated with Tap mode.
Table 6-112 presents timing conditions for OSPI0.
Table 6-112. OSPI0 Timing Conditions
PARAMETER MODE MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 1 6 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 3 10 pF
PCB CONNECTIVITY REQUIREMENTS
No Loopback
Propagation delay of OSPI0_CLK trace Internal PHY Loopback 450 ps
Internal Pad Loopback
td(Trace Delay)
Propagation delay of OSPI0_LBCLKO
External Board Loopback 2L(1) - 30 2L(1) + 30 ps
trace
Propagation delay of OSPI0_DQS trace DQS L(1) - 30 L(1) + 30 ps
Propagation delay mismatch of
td(Trace Mismatch
OSPI0_D[7:0] and OSPI0_CSn[3:0] All modes 60 ps
Delay)
relative to OSPI0_CLK

(1) L = Propagation delay of OSPI0_CLK trace

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6.9.5.19.1 OSPI0 PHY Mode

6.9.5.19.1.1 OSPI0 With PHY Data Training

Read and write data valid windows will shift due to variation in process, voltage, temperature, and operating
frequency. A data training method may be implemented to dynamically configure optimal read and write timing.
Implementing data training enables proper operation across temperature with a specific process, voltage, and
frequency operating condition, while achieving a higher operating frequency.
Data transmit and receive timing parameters are not defined for the data training use case since they are
dynamically adjusted based on the operating condition.
Table 6-113 defines DLL delays required for OSPI0 with Data Training. Table 6-114, Figure 6-95, Figure 6-96,
Table 6-115, Figure 6-97, and Figure 6-98 present timing requirements and switching characteristics for OSPI0
with Data Training.
Table 6-113. OSPI0 DLL Delay Mapping for PHY Data Training
MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE
Transmit
All modes PHY_CONFIG_TX_DLL_DELAY_FLD (1)

Receive
All modes PHY_CONFIG_RX_DLL_DELAY_FLD (2)

(1) Transmit DLL delay value determined by training software

(2) Receive DLL delay value determined by training software
Table 6-114. OSPI0 Timing Requirements – PHY Data Training
see Figure 6-95, and Figure 6-96
NO. MODE MIN MAX UNIT
Setup time, OSPI0_D[7:0] valid before (1)
O15 tsu(D-LBCLK) DDR with DQS ns
active OSPI0_DQS edge
Hold time, OSPI0_D[7:0] valid after active (1)
O16 th(LBCLK-D) DDR with DQS ns
OSPI0_DQS edge
Setup time, OSPI0_D[7:0] valid before (1)
O21 tsu(D-LBCLK) SDR with External Board Loopback ns
active OSPI0_DQS edge
Hold time, OSPI0_D[7:0] valid after active (1)
O22 th(LBCLK-D) SDR with External Board Loopback ns
OSPI0_DQS edge
1.8V, DDR with DQS 1.6 ns
Data valid window (O15 + O16)
3.3V, DDR with DQS 2.2 ns
tDVW
1.8V, SDR with External Board Loopback 2.3 ns
Data valid window (O21 + O22)
3.3V, SDR with External Board Loopback 2.9 ns

(1) Minimum setup and hold time requirements for OSPI0_D[7:0] inputs are not defined when Data Training is used to find the optimum
data valid window. The tDVW parameter defines the minimum data invalid window required. This parameter is provided in lieu of
minimum setup and minimum hold times, where it must be used to check compatibility with the data valid window provided by an
attached device.

OSPI_DQS

O15 O16 O15 O16

OSPI_D[i:0]

OSPI_TIMING_04

Figure 6-95. OSPI0 Timing Requirements – PHY Data Training, DDR with DQS

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OSPI_DQS

O21 O22

OSPI_D[i:0]

OSPI_TIMING_06

Figure 6-96. OSPI0 Timing Requirements – PHY Data Training, SDR with External Board Loopback

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Table 6-115. OSPI Switching Characteristics – PHY Data Training

See Figure 6-97 and Figure 6-98
NO. PARAMETER MODE MIN MAX UNIT
1.8V, DDR 6.0 10 ns
O1
3.3V, DDR 7.5 10 ns
tc(CLK) Cycle time, OSPI0_CLK
1.8V, SDR 6.0 10 ns
O7
3.3V, SDR 7.5 10 ns
O2 DDR
tw(CLKL) Pulse duration, OSPI0_CLK low ((0.475P(1)) - 0.3) ns
O8 SDR
O3 DDR
tw(CLKH) Pulse duration, OSPI0_CLK high ((0.475P(1)) - 0.3) ns
O9 SDR
O4 DDR ((0.475P(1)) + ((0.525P(1)) +
Delay time, OSPI0_CSn[3:0] active edge
td(CSn-CLK) (0.975M(2)R(4)) + (1.025M(2)R(4)) + ns
O10 to OSPI0_CLK rising edge SDR (0.04TD(5)) - 1) (0.11TD(5)) + 1)
O5 DDR ((0.475P(1)) + ((0.525P(1)) +
Delay time, OSPI0_CLK rising edge to
td(CLK-CSn) (0.975N(3)R(4)) - (1.025N(3)R(4)) - ns
O11 OSPI0_CSn[3:0] inactive edge SDR (0.04TD(5)) - 1) (0.11TD(5)) + 1)
O6 Delay time, OSPI0_CLK active edge to DDR
td(CLK-D) (6) (6) ns
O12 OSPI0_D[7:0] transition SDR
Data invalid window (O6 Max - Min) DDR
tDIVW 1.6 ns
Data invalid window (O12 Max - Min) SDR

(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = reference clock cycle time in ns
(5) TD = PHY_CONFIG_TX_DLL_DELAY_FLD
(6) Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data
valid window. The tDIVW parameter defines the maximum data invalid window. This parameter is provided in lieu of minimum and
maximum delay times, where it must be used to check compatibility with the data valid window requirements of an attached device.

OSPI_CSn

O4 O3 O5

OSPI_CLK

O2
O6 O6
O1

OSPI_D[i:0]

OSPI_TIMING_01

Figure 6-97. OSPI0 Switching Characteristics – PHY DDR Data Training

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OSPI_CSn

O10 O7 O11

OSPI_CLK O9 O8

O12

OSPI_D[i:0]

OSPI_TIMING_02

Figure 6-98. OSPI0 Switching Characteristics – PHY SDR Data Training

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6.9.5.19.1.2 OSPI0 Without Data Training

Note
Timing parameters defined in this section are only applicable when data training is not implemented
and DLL delays are configured as described in Section 6.9.5.19.1.2.1 and Section 6.9.5.19.1.2.2.

6.9.5.19.1.2.1 OSPI0 PHY SDR Timing

Table 6-116 defines DLL delays required for OSPI0 PHY SDR Mode. Table 6-117, Figure 6-99, Figure 6-100,
Table 6-118, and Figure 6-101 present timing requirements and switching characteristics for OSPI0 PHY SDR
Mode.
Table 6-116. OSPI0 DLL Delay Mapping for PHY SDR Timing Modes
MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE
Transmit
All modes PHY_CONFIG_TX_DLL_DELAY_FLD, 0x0
Receive
All modes PHY_CONFIG_RX_DLL_DELAY_FLD 0x0

Table 6-117. OSPI0 Timing Requirements – PHY SDR Mode

see Figure 6-99 and Figure 6-100
NO. MODE MIN MAX UNIT

Setup time, OSPI0_D[7:0] valid before 1.8V, SDR with Internal PHY Loopback 4.8 ns
O19 tsu(D-CLK)
active OSPI0_CLK edge 3.3V, SDR with Internal PHY Loopback 5.19 ns

Hold time, OSPI0_D[7:0] valid after active 1.8V, SDR with Internal PHY Loopback -0.5 ns
O20 th(CLK-D)
OSPI0_CLK edge 3.3V, SDR with Internal PHY Loopback -0.5 ns

Setup time, OSPI0_D[7:0] valid before 1.8V, SDR with External Board Loopback 0.6 ns
O21 tsu(D-LBCLK)
active OSPI0_DQS edge 3.3V, SDR with External Board Loopback 0.9 ns

Hold time, OSPI0_D[7:0] valid after active 1.8V, SDR with External Board Loopback 1.7 ns
O22 th(LBCLK-D)
OSPI0_DQS edge 3.3V, SDR with External Board Loopback 2.0 ns

OSPI_CLK

O19 O20

OSPI_D[i:0]

OSPI_TIMING_05

Figure 6-99. OSPI0 Timing Requirements – PHY SDR with Internal PHY Loopback

OSPI_DQS

O21 O22

OSPI_D[i:0]

OSPI_TIMING_06

Figure 6-100. OSPI0 Timing Requirements – PHY SDR with External Board Loopback

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Table 6-118. OSPI0 Switching Characteristics – PHY SDR Mode

see Figure 6-101
NO. PARAMETER MODE MIN MAX UNIT
1.8V 7 ns
O7 tc(CLK) Cycle time, OSPI0_CLK
3.3V 6.03 ns
O8 tw(CLKL) Pulse duration, OSPI0_CLK low ((0.475P(1)) - 0.3) ns
O9 tw(CLKH) Pulse duration, OSPI0_CLK high ((0.475P(1)) - 0.3) ns
Delay time, OSPI0_CSn[3:0] active edge ((0.475P(1)) + ((0.525P(1)) +
O10 td(CSn-CLK) ns
to OSPI0_CLK rising edge (0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)
Delay time, OSPI0_CLK rising edge to ((0.475P(1)) + ((0.525P(1)) +
O11 td(CLK-CSn) ns
OSPI0_CSn[3:0] inactive edge (0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)

Delay time, OSPI0_CLK active edge to 1.8V -1.16 1.25 ns

O12 td(CLK-D)
OSPI0_D[7:0] transition 3.3V -1.33 1.51 ns

(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = reference clock cycle time in ns

OSPI_CSn

O10 O7 O11

OSPI_CLK O9 O8

O12

OSPI_D[i:0]

OSPI_TIMING_02

Figure 6-101. OSPI0 Switching Characteristics – PHY SDR

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6.9.5.19.1.2.2 OSPI0 PHY DDR Timing

Table 6-119 defines DLL delays required for OSPI0 PHY DDR Mode. Table 6-120, Figure 6-102, Table 6-121,
and Figure 6-103 present timing requirements and switching characteristics for OSPI0 PHY DDR Mode.
Table 6-119. OSPI0 DLL Delay Mapping for PHY DDR Timing Modes
MODE OSPI_PHY_CONFIGURATION_REG BIT FIELD DELAY VALUE
Transmit
1.8V PHY_CONFIG_TX_DLL_DELAY_FLD 0x46
3.3V PHY_CONFIG_TX_DLL_DELAY_FLD 0x43
Receive
1.8V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x15
3.3V, DQS PHY_CONFIG_RX_DLL_DELAY_FLD 0x3A
All other modes PHY_CONFIG_RX_DLL_DELAY_FLD 0x0

Table 6-120. OSPI0 Timing Requirements – PHY DDR Mode

see Figure 6-102
NO. MODE MIN MAX UNIT
1.8V, DDR with External Board Loopback 0.53 ns

Setup time, OSPI0_D[7:0] valid before 1.8V, DDR with DQS -0.46 ns
O15 tsu(D-LBCLK)
active OSPI0_DQS edge 3.3V, DDR with External Board Loopback 1.23 ns
3.3V, DDR with DQS -0.66 ns
1.8V, DDR with External Board Loopback 1.24(1) ns

Hold time, OSPI0_D[7:0] valid after active 1.8V, DDR with DQS 3.59 ns
O16 th(LBCLK-D)
OSPI0_DQS edge 3.3V, DDR with External Board Loopback 1.44(1) ns
3.3V, DDR with DQS 7.92 ns

(1) This Hold time requirement is larger than the Hold time provided by a typical OSPI/QSPI/SPI device. Therefore, the trace length
between the SoC and attached OSPI/QSPI/SPI device must be sufficiently long enough to ensure that the Hold time is met at the SoC.
The length of the SoC's external loopback clock (OSPI0_LBCLKO to OSPI0_DQS) may need to be shortened to compensate.

OSPI_DQS

O15 O16 O15 O16

OSPI_D[i:0]

OSPI_TIMING_04

Figure 6-102. OSPI0 Timing Requirements – PHY DDR with External Board Loopback or DQS

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Table 6-121. OSPI0 Switching Characteristics – PHY DDR Mode

see Figure 6-103
NO. PARAMETER MODE MIN MAX UNIT
O1 tc(CLK) Cycle time, OSPI0_CLK 19 ns
O2 tw(CLKL) Pulse duration, OSPI0_CLK low ((0.475P(1)) - 0.3) ns
O3 tw(CLKH) Pulse duration, OSPI0_CLK high ((0.475P(1)) - 0.3) ns
Delay time, OSPI0_CSn[3:0] active edge ((0.475P(1))- ((0.525P(1))
-
O4 td(CSn-CLK) ns
to OSPI0_CLK rising edge (0.975M(2)R(4))) (1.025M(2)R(4)) + 7)
Delay time, OSPI0_CLK rising edge to ((0.475P(1)) + ((0.525P(1)) +
O5 td(CLK-CSn) ns
OSPI0_CSn[3:0] inactive edge (0.975N(3)R(4)) - 7) (1.025N(3)R(4)))

Delay time, OSPI0_CLK active edge to 1.8V -7.71 -1.56 ns

O6 td(CLK-D)
OSPI0_D[7:0] transition 3.3V -7.71 -1.56 ns

(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = reference clock cycle time in ns

OSPI_CSn

O4 O3 O5

OSPI_CLK

O2
O6 O6
O1

OSPI_D[i:0]

OSPI_TIMING_01

Figure 6-103. OSPI0 Switching Characteristics – PHY DDR

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6.9.5.19.2 OSPI0 Tap Mode

6.9.5.19.2.1 OSPI0 Tap SDR Timing

Table 6-122, Figure 6-104, Table 6-123, and Figure 6-105 present timing requirements and switching
characteristics for OSPI0 Tap SDR Mode.
Table 6-122. OSPI0 Timing Requirements – Tap SDR Mode
see Figure 6-104
NO. MODE MIN MAX UNIT
Setup time, OSPI0_D[7:0] valid before (15.4 -
O19 tsu(D-CLK) No Loopback ns
active OSPI0_CLK edge (0.975T(1)R(2)))
Hold time, OSPI0_D[7:0] valid after active (- 4.3 +
O20 th(CLK-D) No Loopback ns
OSPI0_CLK edge (0.975T(1)R(2)))

(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
(2) R = reference clock cycle time in ns

OSPI_CLK

O19 O20

OSPI_D[i:0]

OSPI_TIMING_05

Figure 6-104. OSPI0 Timing Requirements – Tap SDR, No Loopback

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Table 6-123. OSPI0 Switching Characteristics – Tap SDR Mode

see Figure 6-105
NO. PARAMETER MODE MIN MAX UNIT
O7 tc(CLK) Cycle time, OSPI0_CLK 20 ns
O8 tw(CLKL) Pulse duration, OSPI0_CLK low ((0.475P(1)) - 0.3) ns
O9 tw(CLKH) Pulse duration, OSPI0_CLK high ((0.475P(1)) - 0.3) ns
Delay time, OSPI0_CSn[3:0] active edge ((0.475P(1)) + ((0.525P(1)) +
O10 td(CSn-CLK) ns
to OSPI0_CLK rising edge (0.975M(2)R(4)) - 1) (1.025M(2)R(4)) + 1)
Delay time, OSPI0_CLK rising edge to ((0.475P(1)) + ((0.525P(1)) +
O11 td(CLK-CSn) ns
OSPI0_CSn[3:0] inactive edge (0.975N(3)R(4)) - 1) (1.025N(3)R(4)) + 1)
Delay time, OSPI0_CLK active edge to
O12 td(CLK-D) - 4.25 7.25 ns
OSPI0_D[7:0] transition

(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) R = reference clock cycle time in ns

OSPI_CSn

O10 O7 O11

OSPI_CLK O9 O8

O12

OSPI_D[i:0]

OSPI_TIMING_02

Figure 6-105. OSPI0 Switching Characteristics – Tap SDR, No Loopback

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6.9.5.19.2.2 OSPI0 Tap DDR Timing

Table 6-124, Figure 6-106, Table 6-125, and Figure 6-107 present timing requirements and switching
characteristics for OSPI0 Tap DDR Mode.
Table 6-124. OSPI0 Timing Requirements – Tap DDR Mode
see Figure 6-106
NO. MODE MIN MAX UNIT
Setup time, OSPI0_D[7:0] valid before (17.04 -
O13 tsu(D-CLK) No Loopback ns
active OSPI0_CLK edge (0.975T(1)R(2)))
Hold time, OSPI0_D[7:0] valid after active (- 3.16 +
O14 th(CLK-D) No Loopback ns
OSPI0_CLK edge (0.975T(1)R(2)))

(1) T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]
(2) R = reference clock cycle time in ns

OSPI_CLK

O13 O14 O13 O14

OSPI_D[i:0]

OSPI_TIMING_03

Figure 6-106. OSPI0 Timing Requirements – Tap DDR, No Loopback

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Table 6-125. OSPI0 Switching Characteristics – Tap DDR Mode

see Figure 6-107
NO. PARAMETER MODE MIN MAX UNIT
O1 tc(CLK) Cycle time, OSPI0_CLK 40 ns
O2 tw(CLKL) Pulse duration, OSPI0_CLK low ((0.475P(1)) - 0.3) ns
O3 tw(CLKH) Pulse duration, OSPI0_CLK high ((0.475P(1)) - 0.3) ns
Delay time, OSPI0_CSn[3:0] active edge ((0.475P(1)) + ((0.525P(1))
+
O4 td(CSn-CLK) ns
to OSPI0_CLK rising edge ((0.975M(2)R(5)) - 1) ( 1.025M(2)R(5)) + 1)
Delay time, OSPI0_CLK rising edge to ((0.475P(1)) + ((0.525P(1)) +
O5 td(CLK-CSn) ns
OSPI0_CSn[3:0] inactive edge (0.975N(3)R(5)) - 1) (1.025N(3)R(5)) + 1)
(- 5.04 + (3.64 +
Delay time, OSPI0_CLK active edge to
O6 td(CLK-D) (0.975(T(4) + 1)R(5)) (1.025(T(4) + 1)R(5)) ns
OSPI0_D[7:0] transition
- (0.525P(1))) - (0.475P(1)))

(1) P = SCLK cycle time in ns = OSPI0_CLK cycle time in ns

(2) M = OSPI_DEV_DELAY_REG[D_INIT_FLD]
(3) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]
(4) T = OSPI_RD_DATA_CAPTURE_REG[DDR_READ_DELAY_FLD]
(5) R = reference clock cycle time in ns

OSPI_CSn

O4 O3 O5

OSPI_CLK

O2
O6 O6
O1

OSPI_D[i:0]

OSPI_TIMING_01

Figure 6-107. OSPI0 Switching Characteristics – Tap DDR, No Loopback

6.9.5.20 PCIe
The PCI-Express Subsystem is compliant with the PCIe® Base Specification, Revision 4.0. Refer to the
specification for timing details.
For more details about features and additional description information on the device Peripheral Component
Interconnect Express (PCIe), see the SERDES0 Signal Descriptions and the corresponding subsection within
Detailed Description.
For more information, see Peripheral Component Interconnect Express (PCIe) Subsystem section in Peripherals
chapter of the device TRM.

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6.9.5.21 Timers
For more details about features and additional description information on the device Timers, see the
corresponding subsections within Signal Descriptions and Detailed Description sections.
Table 6-126. Timer Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.5 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 2 10 pF

Table 6-127. Timer Input Timing Requirements

see Figure 6-108
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
T1 tw(TINPH) Pulse duration, high CAPTURE 4P(1)+ ns
2.5
T2 tw(TINPL) Pulse duration, low CAPTURE 4P(1)+ ns
2.5

(1) P = functional clock period in ns.

Table 6-128. Timer Output Switching Characteristics
see Figure 6-108
NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
T3 tw(TOUTH) Pulse duration, high PWM 4P(1)- ns
2.5
T4 tw(TOUTL) Pulse duration, low PWM 4P(1) - ns
2.5

(1) P = functional clock period in ns.

T1 T2

TIMER_IOx (inputs)

T3 T4

TIMER_IOx (outputs)

TIMER_01

Figure 6-108. Timer Timing Requirements and Switching Characteristics

For more information, see Timers section in Peripherals chapter in the device TRM.

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6.9.5.22 UART
For more details about features and additional description information on the device Universal Asynchronous
Receiver Transmitter, see the corresponding subsections within Signal Descriptions and Detailed Description
sections.
Table 6-129. UART Timing Conditions
PARAMETER MIN MAX UNIT
INPUT CONDITIONS
SRI Input slew rate 0.5 5 V/ns
OUTPUT CONDITIONS
CL Output load capacitance 1 30(1) pF

(1) This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the
load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall
times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,
it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the
device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point
where the minimum data valid time of the attached device is violated.
Table 6-130. UART Timing Requirements
see Figure 6-109
NO. PARAMETER DESCRIPTION MIN MAX UNIT
0.95U(1) 1.05U(1)
1 tw(RXD) Pulse width, receive data bit high or low (2) (2) ns

0.95U(1)
2 tw(RXDS) Pulse width, receive start bit low (2) ns

(1) U = UART baud time in ns = 1/programmed baud rate.

(2) This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.
Table 6-131. UART Switching Characteristics
see Figure 6-109
NO. PARAMETER DESCRIPTION MIN MAX UNIT
Programmable baud rate for Main Domain UARTs 12 Mbps
f(baud)
Programmable baud rate for MCU and WKUP Domain UARTs 3.7 Mbps
3 tw(TXD) Pulse width, transmit data bit high or low U(1) -2 U(1) +2 ns
4 tw(TXDS) Pulse width, transmit start bit low U(1) - 2 ns

(1) U = UART baud time in ns = 1/actual baud rate, where the actual baud rate is defined in the UART Baud Rate Settings table of the
device TRM.
2
1

Start
VIH
UARTi_RXD Bit
VIL
Data Bits

4
3
Start
UARTi_TXD Bit

Data Bits
UART_TIMING_01_RCVRVIHVIL

Figure 6-109. UART Timing Requirements and Switching Characteristics

For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter
in the device TRM.

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6.9.5.23 USB
The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the
specification for timing details.
For more details about features and additional description information on the device Universal Serial Bus
Subsystem (USB), see the corresponding subsections within Signal Descriptions and Detailed Description
sections.

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7 Detailed Description
7.1 Overview
The AM67x scalable processor family is based on the evolutionary Jacinto™ 7 architecture, targeted at Smart
Vision Camera and General Compute applications and built on extensive market knowledge accumulated over
a decade of TI’s leadership in the Vision processor market. The AM67x family is built for a broad set of
cost-sensitive high performance compute applications in factory automation, building automation, and other
markets.
Key features and benefits:
• Focus on innovation and fast development with Linux® and Android™ SDKs accompanied with real-time
functional safety and security SDKs.
• Address next wave of HMI designs with new generation of 3D GPU and 4K video acceleration.
• Enhance your design connectivity with an extensive set of automotive and high-speed IOs, including: 4x
CAN-FD, 3-port Gigabit Ethernet switch (two external ports) with TSN support, and two USB2.0 ports.
• Supports the latest cybersecurity requirements with the built-in Hardware Security Module (HSM).
• Provides intelligent features, such as: facial recognition and touchless HMI with Arm® Cortex®-A53 CPUs
and open-source AI software and tools
The AM67x processors comply with the AEC - Q100 automotive standard and support industrial-grade. ASIL-B
and SIL-2 functional safety requirements can be addressed using an integrated Arm Cortex-R5F core and
dedicated peripherals, which can all be isolated from the rest of the processor.

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8 Applications, Implementation, and Layout

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Device Connection and Layout Fundamentals

8.1.1 Power Supply
8.1.1.1 Power Distribution Network Implementation Guidance
The Sitara Processor Power Distribution Networks: Implementation and Analysis provides guidance for
successful implementation of the power distribution network. This includes PCB stackup guidance as well as
guidance for optimizing the selection and placement of the decoupling capacitors. TI only supports designs that
follow the board design guidelines contained in the application report.
8.1.2 External Oscillator
For more information about External Oscillators, see the Clock Specifications section.
8.1.3 JTAG, EMU, and TRACE
Texas Instruments supports a variety of eXtended Development System (XDS) JTAG controllers with various
debug capabilities beyond only JTAG support. A summary of this information is available in the XDS Target
Connection Guide.
For recommendations on JTAG, EMU, and TRACE routing, see the Emulation and Trace Headers Technical
Reference Manual
8.1.4 Unused Pins
For more information about Unused Pins, see Pin Connectivity Requirements .

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8.2 Peripheral- and Interface-Specific Design Information

8.2.1 LPDDR4 Board Design and Layout Guidelines
The goal of the Jacinto 7 DDR Board Design and Layout Guidelines is to make the LPDDR4 system
implementation straightforward for all designers. Requirements have been distilled down to a set of layout and
routing rules that allow designers to successfully implement a robust design for the topologies that TI supports.
TI only supports board designs using LPDDR4 memories that follow the guidelines in this document.

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8.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines

The following section details the PCB routing guidelines that must be observed when connecting OSPI, QSPI, or
SPI devices.
8.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
• The signal propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to
B) must be ≤ 450ps (~7cm as stripline or ~8cm as microstrip)
• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
• 50Ω PCB routing is recommended along with series terminations, as shown in Figure 8-1
• Propagation delays and matching:
– (A to B) ≤ 450ps
– (E to F, or F to E) = ((A to B) ± 60ps)

A B
R1

0 Ω*

OSPI/QSPI/SPI
OSPI[x]_CLK
Device Clock Input

OSPI[x]_LBCLKO

OSPI[x]_DQS OSPI Device DQS

E F

OSPI[x]_D[y], OSPI/QSPI/SPI
OSPI[x]_CSn[z] Device IO[y], CS#
OSPI_Board_01

* 0Ω resistor (R1), located as close as possible to the OSPI[x]_CLK pin, is placeholder for fine tuning, if needed.

Figure 8-1. OSPI Connectivity Schematic for No Loopback, Internal PHY Loopback, and Internal Pad
Loopback

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8.2.2.2 External Board Loopback

• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
• The OSPI[x]_LBCLKO output pin must be looped back to the OSPI[x]_DQS input pin
• The signal propagation delay of the OSPI[x]_LBCLKO pin to the OSPI[x]_DQS pin (C to D) must be
approximately twice the propagation delay of the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device
CLK pin (A to B)
• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
• 50Ω PCB routing is recommended along with series terminations, as shown in Figure 8-2
• Propagation delays and matching:
– (C to D) = 2 x ((A to B) ± 30ps), see the exception note below.
– (E to F, or F to E) = ((A to B) ± 60ps)

Note
The External Board Loopback hold time requirement (defined by parameter number O16 in the OSPI0
Timing Requirements - PHY DDR Mode section) may be larger than the hold time provided by a
typical OSPI/QSPI/SPI device. In this case, the propagation delay of OPSI[x]_LBCLKO pin to the
OSPI[x]_DQS pin (C to D) can be reduced to provide additional hold time.

A B
R1

0 Ω*

OSPI/QSPI/SPI
OSPI[x]_CLK
Device Clock Input

C
R1

0 Ω*

OSPI[x]_LBCLKO

OSPI[x]_DQS OSPI Device DQS

E F

OSPI[x]_D[y], OSPI/QSPI/SPI
OSPI[x]_CSn[z] Device IO[y], CS#
OSPI_Board_02

* 0Ω resistor (R1), located as close as possible to the OSPI[x]_CLK and OSPI[x]_LBCLKO pins, is a placeholder for fine tuning, if
needed.

Figure 8-2. OSPI Connectivity Schematic for External Board Loopback

Product Folder Links: AM67 AM67A
AM67, AM67A
SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com

8.2.2.3 DQS (only available in Octal SPI devices)

• The OSPI[x]_CLK output pin must be connected to the CLK input pin of the attached OSPI/QSPI/SPI device
• The DQS pin of the attached OSPI/QSPI/SPI device must be connected to OSPI[x]_DQS pin
• The signal propagation delay from the attached OSPI/QSPI/SPI device DQS pin to the OSPI[x]_DQS pin (D
to C) must be approximately equal to the signal propagation delay from the OSPI[x]_CLK pin to the attached
OSPI/QSPI/SPI device CLK pin (A to B)
• The signal propagation delay of each OSPI[x]_D[y] and OSPI[x]_CSn[z] pin to the corresponding attached
OSPI/QSPI/SPI device data and control pin (E to F, or F to E) must be approximately equal to the signal
propagation delay from the OSPI[x]_CLK pin to the attached OSPI/QSPI/SPI device CLK pin (A to B)
• 50Ω PCB routing is recommended along with series terminations, as shown in Figure 8-3
• Propagation delays and matching:
– (D to C) = ((A to B) ± 30ps)
– (E to F, or F to E) = ((A to B) ± 60ps)

A B
R1

0 Ω*

OSPI/QSPI/SPI
OSPI[x]_CLK
Device Clock Input

OSPI[x]_LBCLKO

C D

OSPI[x]_DQS OSPI Device DQS

E F

OSPI[x]_D[y], OSPI/QSPI/SPI
OSPI[x]_CSn[z] Device IO[y], CS#
OSPI_Board_03

* 0Ω resistor (R1), located as close as possible to the OSPI[x]_CLK pin, is a placeholder for fine tuning, if needed.

Figure 8-3. OSPI Connectivity Schematic for DQS

Product Folder Links: AM67 AM67A

AM67, AM67A
www.ti.com SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

8.2.3 USB VBUS Design Guidelines

The USB 3.1 specification allows the VBUS voltage to be as high as 5.5V for normal operation, and as high as
20V when the Power Delivery addendum is supported. Some automotive applications require a max voltage to
be 30V.
The device requires the VBUS signal voltage be scaled down using an external resistor divider (as shown in
the Figure 8-4), which limits the voltage applied to the actual device pin (USB0_VBUS). The tolerance of these
external resistors should be equal to or less than 1%, and the leakage current of Zener diode at 5V should be
less than 100nA.

Device

USBn_VBUS

16.5 kΩ 3.48 kΩ
±1% ±1%
VBUS signal

10 kΩ
±1% 6.8V
(BZX84C6V8 or equivalent)

VSS VSS
J7ES_USB_VBUS_01

Figure 8-4. USB VBUS Detect Voltage Divider / Clamp Circuit

The USB0_VBUS pin can be considered to be fail-safe because the external circuit in Figure 8-4 limits the input
current to the actual device pin in a case where VBUS is applied while the device is powered off.
8.2.4 System Power Supply Monitor Design Guidelines
The VMON_VSYS pin provides a way to monitor a system power supply. This system power supply is typically
a single pre-regulated power source for the entire system and can be connected to the VMON_VSYS pin via
and external resistor divider circuit. This system supply is monitored by comparing the external voltage divider
output voltage to an internal voltage reference, where a power fail event is triggered when the voltage applied
to VMON_VSYS drops below the internal reference voltage. The actual system power supply voltage trip point
is determined by the system designer when selecting component values used to implement the external resistor
voltage divider circuit.
When designing the resistor divider circuit the designer must understand various factors which contribute to
variability in the system power supply monitor trip point. The first thing to consider is the initial accuracy of
the VMON_VSYS input threshold which has a nominal value of 0.45V, with a variation of ±3%. Precision
1% resistors with similar thermal coefficient are recommended for implementing the resistor voltage divider.
This minimizes variability contributed by resistor value tolerances. Input leakage current associated with
VMON_VSYS must also be considered since any current flowing into the pin creates a loading error on the
voltage divider output. The VMON_VSYS input leakage current can be in the range of 10nA to 2.5µA when
applying 0.45V.

Note
The resistor voltage divider shall be designed such that the output voltage never exceeds the
maximum value defined in the Recommended Operating Conditions section, during normal operating
conditions.

Figure 8-5 presents an example, where the system power supply is nominally 5V and the maximum trigger
threshold is 5V - 10%, or 4.5V.

Product Folder Links: AM67 AM67A
AM67, AM67A
SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com

For this example, the designer must understand which variables effect the maximum trigger threshold when
selecting resistor values. A device which has a VMON_VSYS input threshold of 0.45V + 3% needs to be
considered when trying to design a voltage divider that doesn’t trip until the system supply drops 10%. The effect
of resistor tolerance and input leakage also needs to be considered, but the contribution to the maximum trigger
point is not obvious. When selecting component values which produce a maximum trigger voltage, the system
designer must consider a condition where the value of R1 is 1% low and the value of R2 is 1% high combined
with a condition where input leakage current for the VMON_VSYS pin is 2.5µA. When implementing a resistor
divider where R1 = 4.81KΩ and R2 = 40.2KΩ, the result is a maximum trigger threshold of 4.517V.
Once component values have been selected to satisfy the maximum trigger voltage as described above, the
system designer can determine the minimum trigger voltage by calculating the applied voltage that produces an
output voltage of 0.45V - 3% when the value of R1 is 1% high and the value of R2 is 1% low, and the input
leakage current is 10nA, or zero. Using an input leakage of zero with the resistor values given above, the result
is a minimum trigger threshold of 4.013V.
This example demonstrates a system power supply voltage trip point that ranges from 4.013V to 4.517V.
Approximately 250mV of this range is introduced by VMON_VSYS input threshold accuracy of ±3%,
approximately 150 mV of this range is introduced by resistor tolerance of ±1%, and approximately 100mV of
this range is introduced by loading error when VMON_VSYS input leakage current is 2.5µA.
The resistor values selected in this example produces approximately 100µA of bias current through the resistor
divider when the system supply is 4.5V. The 100mV of loading error mentioned above can be reduced to about
10mV by increasing the bias current through the resistor divider to approximately 1mA. So resistor divider bias
current vs loading error is something the system designer needs to consider when selecting component values.
The system designer must also consider implementing a noise filter on the voltage divider output since
VMON_VSYS has minimum hysteresis and a high-bandwidth response to transients. This can be done by
installing a capacitor across R1 as shown in Figure 8-5. However, the system designer must determine the
response time of this filter based on system supply noise and expected response to transient events.

Device

VMON_VSYS

R2
VSYS
40.2 kΩ ±1% (System Power Supply)
R1 4.81 kΩ
C1
±1%
Value = Determined by system designer

VSS
SPRSP56_VMON_ER_MON_01

Figure 8-5. System Supply Monitor Voltage Divider Circuit

VMON_1P8_SOC pin provides a way to monitor external 1.8V power supplies. This pin must be connected
directly to their respective power source. An internal resistor divider with software control is implemented inside
the SoC for each of these pins. Software can program each internal resistor divider to create appropriate under
voltage and over voltage interrupts.
VMON_3P3_SOC pin provides a way to monitor external 3.3V power supplies. This pin must be connected
directly to their respective power source. An internal resistor divider with software control is implemented inside
the SoC for each of these pins. Software can program each internal resistor divider to create appropriate under
voltage and over voltage interrupts.

Product Folder Links: AM67 AM67A

AM67, AM67A
www.ti.com SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

8.2.5 High Speed Differential Signal Routing Guidance

The High Speed Interface Layout Guidelines provides guidance for successful routing of the high speed
differential signals. This includes PCB stackup and materials guidance as well as routing skew, length and
spacing limits. TI supports only designs that follow the board design guidelines contained in the application note.
8.2.6 Thermal Solution Guidance
The Thermal Design Guide for DSP and ARM Application Processors provides guidance for successful
implementation of a thermal solution for system designs containing this device. This document provides
background information on common terms and methods related to thermal solutions. TI only supports designs
that follow system design guidelines contained in the application note.

Product Folder Links: AM67 AM67A
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SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com

8.3 Clock Routing Guidelines

8.3.1 Oscillator Routing
When designing the printed-circuit board:
• Place all crystal circuit components as close as possible to the respective device pins.
• Route the crystal circuit traces on the outer layer of the PCB and minimize trace lengths to reduce parasitic
capacitance and minimize crosstalk from other signals.
• Place a continuous ground plane on the adjacent layer of the PCB such that it is under all crystal circuit
components and crystal circuit traces.
• Route a ground guard around the crystal circuit components to shield it from any adjacent signals routed on
the same layer as the crystal circuit traces. Insert multiple vias to stitch down the ground guard such that it
does not have any unterminated stubs.
• Route a ground guard between the MCU_OSC0_XI and MCU_OSC0_XO signals to shield the
MCU_OSC0_XI signal from the MCU_OSC0_X0 signal. Insert multiple vias to stitch down the ground guard
such that it does not have any unterminated stubs.
• Connect all crystal circuit ground connections and ground guard connections directly to the adjacent layer
ground plane, and the device VSS ground plane if they are implemented separately on different layers of the
PCB.

Note
Implementing a ground guard between the MCU_OSC0_XI and MCU_OSC0_XO signals is critical
to minimize shunt capacitance between the two signals. Routing these two signals adjacent to each
other without a ground guard between them will effectively reduce the gain of the oscillator amplifier,
which reduces its ability to start oscillation.

GND vias

Device

GND plane MCU_OSC0_XI

Cap
Crystal

Cap

GND guard
MCU_OSC0_XO

GND vias
Figure 8-6. MCU_OSC0 PCB requirements

Product Folder Links: AM67 AM67A

AM67, AM67A
www.ti.com SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

9 Device and Documentation Support

9.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix) (for
example, AM67xTBD). Texas Instruments recommends two of three possible prefix designators for its support
tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development from engineering
prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:

X Experimental device that is not necessarily representative of the final device's electrical specifications and
may not use production assembly flow.
P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical
specifications.
null Production version of the silicon die that is fully qualified.

Support tool development evolutionary flow:

TMDX Development-support product that has not yet completed Texas Instruments internal qualification testing.
TMDS Fully-qualified development-support product.

X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
For orderable part numbers of AM67x devices in the AMWpackage type, see the Package Option Addendum of
this document, the TI website (ti.com), or contact your TI sales representative.

Product Folder Links: AM67 AM67A
AM67, AM67A
SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com

9.1.1 Standard Package Symbolization

Note
Some devices may have a cosmetic circular marking visible on the top of the device package which
results from the production test process. In addition, some devices may also show a color variation in
the package substrate which results from the substrate manufacturer. These differences are cosmetic
only with no reliability impact.

TI aBBBBB
BBrZfYt Q1

XXXXXXX
YYY PPP
A1
(PIN 1 INDICATOR)

Figure 9-1. Printed Device Reference

Product Folder Links: AM67 AM67A

AM67, AM67A
www.ti.com SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

9.1.2 Device Naming Convention

Table 9-1. Nomenclature Description
FIELD PARAMETER FIELD DESCRIPTION VALUE DESCRIPTION
X Prototype
Device evolution P Preproduction (production test flow, no reliability data)
a
stage(1)
BLANK
Production
(null)
J722S(2)
AM67A94
Base production part
BBBBBBB or BBBBBB AM67A74 For more P/N details, see Device Comparison
number
AM6754
AM6734
r Device Revision A SR 1.0
J
Z Device Speed Grade See Device Speed Grades table
K
f Features G Base, no additional Features
1 to 9 Secure with Dummy Key / No Functional Safety
Security / Functional
Y H to R Secure with Production Key / No Functional Safety
Safety
S to Z Secure with Production Key / Functional Safety
–40°C to 125°C - "125°C Industrial and Automotive" (see Recommended
t Temperature I
Operation Conditions)
BLANK Standard

Q1 Automotive Designator Meet AEC-Q100 qualification requirements, with exceptions as specified

Q1 in this document (data sheet).
Supports TJ = –40°C to 125°C
Varies
2D Barcode Optional 2D barcode
BLANK
XXXXXXX Lot Trace Code (LTC)
YYY Production Code, For TI use only
PPP Package Designator AMW AMW FCBGA (18mm × 18mm)
O Pin one designator

(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent
evolutionary stages of product development from engineering prototypes through fully qualified production devices.
Prototype devices are shipped against the following disclaimer:
“This product is still in development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of
merchantability of fitness for a specific purpose, of this device.
(2) J722S is the base part number for the preproduction superset device. Software should constrain the features used to match the
intended production device.

Note
BLANK in the symbol or part number is collapsed so there are no gaps between characters.

Product Folder Links: AM67 AM67A
AM67, AM67A
SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com

9.2 Tools and Software

The following Development Tools support development for TI's Embedded Processing platforms:
Development Tools
Code Composer Studio™ Integrated Development Environment Code Composer Studio (CCS) Integrated
Development Environment (IDE) is a development environment that supports TI's Microcontroller and Embedded
Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded
applications. The tool includes an optimizing C/C++ compiler, source code editor, project build environment,
debugger, profiler, and many other features. The intuitive IDE provides a single user interface taking you through
each step of the application development flow. Familiar tools and interfaces allow users to get started faster
than ever before. Code Composer Studio combines the advantages of the Eclipse software framework with
advanced embedded debug capabilities from TI resulting in a compelling feature-rich development environment
for embedded developers.
SysConfig-PinMux Tool The SysConfig-PinMux Tool is a software tool which provides a Graphical User
Interface for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for TI
Embedded Processor devices. The tool can be used to automatically calculate the optimal pinmux configuration
to satisfy entered system requirements. The tool generates output C header/code files that can be imported
into software development kits (SDKs) and used to configure customer's software to meet custom hardware
requirements. The Cloud-based SysConfig-PinMux Tool is also available.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized
distributor.
9.3 Documentation Support
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
The following documents describe the AM67x devices.
Technical Reference Manual
J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Technical Reference Manual: Details the
integration, the environment, the functional description, and the programming models for each peripheral and
subsystem in the AM67x family of devices.
Errata
J722S TDA4VEN TDA4AEN AM67 Processor Silicon Revision 1.0 Errata: Describes the known exceptions to
the functional specifications for the device.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
Android™ is a trademark of Google LLC.
Code Composer Studio™ and TI E2E™ are trademarks of Texas Instruments.
Arm®, Cortex®, and TrustZone® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or
elsewhere.
MIPI® is a registered trademark of Mobil Industry Processor Interface Alliance.
PCI-Express® is a registered trademark of PCI-SIG.
Secure Digital® and SD® are registered trademarks of SD Card Association.

Product Folder Links: AM67 AM67A

AM67, AM67A
www.ti.com SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

Linux® is a registered trademark of Linus Torvalds.

All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Revision History

Changes from March 22, 2024 to September 30, 2024 (from Revision * (March 2024) to
Revision A (September 2024)) Page
• Global: Changed the document product status from "Advance Information" to "Production Data"................... 1
• (Features): Added "Motion JPEG encode" feature.............................................................................................1
• (Features/Media and Data Storage): Updated/Changed the "… eMMC interface up to HS200 speed" to "… up
to HS400 speed".................................................................................................................................................1
• (Features): Updated/Changed the CSI2.0 bullet and added sub-bullets............................................................1
• (Applications): Add End Equipment (EE) ulinks to the Applications list..............................................................3
• (Functional Block Diagram): Added an additional ulink for the non-A AM67 TI Software Development Kit
(SDK).................................................................................................................................................................. 5
• (Functional Block Diagram): Added a "JPEG Encode" block to the Multimedia main block...............................5
• (Device Comparison): Added an additional ulink for the non-A AM67 TI Software Development Kit (SDK) to
the "To understand what device features are currently supported by TI Software Development Kits, …" Note.7
• (SDIO Electrical Characteristics): Changed VDDSHV5 power rail name, where applicable, used to define the
VIL/VILSS/VIH/VIHSS/VOL/VOH parameter values by referencing a generic power rail name (VDD), and added an
associated table note........................................................................................................................................90
• (Recommended Operating Conditions for OTP eFuse Programming): Changed the "VPP Slew Rate"
parameter name to "VPP Power-up Slew Rate" to clarify the limit associated with this parameter only applies
during power-up................................................................................................................................................93
• (Power-Up Sequencing): Added note to clarify power rails must decay below 300mv before initiating a new
power-up sequence.......................................................................................................................................... 98
• (Power-Down Sequencing): Added note to clarify power rails must decay below 300mv before initiating a new
power-up sequence........................................................................................................................................ 101
• (BOOTMODE Timing Requirements): Updated the description for parameters RST23 and RST24............. 104
• (MCU_OSC0 LVCMOS Digital Clock Source): Added the new MCU_OSC0 LVCMOS Digital Clock Source
Requirements table.........................................................................................................................................116
• (CPSW3G RGMII Timing Conditions): Added operating voltage conditions to the Input Slew Rate parameter
to allow a relaxed slew rate when operating at 1.8V...................................................................................... 128
• (I2C): Changed the maximum slew rate value from 0.8V/ns to 0.08V/ns and added "when operating at 3.3V"
to clarify the exception is not applicable to 1.8V operation.............................................................................164
• (MMC0 Timing Requirements – HS400 Mode): Changed the maximum values associated with parameters
HS4001, HS4002, HS4003, and HS4004 from 500 to 475............................................................................ 183
• (MMC0 Switching Characteristics – HS400 Mode): Replaced the Delay time parameters HS4008 and
HS4009 with Output setup and Output hold parameters HS4008, HS4009, HS40010, and HS40011.......... 183
• (eMMC in – HS400 Mode – Transmitter Mode): Updated the timing diagram to match the new definitions
associated with parameters HS4008, HS4009, HS40010, and HS40011...................................................... 183
• (Device Nomenclature): Updated/Changed the package type (designator) form "AMH" to "AMW" in the
orderable part numbers paragraph.................................................................................................................225

Product Folder Links: AM67 AM67A
AM67, AM67A
SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024 www.ti.com

• (Nomenclature Description): Updated/Changed the table to match the Standard Package Symbolization
image.............................................................................................................................................................. 227

Product Folder Links: AM67 AM67A

AM67, AM67A
www.ti.com SPRSPA3A – MARCH 2024 – REVISED SEPTEMBER 2024

11 Mechanical, Packaging, and Orderable Information

11.1 Packaging Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Product Folder Links: AM67 AM67A
PACKAGE OPTION ADDENDUM

www.ti.com 12-Dec-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

AM6734AKGHIAMWR ACTIVE FCBGA AMW 594 750 RoHS & Green Call TI Level-3-250C-168 HR -40 to 125 AM67 Samples
34AKGHI
AM6754AKGHIAMWR ACTIVE FCBGA AMW 594 750 RoHS & Green Call TI Level-3-250C-168 HR -40 to 125 AM67 Samples
54AKGHI
AM67A74AKGHIAMWR ACTIVE FCBGA AMW 594 750 RoHS & Green Call TI Level-3-250C-168 HR -40 to 125 AM67A Samples
74AKGHI
AM67A94AKGHIAMWR ACTIVE FCBGA AMW 594 750 RoHS & Green Call TI Level-3-250C-168 HR -40 to 125 AM67A Samples
94AKGHI
XAM6754AKGHIAMW ACTIVE FCBGA AMW 594 1 TBD Call TI Call TI -40 to 125 Samples

XAM67A94AKGHIAMW ACTIVE FCBGA AMW 594 1 TBD Call TI Call TI -40 to 125 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
PACKAGE OPTION ADDENDUM

www.ti.com 12-Dec-2024

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
PACKAGE OUTLINE
AMW0594A SCALE 0.900
FCBGA - 2.473 mm max height
BALL GRID ARRAY

18.1 A
B
17.9

BALL A1 CORNER

PIN 1 ID
18.1
17.9
( 13.6)
0.1 C
( 17.6)

( 11.6)

2.154
2.473 1.950 0.2 C
2.245
C

SEATING PLANE
0.357
TYP 0.15 C
0.257

16.9 TYP

0.65 TYP (0.55) TYP

PKG
(0.55) TYP

AG
AF
AE
AD
AC
AB
AA
Y
W
V
U
T
PKG R
P 16.9
N
M
L
TYP
K
J
H
G
F
E
D
C
B
A

0.45 1 2 3 4 5 6 7 8 9 10 12 14 16 18 20 22 24 26
594X NOTE 3 11 13 15 17 19 21 23 25 27
0.35 0.65 TYP
0.25 C A B
0.1 C
4229875/A 07/2023
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Ball diameter after reflow. Dimension is measured at the maximum solder ball diameter parallel to primary datum C.

www.ti.com
EXAMPLE BOARD LAYOUT
AMW0594A FCBGA - 2.473 mm max height
BALL GRID ARRAY

594X ( 0.35) (0.65) TYP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

(0.65) TYP A
B
C
D
E
F
G
H
J
K
L
M
N
PKG
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG

PKG

LAND PATTERN EXAMPLE

EXPOSED METAL SNOWN
SCALE:6X

0.07 MAX
( 0.35) 0.07 MIN METAL UNDER
METAL SOLDER MASK
EXPOSED METAL

SOLDER MASK EXPOSED METAL ( 0.35)

OPENING SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

4229875/A 07/2023

NOTES: (continued)

4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).

www.ti.com
EXAMPLE STENCIL DESIGN
AMW0594A FCBGA - 2.473 mm max height
BALL GRID ARRAY

594X ( 0.35) (0.65) TYP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

(0.65) TYP A
B
C
D
E
F
G
H
J
K
L
M
N
PKG
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG

PKG

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 6X

4229875/A 07/2023

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
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