Digital Logic Design Lab (EE-123L)

Lab Report # 07

Group No. ____

Submitted by:
Name: Reg No:
Name: Reg No:
Name: Reg No:
Name: Reg No:

Submitted to:

Engr. Awais Mehmood

Department of Computer Science (BS-CS) Air

University Aerospace and Aviation Campus
Kamra
 AIR UNIVERSITY, AEROSPACE &
AVIATION CAMPUS KAMRA
DEPARTMENT OF COMPUTER SCIENCE

DIGITAL LOGIC DESIGN LAB (EE-123L)

LAB NO # 07

LAB TITLE: Implementation of Multiplexer and Demultiplexer Circuits

LAB ASSESSMENT:
Student Names (CLO-1,PLO-5, (CLO-2,PLO-4, P2) (CLO-3,PLO-9, Total
P3) A2) Marks
(20)

Ability to use IT Ability Ability Individual and Obtained

Trainer and to to group participation Marks
results conduc investig
demonstration t ate the (05)
(05) experim results
ent (05) (05)

LAB REPORT ASSESSMENT:

ASSESSMENT OF (CLO-3, PLO-9, A2)

Performance Indicator Excellent Good Average Unsatisfactory

5 3-4 1-2 0

Experimental Results

Data Presentation

Total Marks: ______________ Obtained Marks: ______________ Instructor’s Signature:

 _________

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Implementation and Analysis of Multiplexer and Demultiplexer Circuits

OBJECTIVE
∙ Learn how multiplexers (MUX) and demultiplexer (DEMUX) control and route multiple
data signals efficiently in digital circuits.
∙ Gain practical experience in designing, wiring, and testing MUX and DEMUX circuits
using logic gates or ICs.

THEORY
MULTIPLEXER (MUX)
A multiplexer is a circuit with ‘2n’ inputs, ‘n’ number of selection lines and a single output.
Multiplexer is commonly known as MUX. Multiplexer is also known as selector because it
can freely select any input line and shows its result on output. Multiplexers used for digital
applications are called digital multiplexers. Mux’s basic operation is that it has select lines
which select which input will be connected to the output.

Types of Multiplexer
2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and
single outputs, i.e., Y. On the basis of the combination of inputs which are present at the
selection line S0, one of these 2 inputs will be connected to the output. The block diagram and
the truth table of the 2×1 multiplexer are given below.

Block Diagram (2x1)

Truth Table (2 x 1)
E A0 A1 S0 Y

0 X X X 0
 1 1 0 0 1

1 0 1 1 1

Boolean Expression
̅
�� = ��0 . ��0 + ��1. ��0

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Logic Circuit Diagram

4×1 Multiplexer
In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2 selection lines,
i.e., S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are
present at the selection lines S0 and S1, one of these 4 inputs are connected to the output. The
block diagram and the truth table of the 4×1 multiplexer are given below.

Block Diagram (4x1)

Truth Table (4 x 1)
E A0 A1 A2 A3 S1 S0 Y
 0 X X X X X X 0

1 1 0 0 0 0 0 1

1 0 1 0 0 0 1 1

1 0 0 1 0 1 0 1

1 0 0 0 1 1 1 1

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Boolean Expression

̅ ̅ ̅
�� = ��1 . ��0 . A0 + ��1 . ��0 .A1 + ��1. ��̅0 . A2 + ��1. ��0 .A3

Logic Circuit Diagram

8×1 Multiplexer
In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and
A7, 3 selection lines, i.e., S0, S1 and S2 and single output, i.e., Y. On the basis of the
combination of inputs that are present at the selection lines S0, S1, and S2, one of these 8
inputs are connected to the output. The block diagram and the truth table of the 8×1
multiplexer are given below:

Block Diagram (8x1)

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Truth Table (8 x 1)
E A0 A1 A2 A3 A4 A5 A6 A7 S0 S1 S2 Y

0 X X X X X X X X X X X 0

1 1 0 0 0 0 0 0 0 0 0 0 1

1 0 1 0 0 0 0 0 0 0 0 1 1

1 0 0 1 0 0 0 0 0 0 1 0 1

1 0 0 0 1 0 0 0 0 0 1 1 1

1 0 0 0 0 1 0 0 0 1 0 0 1

1 0 0 0 0 0 1 0 0 1 0 1 1

1 0 0 0 0 0 0 1 0 1 1 0 1

1 0 0 0 0 0 0 0 1 1 1 1 1

Boolean Expression

̅ ̅
. ��1 . ��2
̅̅
. ��0 + ��0
̅ ̅
. ��1 . ��2 . ��1 + ��0
̅̅
. ��1 . ��2
̅̅
. ��2 + ��0
̅ ̅
. ��1 . ��2 .��3 + ��0 . ��1 . ��2
 �� = ��0 ̅̅
̅̅ . ��4
̅
+ ��0 . ��1 . ��2. ��5 + . ��6 + ��0. ��1 . ��2
��0 . ��1 . ��2 .��7

Logic Circuit Diagram

P
a g e 6 | 13
8 x 1 Multiplexer On IT Trainer
When INH input of IC 4051 is at the level of "1", whatever is the selection inputs, outputs are at the
level of "0". INH control works as a authorization signal. C, B, A selection lines select the inputs to be
multiplied and applied to the output. When the INH input is at the level of "0" (authorization), the
information at the input selected according to the condition of C, B, A selection lines is transferred to
Y output.

Truth Table
Circuit diagram:

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Procedure:
∙ The circuit of the 8x1 multiplexer is shown in the diagram above, which is implemented on
the given IT-Trainer.
∙ All you need to use a 4051 with an additional data line along with LED’s (Logic-1)
available in IT-Trainer.
∙ IT-Trainer has following authorization pin ������ (it should be low) and �� must be
Active HIGH and connected to the output LEDs respectively.
∙ Three select lines A, B and C must be connected with data lines while 8 inputs D0-D7 are
 connected to data lines as input.
∙ The input in binary will be converted or matched to its equivalent output data either 1 or 0
can be witnessed from output LED.
∙ Implement the circuit as described and try the relevant lab tasks according to the lab.
DEMULTEPLEXER

The information given from the input is distributed to outputs according to input row. So that,
the information is distributed to outputs in the order in which it came. This order heads
towards the output according to the situation of selection edges. This is commonly known as
distributor because it distributes data coming from single input line.
Types of DE Multiplexer:
1×2 De-multiplexer
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1 selection lines,
i.e., S0, and single input, i.e., A. On the basis of the selection value, the input will be
connected to one of the outputs. The block diagram and the truth table of the 1×2 multiplexer
are given below.

Block Diagram (1x2)

Truth Table (1x2)

E A S Y0 Y1
0 X X 0 0
1 1 0 1 0
1 1 1 0 1

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Boolean Expression (1x2)

̅
1. Y0 = S . A
2. Y1 = S . A
Logic Circuit Diagram

1×4 De-multiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2, and Y3, 2 selection
lines, i.e., S0 and S1 and single input, i.e., A. On the basis of the combination of inputs which
are present at the selection lines S0 and S1, the input be connected to one of the outputs. The
block diagram and the truth table of the 1×4 multiplexer are given below.

Block Diagram (1x2)

Truth Table (1x4)

E A S1 S0 Y0 Y1 Y2 Y3
0 X X X 0 0 0 0
1 1 0 0 1 0 0 0
1 1 0 1 0 1 0 0
1 1 1 0 0 0 1 0
1 1 1 1 0 0 0 1

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Boolean Expression (1x4)
 ̅
1. Y0 = S1 . S0
̅̅
.A
̅
2. Y1 = ��1 . ��0. A
̅
3. Y2 = ��1. ��0 . A
4. Y3 = S1‫۔‬S0. A

Logic Circuit Diagram

1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6,
and Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the
combination of inputs which are present at the selection lines S0, S1 and S2, the input will be
connected to one of these outputs. The block diagram and the truth table of the 1×8
de-multiplexer are given below.

Block Diagram (1x8)

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Truth Table (1x8)
E A S0 S1 S2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 X X X X 0 0 0 0 0 0 0 0
1 1 0 0 0 1 0 0 0 0 0 0 0
1 1 0 0 1 0 1 0 0 0 0 0 0
1 1 0 1 0 0 0 1 0 0 0 0 0
1 1 0 1 1 0 0 0 1 0 0 0 0
1 1 1 0 0 0 0 0 0 1 0 0 0
1 1 1 0 1 0 0 0 0 0 1 0 0
1 1 1 1 0 0 0 0 0 0 0 1 0
1 1 1 1 1 0 0 0 0 0 0 0 1

Boolean Expression (1x8)

̅̅ ̅
. S1 . S2
1. Y0 = S0
̅̅
.A
̅̅ ̅
. S1 . S2 . A
2. Y1 = S0
 ̅̅
. S1. S2
3. Y2 = S0
̅̅
.A
̅
. S1. S2. A
4. Y3 = S0
̅
5. Y4 = S0 . S1 . S2
̅
.A
̅
6. Y5 = S0 . S1 . S2. A
̅
.A
7. Y6 = S0 . S1. S2
8. Y7 = S0 . S1 . S2 . A

Logic Circuit Diagram

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1 x 8 De Multiplexer On IT Trainer
Truth Table
Circuit diagram:

Procedure:
∙ The circuit of the 1x8 demultiplexer is shown in the diagram above, which is implemented
on the given IT-Trainer.
∙ IC-4051 this time will be used as a demultiplexer with only 1 input line. ∙ IT-Trainer has
following ������ must be Active LOW and �� connected to any input data lines for
HIGH.
∙ Three select lines A, B and C must be connected with data lines while 8 outputs D0-D7 are
connected to LEDs.
∙ Select lines serve the purpose to select any output pin to get the result of the given input Y. ∙
The input in binary will be converted or matched to its equivalent output data either 1 or 0
can be witnessed from output LED.
∙ Implement the circuit as described and try the relevant lab tasks according to the lab.

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LAB TASKS
Task 1:
Implement a 4×1 Multiplexer using AND gate IC (7408), OR gate IC (7432) and NOT gate
IC (7404), then verify its truth table.

Task 2:
Implement a 4×1 Multiplexer using the Advanced Digital Electronics IT Trainer and verify its
truth table.

Task 3:
Implement a 1x4 Demultiplexer using AND gate IC (7408) and NOT gate IC (7404), then
verify its truth table.

Task 4:
Implement a 1x4 Demultiplexer using the Advanced Digital Electronics IT Trainer and verify
its truth table.

Note: Display the output of the Multiplexer and Demultiplexer logic using Active High LEDs.

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