Sequential Logic Circuits All the digital systems designed and analyzed so far are based upon combinational logic where the Suibut levels at any instant of ime depend only upon the levels present a the inputs at that time. Such sees ere sald to be memoryless systems. However there are many applications in which digit elements, Inputs. ‘Output Figure (5. 1)shows the block diagram of a sequential circuit coeay {consists of a combinational circuit, which accepts digital signals from external inputs and from the outputs of memory elements connected in feedback path and generates. ‘signals for external outputs and for the inputs to memory element. Memory The Table (5. 1)the comparison between combinational and z ‘Sequential circuit. Figure-5.1 Block diagram ofa sequential circuit Table-5.1 Comparison ofcombinationaland sequential circuit Combinational Circuits ‘Sequential Circuits 1 The output vaiables at any instant of ime 1, The output variables at any instant of ime {depends only on the presentinput variables, ‘depends not only on the present input variables butalsoon the pasthistory ofthe system. 2 Theso cirauts do ot requte ary memory 2. To store the past history ofthe input varebes, element, hence called memoryless system. ‘memory unitis required. 3. Combinational circuits are faster. 3. Sequential circuits are slower, 4. They areeasytodesign. 4.__ They are comparatively harder todesign * The sequential cicuits are classified as synchronous sequential circuits and asynchronous sequential Ciitcuits depending on the timing of their signals. Publications. Scanned with CamScanneryr Ape east Sequential Logic Circults | 115 mn public Te eg 2 nie y synchronous Sequential Circuit + The change in input si k signals. ‘gnals can affect m ement upon activation of clock sigi + Themaximum operational g acer x Peed of clock depends on time delays involved. + Inthis circuit, memory elements are “clocked {lip-flops" + Itis easier to design, {tis generally “edge triggered" (i) Asynchronous Sequential Circuit * Thech a change a «abut signals can attect memory oloment at any instant of time . perausoote aoe Of clock, this circuit can ‘operate faster than synchronous circuit. . * Memory elements are either “unclocked fl * or tit - \e delay elements. + More difficult to design, eee ete ey | + _Itis generally "Level triggered, [NTE:Cock's aperiodic 5.1. Latches and Flip-Flops "4 Abasic memory cellis a circuit that cated flip-flop. The flip-flop is made. up of an assembly of logic gates. Even though a logic gate by | itself has no storage Capacly, several logic gates can be connected together in ways that permit | information to be stored. Flip-flops are the basic building blocks of most sequential circuit. + Aflip-flop, known more formal | ‘+ Flip flop is also called a binary or one. | Figure (5.2) shows the general symbol used for alip-flop, The flip-flop has two outputs, labelled as Qand @. The Qis the normal output of the flip-flop and Q is the inverted output. (| — Normal output —1 a [-— Inverted output t Figure-5.2 Generalsymbolofaflip-flop {nits simplest form, flip-flop is called a ‘Latch, since itlatches (or locks) data in it. In latch there is No facility to read its contents. They are temporary storage devices, ‘ideally suited for storing | information between processing units and input units. The main difference between alatch anda | {lip-tlop is in method used for changing their state, Latches are generally unclocked, | * The below Table (5.3) ists the basic difference between flip-flop and latch as: Table. .2. Comparison between fp-flopandlatch Vins anne SFB FIop Latches use level triggering Flip-flops use edge triggering, Asychronous inputs 2, Synchronous inputs t changes as per the ‘The output changes as per the |3. The output ) inputtilenabie|s gh. input only at triggering point. — es Scanned with CamScanner> atid MADE y, , it 116.| Electronics Engineering _¢ Digital Circuits ~—rsSy .s connection of NAND gates or NOR gates Me my 08: The flip-flop can also be realized by the or Sn eure (53) NNAND gates connected in feedback loop are A a A a Figure.3 Basiememoryelement Q= A= . G= AHA ‘AS we know, the two outputs @ and @ are always complement of each other. It can exist in two stay, [ogi b); where as in reset. Slate where, States Le. set and resehInetState, Qis HIGH ((6gie 1) and G isHIGH (logic 1) and Qis LOW (logic 0) For flip flop to act as amemary element it should retain thy information stored init. 3.1.1 Triggering " : J Triggering is used to initiate the ‘operation of latches or flip-flops. Its main Purpose is to synchronize latches or flipfops,Itis classified as: ] @ — Leveltriggering (ii) Edge triggering = * _ Inlevel tiggering, input signals attect the flip-flop only when TEE at logic ‘1" seed Dese pa e Postive level tggering Negative level triggering pe, pm fre SAL) Lerten os * _ Inedge triggering, input Signals affectthe fp pony. hevare bresent athe postive going o negative going edge of the cléck pubes fa) (b) Positive edge triggering Negative edge triggering Figure-$.4(b) Edgetriggering In level triggering circuit the output may change several times ina triggering circuit the output will change only once in a single clock, single clock, whereas in edge The S-RLatch * The simplest type of tip-lop is called a S-R latch. It can be constructed with two cross coupled NNAND gates or two cross-coupled NOR gates and the two inputs labeled Stor set and Aor reset. The two outputs are Q and G, * The $-Rlatch constructed using two cross coupled NAND gates is shown in Figure 3.5 (a). Note that the output of each gate is connected to one of the inputs of other gate. The latch works as per the truth table shown in Figure 5.5 (b) MADE EASY Publications Scanned with CamScannergE Elim ———_______semenunonecrots | 117 - s 1 oo) S|R]Q.4] Stato Olo * | Forbidden Oli} 4 | sot a 1) 0 oO Reset ro——| 1/1] 0, | Hot i (a) Logic diagram (b) Truth table : Figure-5.5 S-RLatchwith NAND gates The $-R latch with two cross-coupled NAND a . operates with both inputs normally at 1, unless the a state of the latch is changed. The applicatio N of '0' to the Sinput causes output Q to go to ‘1’, + putting the latch in the ‘Set’ state. When the $input goes back to’, the circuit remains in the set state. After Both inputs go back ot", we are allowed to change the state ofthe latch by placing a'0 inthe Rinput. The action causes the circuit to go to reset and return to ‘1’. The condition is avoided in NAND latch when both the inputs are ‘0 t the same time is called invalid or forbidden state. + Figure 5.6 (a) and (b) shows the logic diagram and the truth table for a NOR S-R latch. The operation of this latch is totally reverse of the operation of the NAND latch. R @ SPREE pon of ol a | Hat oO} 4] 0 | Reset : t}o] 1] set s 8 t [4] x |roidden 9 une a (a) Logic diagram (b) Truth table Figure-5.6 S-RlatchswitchNOR gates . fall the O's are replaced by 1's and 1's by O's in Figure 5.6 (b), we get the same truth table as that a ‘of NAND gate latch shown in Figure 5.5 (b). re Eo The following binary values were applied to the X and Y inputs of the NAND latch shown in the figure in the sequence indicated below: — X=0,¥=1; X=0,¥=0; Xe Y=t. x p The corresponding stable P, Q outputs will be (@)P=1,0 =1,Q=0 of P=1,Q=00rP=0,0=1 — ()P=1,Q 0,Q=1 of P=0,Q=10rP=0,Q=1 () P=1,0 1,Q=1 of P=1,Q=00rP=0,Q=1 y ° (2) P=1,Q=0; P=1,Q=1 or P=1,Q= Solution :(c) 4 given in the truth table of NAND-gate latch circult, we get Inputs Outputs Scanned with CamScannera. MADE ERs, its oh 118 | Electronics Engineering ® Digital Circul SAgy a ay NOR =" i WAND = '1' and for NOTE) 1nSAlaich both te gates are enabled (fr ed MAND = anion the gates are disable ; it provious stateand when both { Rats 3 ininvald (prohibited) stat. e 5.1.3 Clocked Flip-Flop and Clock Signal a * Digital systems can operate either Asynchronously or Sy ange ites determined, SA ‘+ Insynchronous system, the exact time at which any output can Saari Yn conmonty known as the “Clock signal’. The outputs can change sta 7 transition (also called edges). - an, Clock changes trom 0 to 1 -» Positive going transition ( Clock changes from 1 00 -» Negative going transition (NGT). Q}—o count @—f a count | . inputs. inputs 9 >| CLK JL 7a rea aj a Ake actvates Cle acvated byePcr byaNGT Figure-5.7 :Clocked Flip flop Clocked FFs have a clock input ie. typically labelled CLK, CK of CP. This s indicated bya smal) triangle on the CLK input. Uttmately we can say thatthe Contol inputs get the FF outputs ready to change. While the active transition at the CLK inpuls actually riggers the change ie. the control inputs control the (what state the output will go to); the CLK input determines the “When" Setup Time (t) “What {tis the time interval immediatel synchronous input has to be m: 'C manufacturers usually speci ly preceding the active transition of CLK si taintained at the proper level. ify the minimum setup time, (1, tin ‘Synchronous. ye ‘contro input ignal during which the CLK input Figure-5,7(a) Hold Time (,) {tis the time interval immediately followi ing the active transition of CLK signal during which the Synchronous input has to be maintained at the proper level * It should be minimum, * _ Mthis requirement is not met, the lip-lop will not trigger reliably, Scanned with CamScannerape EASY publications 514 clocked S-RFlip-Flop truth Table for S-R flip-flop by Hold ime Figure-5.7(b) ‘The Figure 5.8 | (a) shows the clocked S-R flip-flop. The circuit is similar to Sf two AND gates. The circuit responds to the positive edge of clock Taverter Figure-5.8 (o)Logicdiagram of -Rfipfop sequentialtogiccirevits | 119 Rlatch except clk signal and pulse to the inputs S&F. $ ; t a ra} | i i Q pa Clock] S | R | Qh. | State 1 oid 1] 0 Reset 1 }afo]4 Set a fa fa] x | tnvaiia flip-lop output '@' after the Characteristic Table of S-R Flip-flop Here, Q, represents the state of fip-o Figure-5.8 (b)TthtableforS-Rfip-lop p before applying the input application of input and clock. ts and Q, , , represents the state of -Q | Qnos State 0} 0 (Hold 1 1 Q, (Hold) a) Reset 1] 0 o} 1 ~ 1 1 o | x | Forbidden’ 1] x Invalid (a characteristctableof5-Rfip-op Scanned with CamScanner120 | Electronics Engineering # Digital Circuits Characteristic Equation of S-R Flip-flop The characteristic equations an algebric ex ofthe characteristic able. it specifies the value of next state of all terms of its present state and present excitation. To oblain the characteristic equation of S-R flip-flop the K-map { state ¢ in terms of its present state and inpuls is shown in Figure 5.8 (4). Qn = S+RQ, ppression for the binary information flip-flop in for the next ++ Characteristic equation of S-R flip-flop is. Excitation Table The truth table of flip-flop refers to the operation characteristic of the flip-flop, but in the designjy, ‘Sequential circuits, we often face the situations where the present state and the next state of the fp. is specified and we have to find out the input conditions that must prevail for the desired output cone, Thus, the table which lists the present state, the next state and the excitations of a flip-flop calleg y, excitation table of a flip-flop ie, the excitation table is a table which indicates the excitations required, take the flip-flop from the present state to the next state. Excitation table of S-R flip-flop: Figure 5.8 (e) shows the excitation table for S-R flip-flop. a [ar [ S| R of o fol|x o}4 1] 0 1/0 }o]4 1 1|xlo Figure-5.8 (e)ExcitationtableofS8fip-op The description for excitation table is as follows: Case-A: when, Q,=Oand Q,,,=0 For Therefore, the desired output Q,,, , = 0, when S= Oand A= ‘x’ where 'x' is a don't care. Case-B: when, Q,=Oand Q,,,=1 For s => Q,,;=0,=0 s => Q,,,=0 821; = Qy=1 S=1;R=1 = Q.iax Therefore, desired output Q,, , = 0, when Case-C: when, Q, = 1and Q,,4= For So, desired output Q,, Scanned with CamScannersy ADE ERS euentantgtecreute | 1.21 Case-D: when, Q,= and Q,,,=1 For 0 0 1 1 s s s 8 ‘The desired output Q,, , = 1, when R graphical symbol of S-R latch ° s ° o—fs af cpo— cP o—a> ° R a ° R a ° () Positive edge trigger (ll) Negative edge trigger Figure-s.8 (1) GrophicalsymbolofS-Rlatch «Disadvantages: Invalid states are present when both the inputs ‘S' and '" are made HIGH (logic 1). To avoid this difficulty we use J-K tlip-lop. 5.1.5 J-KFlip-Flop The J-K fip-lop is a refinement ofthe S-R fip-iop in which the indeterminate (invalid) state of the SR type is defined in the J-K type. Figure 5.9(a) shows the logic diagram of J+ flip-flop with data input J and K ANDed with @ and respectively to obtain S and Rinputs i. S=JG] and [R=KQ Truth Table of J-K Flip-flop Figure's.9(b) Publications Scanned with CamScanner122 | Electronics Engineering © Digital Circuits Characteristics Table of J-K Flip-flop JT KT @ [ener [State OP oF Oo | OT a etoia) Roset 7 1 2 Sot ° Toggle 1{ 1] 0 Figure-5.9 () Characterisictableof-Kflip-op Characteristic Equation of J-K Flip-flop Ka, Noort t0 Figure-5.9(4)K-mop +. Characteristic equations [ Ques = JQ, +KQ, Excitation Table of JK Flip-flop Q | Qe | Jy TK of o fo|x of 1 ]4]o 1] 0 |x }a4 +11|xlo Figure-5.9(e) Excitation table of Kp flop Case-A when, Q,=Oand Q,,,=0 condition can happen with either J = 0 and K = OorJ=OandK=1 [Characteristic table]. Therefore, the desired output Q,,, = 0is obtained when J = O and K = x (dont care) Case-B when, Q,=OandQ,,,=1 This can happen with either J= 1 and K=OorJ= tandK=1 (toggle condition). Therefore the desired output Q,,, , = 1 is obtained when, J= 1 and K= x. Case-C when, Q,= 1 and Q,, This can happen with either J= and K = 1 or J= 1 andK=1. Therefore, the desired output Q,,, , = Ois obtained when J=xand 0 Scanned with CamScannerMADE Ree case-D when, Q, = Tand Q, , , This condition can hap; Pen with either J= 0 and K=OorJ= 7 Thus, the desired output Q, = + is obtaineg wath 7 Ke aie - ha we Sequential Logie Circuits | 123 —____seaquentiattogiccireuits Graphical Symbol Figure-5.9(f) (Graphical symbolof kK fip-flop 5.1.6 DFlip-Flop * From the truth table of SR tip top its clear thatthe output of SA flip-flop is in unpredictable state wwhen Ihe inputs are same (ie. when S= A= 0 then Q= Halt and when SA 1; Q= invalid). Therefore in many practical applications, these input conditions are net, required. Thus the modified ‘S-R flip flop in which such conditions are avoided is known as Dflip flop, shown in Figure 5. 10 (a). * tis flip-lop with delay equal to exactly one cycle of CLK. + tis also called “data transmission flipiop" and "transparent latch’, | fr s | a | ouK | cux | a | R Figure-S.10 ()Logic diagram ofOfip-op | where, S=D] and [R=D] Truth Table of D Flip-flop | CLK Lana | o [x | a, | 1 }o} 0 | str ]4 | Figure-5.10 (b) Truth table of Dfip-lop Characteristic Table of D Flip-flop D | Q, |Q,.4| State 0 | 0 | 0 | Reset 0 | 1 | 0 | Reset +] 0] 1 | set +} 1 [1] set Flgure-5.10(c) Characteristic table ofDflp-flop MADE EASY —— Paes Scanned with CamScanner124 | Electronics Engineering Digital Circuits MADE ——$ Digital Cireults — The characteristic equation of Ditip-lop is 2, io ° Q,.4=0 1 Figure-5.10(d) K-map_ The excitation Table of D Flip-flop ee 0 0 0 0 1 1 1 0 oO +} [4 Figure-5.10 (e) Excitation table ofDfip-flop For a Dilip-flop, the next State is always equal to the D input and it is independent of the Therefore, Dmust be 0'if ,, ,has tobe 0, and t if Q, Graphical Symbol Present state +1 has to be 1 regardless ofthe value of a, a a G ax BF R kK apo 0 “ [S=D] ana [R=5] J=D] ang [k=B] Figure:.10(f) GraphicalsymbolofDfip-fop 3.1.7. T Flip-Flop Figure 5.11 (a) shows the logical diagram of Ttlip-lop. T flip-flop is a single input version of JK flip-flop and can be obtained trom J-K tlip-flop it Jand Kinputs are tied together, ‘Change’ state, * The designation ‘T’ comes from the ability ofthe flip-lop to ‘Toggle’ or cux—+—4 Figure-8.11 (a) Logie diagram Tip-lop Publications Scanned with CamScannermape EASY $$ + serumtnnetien | 425 ruth Table of TFlip-lop [ext 7 Ton 0 x Q, 1] 0 | @, 7+ Ho 1 1 Q, | togge Figure-5.11 (b) Truth table he Characteristic Table for TFlip-flop T [| aes o | 0 0 o | 4 1 1 0 1 4 1 0 Figure-5.11(¢) Characteristictable of T flip-flop ‘The characteristic equation of Ttlip-flop is eo 4 of |@ Q).1 = 70, +7Q,| 0F|Q,,,=T OQ Figure-5.11 (d) K-map Excitation Table of T Flip-flop ForaT flip-flop, when the input T= 1, the state: of the flip-flop is complemented and when of the flip-flop remains unchanged. Thus, to obtain the output Q,,,=Oor 1 when Q, O and to obtain the output Q, ,, = 1 or Ownen Q, = 1 oF Othe Tmust be 1. Therefore, the excitation table, T=0, the state or 1 Tmust be (aye Gnet fa TS 0 0 0 oO 1 1 1 0 1 1 1 o igures.11(e)ExctationtableofTMp-eP Graphical symbol Te uk LS. rigure-5.11 (9 Gaphclsymbal oT Mop Scanned with CamScanneri 1D ital Circuits 126 | Electronics Engineering Digital aU " hc ll AOA z Using .K fipsfopal ater fip-flops can be designed thus itis known as - -— uD or an] 5.2 Race Around Condition * The difficuty of both the inputs to be 't'in case of S-R of invalid te is or ‘nese byayy flop by using feedback connections. From output a iy ee s (970 5.9) Hone, siti iggered) J = K = 1 is not yel cs —— aot See (CLK) is applied. After a propagation deay tng ', through two NAND gates, the output will toggle to Q, = 1. Since this is feedback to the 'nputs, the cutPut will toggle back to , = Oafter another, delay of toa ery: q . * Thus. as long as the clock pulse is present (fe): the output will toggle at every Soaten ANC At the eng of the clock Pulse, the value of Q, is uncertain, This situation will continue as long as the Clock, Pulse width f,, is longer than the Propagation delay (t,,) of each NAND gate. Such Situation jg referred to asthe "race around condition®, SS en ti, ey it, Publica Figure-s.12 Wavetormetkfip op Thus, the “Race around condition’ willoccur when @ J=K=4 (i) Wren to 45) < boy (iif) When level trigger is applied. One way to avoid this problem is to Maintain toy < fogee) < T. A most practical Method for over ‘Coming this problem is use of the “Master slave configuration”, 5.2.1 Master-SlaveFlip-Flop 5 A°MESFF"is basically constructed trom 2 FFs (a MASTER anda * Onthe rising edge of CLK (ie, +ve edge CLK PULSE) the contolinputs are used to determine the Cutputof the “MASTER”. When the CLK goes LOW (i. -ve edge CLK PULSE), the stato of Master ‘s transferred to the “SLAVE", whose outputs are Qand Q. In the °M-S FF’, outputis fuly dependent upon the output of SLAVE-FF, MADE EASY Publeations Scanned with CamScanner ee