Baics of SystemVerilog
Baics of SystemVerilog
DATA TYPE
HARDWARE (SYTHESIZABLE) VARIABLE(SIMULATION) USER DEFINE(SYTHESIZABLE)
▪ Unpacked array: Dimension declared after identifier name, may or may not represent a continuous set of bits, like memory
logic [7:0] mem_array [0:15]; // 16 locations, 8-bit each
Packed = bit-wise storage, used for arithmetic 👉 Unpacked = element-wise storage (memory-style)
Limitations
o Not synthesizable (simulation only)
o No guaranteed ordering of elements
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Queues
Dynamic, ordered collection (FIFO/LIFO behavior)
Use .push_back(), .pop_front() for insertion/removal
Perfect for modeling transaction flows
▪ Unbounded Queue (int q[$])
Dynamic size: Grows/shrinks infinitely (limited only by memory).
No overflow risk: Always accepts new elements.
▪ Bounded Queue (int q[$:N])
Fixed maximum size: Limited to N elements (index 0:N).
Overflow protection: Rejects new pushes when full (no auto-resize).
int q[$];
q.push_back(10); // Enqueue
q.push_front(5); // Insert at front
int val = q.pop_front(); // Dequeue (FIFO)
Great for TB stimulus, scoreboard, packet queues
Blocks in SystemVerilog
▪ initial : work only onces to initialize the global signals or get data signals value,monitor the response
initial begin
$display("Simulation started!");
#10; // Delay for 10 time units
$finish; // End simulation
end
▪ always_comb : Automatic sensitivity list for combinational logic
always_comb begin
y = a & b;
end
No risk of missing signals like in Verilog's always @(*)
▪ always_ff : For sequential logic (flip-flops)
Why this matters? Separating ff and comb logic avoids race conditions and unintended latches.
always_latch begin
if (en)
q = d;
end
Use only when latch behavior is intentional
Use cautiously — latches are hard to synthesize, and can cause timing issues.
▪ Standard counter-based iteration • Execute a block N times (no counter) • Auto-iterates over arrays
▪ Use for fixed-size arrays or known
ranges • Ideal for fixed repetitions (e.g., clock • No manual index management
cycles)
for (int i = 0; i < 10; i++) begin
repeat (5) begin
int arr[4] = '{1, 2, 3, 4};
$display("Iteration %d", i); foreach (arr[i]) $display("arr[%d] =
$display("Repeating 5 times");
%d", i, arr[i]);
\ end end
Functions Tasks
Purpose: Compute and return a single value (like Purpose: Execute procedural code that may include timing
mathematical operations) controls and multiple outputs
▪ Must return a value using return (SystemVerilog) or by ▪ Can contain delays (#10), event waits (@posedge), and
assigning to the function name (Verilog) blocking/non-blocking assignments
▪ Cannot contain time delays (#, @, wait) ▪ Can call other tasks and functions
▪ Can call other functions but not tasks ▪ Do not return values directly (but can modify output
▪ Execute in zero simulation time arguments)
function [return_type] function_name ([inputs]); ▪ Can consume simulation time
// Statements task task_name ([input/output args]);
return value; // SystemVerilog style // Procedural statements
endfunction endtask
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