Chapter 5

5.1 Interfacing with i8086

• What and why is interfacing

• Types and techniques of I/O interfacing
• Programmable peripheral Interfaces (PPI)
 Why interfacing?
I/O Problems
Operational Functions
✓ Wide variety of peripherals
I/O module functions
✓ Delivering different amounts of data
• Control & Timing
• At different speeds
• CPU Communication
• In different formats
• Device Communication
✓ All slower than CPU and RAM
• Data Buffering
✓ Need I/O modules
• Error Detection
I/O interface Modules
I/O steps
✓ Interface to CPU and Memory
1. CPU checks I/O module device status
✓ Interface to one or more peripherals
2. I/O module returns status
3. If ready, CPU requests data transfer
External Devices
4. I/O module gets data from device
Human readable
5. I/O module transfers data to CPU
Screen, printer, keyboard
Types of IO Interfacing
Machine readable
• IO mapped /Isolated IO
Monitoring and control
• Memory mapped
Communication
I/O Techniques of interfacing
Modem
• Programmed IO interfacing
Network Interface Card (NIC)
• Interrupt driven IO interfacing
• Direct Memory Access (DMA) interfacing

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 THE IO INTERFACE CIRCUITS OF AN i8086-BASED
MICROCOMPUTER SYSTEM.
The input/output system of the microprocessor allows peripherals to provide data or receive
results of processing the data. This is done using I/O ports.
✓ 8088/8086 architecture implements independent memory and input/output address spaces
✓ Memory address space- 1,048,576 bytes long (1M-byte)—00000H-FFFFFH
✓ Input/output address space- 65,536 bytes long (64K-bytes)—0000H-FFFFH
✓ Input/output can be implemented in either the memory or I/O address space
✓ Each input/output address is called a port
✓ The 8086 microcomputers can employ two different types of input/output (I/O) interfacing:
• IO mapped/ Isolated IO.
• Memory-mapped IO.

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A) IO MAPPED / ISOLATED IO INTERFACING

• Using isolated I/O a microcomputer system, the I/O devices are treated separate from memory. i.e.
I/O locations are isolated from memory system in a separate address space.
• The part of the I/O address space from address 0000H through 00FFH is referred to as Page 0 as
shown in figure (2).
• Supports byte and word I/O ports.
• 64K independent byte-wide I/O ports.
• 32K independent aligned word-wide I/O ports .
• In PC, isolated I/O ports are used for controlling peripheral device .
• 8-bit port address access devices located on system board.
• 16-bit port access serial, parallel ports, video & disk drive.
• i8086 uses M/𝐼𝑂 control signal to select b/n memory and I/O devices.
• User can expand the memory to its full size.
• Data transferred between I/O and microprocessor must be access by IN/OUT instructions.

Advantages of isolated I/O

1. Complete memory address space available for use by memory
2. Special instructions have been provided in the instruction set of the 8086 to perform isolated
I/O operation. This instructions tailored to maximize performance
Disadvantage of Isolated I/O
• All inputs/outputs must take place between an I/O port and accumulator (AL or AX) register

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• The 8086 microprocessors that employ isolated I/O, using special input and output instructions together
with the I/O port addressing modes.
I/O Addressing: Two addressing modes
1) Immediate port address
- Can only be 1 byte immediate address
- Can only address ports 00H through FFH
2) Port address present in DX
- Can address all ports 0000h through FFFFH
- Can only use DX for port addresses
- Can only use AL,AX for port data
I/O Instructions: Two I/O instructions:
• Transfers information to an I/O device (OUT)
• Read information from an I/O device (IN)
o When data are transferred using IN/OUT instruction, I/O address (port number) appears on the address
bus.
o 8-bit fixed port appears on address bus A7-A0 with A15-A8 bits equal to 00000000b
o 16-bit variable port appears on address connection A15-A0
Instructions Meaning Format Operation Flag affected
mnemonic
IN Input direct IN Acc, Port (Acc) ← (Port) none
Input variable IN Acc, DX (Acc) ← (DX)
OUT Output direct OUT Port, Acc (Port) ← (Acc) none
Output variable OUT DX , Acc (DX) ← (Acc)
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 I/O Instructions…e.g.
IN AL, p8 ;Read from port p8 to AL
IN AX, p8 ;Read from port p8 to AX
IN AL, DX ;Read from port addressed by DX to AL
IN AX, DX ;Read from port addressed by DX to AX
OUT p8 , AL ;Output from AL into port p8
OUT p8 , AX ;Output from AX into port p8
OUT DX, AL ;Output from AL into port addressed by DX
• A simple shift register can be used to change a serial Port to parallel or vice versa
• Example: write a series of instructions that will output FFH to an output port located at address
B000H of the I/O address space.
Solution: MOV DX, B000H
MOV AL, FFH
OUT DX, AL
• Example: Data are to be read from two byte-wide input ports at addresses AAH and A9H and then
output as a word to a word-wide output port at address B000H. Write a series of instructions to
perform this input/output operation.
Solution: IN AL, AAH
MOV AH, AL
IN AL, A9H
MOV DX, B000H
OUT DX, AX

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CONFIGURATION OF i8086 FOR ISOLATED IO CIRCUITRY
• The way in which the MPU deals with input/output circuitry is similar to the way in which it
interfaces with memory circuitry.
• There is an I/O interface circuitry for minimum mode. This interface also use the signals ALE,
𝐵𝐻𝐿, M/𝐼𝑂, 𝑊𝑅, 𝑅𝐷, DT/ 𝑅ത and 𝐷𝐸𝑁
• There is an I/O interface circuitry for maximum mode. This interface uses the 8288 bus
controller.
• Through this I/O interface, the MPU can input or output data in bit, byte or word.
• Unlike the memory interface, just the 16 least significant lines of the address bus (A15
through A0) are used.
• The logic levels of signals A0 and 𝐵𝐻𝐿 determine whether data are input/ output for an odd-
addressed byte-wide port, even-addressed byte-wide port, or a word-wide port.

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Figure-3-(a) shows the isolated I/O interface of a minimum – mode

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fig-3-(b) show the maximum – mode 8086 – based microcomputer system.

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BYTE-WIDE INPUT AND OUTPUT PORTS USING ISOLATED I/O

Figure (8) shows a circuits diagram of a byte-wide input and output ports (8 bit) using isolated I/O for
an 8086 based microcomputer system. From this diagram there is four parts:
Demultiplexing IC:
• Two 74F373 octal latches are used to form a 16-bit address latch. These devices latch the
address A0 through A15 synchronously with the ALE pulse. The latched address outputs are labeled
A0L through A15L.
• Remember that address lines A16 through A19 are not involved in the I/O interface.
• Data bus transceiver buffer in 8086 system is implemented using 74F245 octal bus IC’s, where the
control inputs ‘DIR ’ and ‘𝐺’ҧ is used to control the data flow (An → Bn) or (Bn →An).
Decoder IC:
• A 74F138 (3 Line-to- 8 Line decoder) is used for decoder circuit. Address lines A4L-A15L are applied
to AND gate, output of AND gate and address line A0L provide two of the three enable inputs of
the 74F138 input/output address decoder.
The Latch IC :
• For output circuit we need to store the output data so we use latch, for this purpose 74F374 device
is selected.
• For Figure (8), the gate at the CLK input of 74F374 has its inputs P0 and WR .
The Buffer :
• Buffer is used with input ports. In figure (8) the 74F244 octal buffer is used to implement
• the port. The outputs of the buffer are applied to the data bus for input to the MPU. This buffer has
three-state outputs. For Figure (8), the gate at the G input of 74F244 has its inputs P7 and RD.
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Fig. (8): A byte-wide input and output ports using Isolated I/P for an 8086 based.
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INPUT/OUTPUT Device :
• The circuit in figure (8) has 8 LEDs attached to outputs O0 – O7 of output port 0. These LEDs represent
output device.
• Also, in figure (8) there is 8 switches attached to input I0 – I7 of input port 7. These switches
represent input device.
Example 1: For figure (8), what is the I/O address of a. Port 0 (P0) b. Port 7 (P7) Assume all
unused address bit are at logic 0.
Solution:
To enable ports P0–P7→74F138 decoder must be enabled → 𝐺2𝐵 𝐺2𝐴 G1 = 001
G1=1 →output of AND gate=1→A4L– A15L=111111111111
𝐺2𝐵=0 →A0L= 0
𝐺2𝐴=0 →IOM = 0

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Example 2:
For the circuit of figure (8), write an instruction sequence that inputs the byte
contents of input port 7 to the memory DS:A000H.
Solution: The address of Port P7 =FFFEH. The instruction sequence needed to input the byte is:
MOV DX, FFFEH
IN AL, DX
MOV [A000], AL

Example 3:
For the circuit of figure (8), write an instruction sequence that outputs contents of
memory location DS:8000H to output port 0.
Solution: The address of Port P0 =FFF0H. The instruction sequence needed to output the
contents of memory location DS:8000H to output port 0 is:
MOV DX, FFF0H
MOV AL, [8000]
OUT DX, AL

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Example. Blinking an LED at an O/P port with a delay loop
• The circuit in Figure 1 show how to attach a LED to output port O7 of parallel port 0. The port address
is FFF0H, and the LED corresponds to bit 7 of the byte of data that is written to port 0. The circuit use
74LS374 (edge clocked octal latch). For the LED to turn on, O7 must be switched to logic 0, and it will
remain on until this output is switched back to 1. The 74LS374 is not an inverting latch, therefore, to
make O7 logic 0, simply write 0 to that bit of the octal latch.

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Example 1: Write instruction sequence to make the LED (in Figure 1) blink.
Solution: we must write a program that first makes O7 logic 0 to turn on the LED, delays for a
short period of time, and then switches O7 back to 1 to turn off the LED. This piece of program
can run as a loop to make the LED continuously blink. This is done as follows:
Sequence of instructions needed to initialize0 7 to logic 0.
MOV DX, FFF0H ; Initialize address of port0
MOV AL, 00H ; Load data with bit 7 as logic 0
ON_OFF: OUT DX, AL ; Output the data to port 0

Delay for a short period of time so as to maintain the data written to the LED
MOV CX, FFFFH ; Load delay count of FFFFH
HERE: LOOP HERE ; Time delay loop

The value in bit 7 of AL is complemented to 1 and then a jump is performed to return to the
output operation that writes the data to the output port:
MOV DX, 8000h
XOR AL, 80H ; Complement bit 7 of AL
MOV AL, 00h
JMP ON_OFF ; Repeat to Output the new bit 7
ON_OFF:
OUT DX,AL
MOV CX,FFFFh
HERE:
LOOP HERE
XOR AL,80h
JMP ON_OFF
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B) MEMORY MAPPED I/O INTERFACING
• I/O devices can be placed in the memory address space of the microcomputer as well as in the
independent I/O address space. In this case, the MPU looks at the I/O port as though it is a storage
location in memory. For this reason, the method is known as memory-mapped I/O. i.e. A device is treated
as memory location and a part of the memory address space is dedicated to I/O devices
• For Example: (E0000H-E0FFFH) → 4096 memory addresses assigned to I/O ports
• E0000H, E0001H, and E0002H correspond to byte wide ports 0,1, and 2
• E0000H and E0001H correspond to word-wide port 0 at address E0000H
• When I/O is configured in this way, instructions that affect data in memory are used instead of the special
input/output instructions. This is an advantage in that many more instructions and addressing modes are
available to perform I/O operations. In addition, I/O transfers can now take place between an I/O port and
an internal register other than just AL or AX. However, this also leads to a disadvantage. That is, the
memory instructions tend to execute slower than those specifically designed for isolated I/O. Therefore, a
memory—mapped I/O routine may take longer to perform than an equivalent program using the
input/output instructions. Uses instructions that transfers data between microprocessor & memory.

Advantages of memory mapped I/O

1. Instructions that affect data in memory (MOV, ADD, AND, etc.) can be used to perform I/O operations
2. I/O transfers can take place between I/O port and any of the registers

Disadvantage of memory mapped I/O

1. Memory instructions perform slower
2. Part of the memory address space cannot be used to implement memory i.e. memory address space is
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For example, in Figure-6- the 4096 memory addresses in the range form E0000H through E0FFFH are
assigned to I/O devices.

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Differences between Isolated I/O and Memory Mapped I/O:

Isolated I/O Memory Mapped I/O

Isolated I/O uses separate memory space. Memory mapped I/O uses memory from the main
memory.
Limited instructions can be used. Those Any instruction which references to memory can be
are IN, OUT, INS, OUTS. used. (MOV, AND XCHG, SUB …….)
Faster because I/O instructions is Slower because memory instructions execute slower
specifically designed to run faster than than the special I/O instructions
memory instructions
The memory address space is not affected Part of the memory address space is lost
The addresses for Isolated I/O devices are Memory mapped I/O devices are treated as memory
called ports. locations on the memory map

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PPI (Programmable peripheral interfaces) IC
Several developed by Intel to ease design burden provide a complete I/O interface on a single chip
Examples of common I/O interface chips:
• 8255A Programmable Peripheral Interface (PPI)
• 8259 Programmable Interrupt Controller (PIC)
• 8253/4 Programmable Interval Timer (PIT)
• 8237 Programmable DMA Controller
• IBM PC/XT had these chips on system board
• Modern PCs have functionality included in system chipset

Interfacing with i8255

• I8255 Internal Architecture

• Working Modes Of i8255
• Control Word Of i8255 PPI
• BSR Mode Control Word
• Operation Of Different i8255 Modes
• Interfacing Examples Using i8255 PPI

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 i8255A-ic Pin Description
Download the datasheet for i8255 and refer to Pin diagram of 8255A
• The internal structure
• How to interface with the microprocessor
• how to control data transfer between the ports and the
microprocessor
• Details are available with examples on the 3rd manual
• It can be programmed to transfer data under various
conditions.
• It has 24 I/O pins.
• The function of i8255A is in two modes.
1. BSR mode
2. I/O mode
• Control word identify between the operation mode as:
✓ BSR mode
✓ IO mode:
• Mode 0
• Mode 1
• Mode 2

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 BLOCK
DIAGRAM
OF 8255A

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 CONTROL WORD FORMAT
• Control word is some times called command word
• It is stored in control register
• It is 8 bit length
• It configure the interface IC to suitable setting

Mode selection B
Mode selection A 0 mode 0
00 mode 0 1 mode 1
01 mode 1
1x mode 2

• To know in which mode the interface is working we need to know the value of Control word. Control
word is a part of control register in 8255 which specify an I/O function for each port. This is format of
control word 8255.
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If the most significant bit of control word or D7 is 1 then 8255 works in I/O mode else, if it’s value is 0 it
works in BSR mode.
A) IO mode -D7=1
I/O Mode – When MSB of the control register is one(1), i8255 works in Input-Output mode.it is further
divided into three categories.
Mode 0 –D6D5 =00 Simple or basic I/O mode:
• Port A, B and C can work either as input function or as output function.
• The outputs are latched but the inputs are not latched. It has interrupt handling capability.
Mode 1 –D6D5=01 Handshake or strobed I/O:
• In this either port A or B can work and port C bits are used to provide handshaking.
• The outputs as well as inputs are latched. It has interrupt handling capability.
• Before actual data transfer there is transmission of signal to match speed of CPU and printer.
• Example: When CPU wants to send data to slow peripheral device like printer, it will send handshaking
signal to printer to tell whether it is ready or not to transfer the data. When printer will be ready it will
send one acknowledgement to CPU then there will be transfer of data through data bus.

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THE FUNCTIONAL PULSES IN MODE 1 DATA TRANSFER TECHNIQUE

Strobe pulse:
A strobe pulse is supplied by one unit to indicate the other unit when the transfer has to occur.
Handshaking pulse:
A control signal is accompanied with each data being transmitted to indicate the presence of data in the
bus.
The receiving unit responds with another control signal to acknowledge receipt of the data.
This type of agreement b/n two independent unit called handshaking.
Busy pulse:
If previous task of data transfer is not accomplished this signal remains active to notify the other device
it is busy
DATA

Other
Device

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Mode 2 – Bidirectional I/O:
In this mode only port A will work, port B can either is in mode 0 or 1 and port C bits are used as
handshake signal. The outputs as well as inputs are latched. It has interrupt handling capability. The
remaining are port group definition
✓ D4 defines i/0 of protA
✓ D3 defines protC (upper)
✓ D2 defines mode 0/1 of protB
✓ D1 defines i/o of portB
✓ D0 defines portC (lower)
Control Register is as follows:

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B) Bit set reset (BSR) mode –
This mode is used to set or reset the bits of port C only, and selected when the most significant bit (D7) in
the control register is 0.
Control Register is as follows:

This mode affects only one bit of port C at a time because, as user set the bit, it remains set until and
unless user changes it. User needs to load the bit pattern in control register to change the bit.

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****8255 Interfacing with 8086 in I/O Mapped I/O Mode:

• The 8086 has four special instructions IN, INS, OUT, and OUTS to transfer data through the
input/output ports in I/O mapped I/O system.
• M/IO signal is always low when 8086 is executing these instructions. So M/IO signal is used to
generate separate addresses for, memory and input/output.
• Only 256 (28 ) I/O addresses can be generated when direct addressing method is used.
• By using indirect address method this range can be extended up to 65536 (216 ) addresses.

• Fig. on next slide shows the 8255 Interfacing with 8086 in I/O mapped I/O technique. Here, RD and
WR signals are activated when M/IO signal is low, indicating I/O bus cycle.
• Only lower data bus (D0 — D7) is used as 8255 is 8-bit device. Reset out signal from clock generator
is connected to the Reset signal of the 8255.
• In case of interrupt driven I/O INTR signal (PC3 or PC0) from 8255 is connected to INTR input of
8088.

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IO mapped/Isolated IO configuration:

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****8255 Interfacing with 8086 in Memory Mapped I/O:

• In this type of I/O interfacing, the 8086 uses 20 address lines to identify an I/O device; an I/O device is
connected as if it is a memory register.
• The 8086 uses same control signals and instructions to access I/O as those of memory.
• Fig. on thee next slide shows the 8255 Interfacing with 8086 in memory mapped I/O technique.
• Here RD and WR signals are activated when M/IO signal is high, indicating memory bus cycle.
Address lines A0 – A2 are used by 8255 for internal decoding.
• To get absolute address, all remaining address lines (A3 – A19) are used to decode the address for
8255. Other signal connections are same as in I/O mapped I/O.

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Memory mapped IO configuration

IO map:

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 EXERCISE
What is the address for the following 8255A Programmable peripheral interface? Include work and result:
Address of PORTA
PORTB
PORTC
CONTROL PORT

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Example:-
Interface an 8255 chip with 8086 to work as an I/O port. Initialize port A as output port, Port B as I/P
port and Port C as O/P port. Port A address should be 0740H. Write an ALP to sense switch positions
SW0–SW7 connected at port B. The sensed pattern is to be displayed on port A, to which 8 LED's are
connected, while port C lower displays number of on switches out of the total eight switches .

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 Problems
Problem 1:
write control word to configure port s input port in mode 0 and port B in mode 1 s output port
Solution:

The control word is 94H.

N.B D0 and D3 are low if port C is used as output or if unused.

Problem 2 :
A control word is given CW=CDH. Explain the condition of ports of 8255A
Solution:

D7=1; I/O mode

D6=1;D5=0; Port A is in mode 2.
D4=0; Port A is output port
D3=1; Port C(Upper) is input port.
D2=1; Port B is in mode 1.
D1=0; Port B is output Port.
D0=0; Port C(Lower) is input port.
Configure Port A in Mode 2. Port B as o/p in mode 1.
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Programming steps for interfacing with i8255
✓ Port address definition
✓ Control word address definition
✓ Defining control word(input-output port definition and mode
✓ Loading control word to control register
✓ Statements to receive input
✓ Statement to casting output

To communicate with peripherals through 8255 three steps are necessary:

• Determine the addresses of Port A, B, C and Control register according to Chip Select Logic and
the Address lines A0 and A1.
• Write a control word in control register.
• Write I/O instructions to communicate with peripherals through port A, B, C.

Programming steps
1. Define the address of each port and control register
2. Write a statement to load the control word
3. Then the body of your program will follow accordingly you will use the port connection
statement with DX then the statement with instruction IN or OUT to get to the input-output
register AL

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DATA SEGMENT
PORTA EQU 0740H
PORTB EQU 0742H
PORTC EQU 0744H ;PORT ADDRESS
COMD EQU 0746H ;COMMAND WORD
ENDS

CODE SEGMENT
MOV DX, COMD ;connecting to the control register
MOV AL, 82H ;loading the control word AL
OUT DX, AL ;loading AL value to the control register through DX

MOV AL, 11000000B ; loading to the io-register

MOV DX, PORTA ;connecting the port
OUT DX,AL ;oupting the value in AL to portA

START:
MOV DX, PORTB
IN AL, DX ;receiving the input from portB
;so you can put any logic any where but according to the steps
CODE ENDS
END
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Problem 1: Configure Port in Mode 2, Port B as O/P in mode 1

Control words including the don’t care will take different value: 1100 0100/1100 0101/1100
1100/1100 1101/1101 0100/1101 0101/1101 1100/1101 1101/1110 0100/1110 0101/1110
1100/1110 1101/1111 0100/1111 0101/1111 1100/1111 1101
Equivalently in hex: C4H/C5H/D4H/D5H/DCH/DDH/E4H/E5H/ECH/EDH/F4H/F5H/FCH/FDH

Problem 2: Write an8086 assembly language procedure to red an Ascii character from keyboarded via
port A of n 8255 PPI when Port C bit is strobed low assume base dress of 20h

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Problem 3 :
Write an 8086 assembly language procedure to send an ASCII character, stored in register AH, to print via
PORTB of an 8255 PPI when PORTC bit PC0 is strobed low after an active low acknowledge signal is
detected on PORTC bit PC5 from the printer. Assume a base address of 60H.
Solution:
PORTB EQU 61H
PORTC EQU 62H
CONTROL EQU 63H
PRINT PROC NEAR
MOV AL,88H
OUT CONTROL,AL
PRINT1:
IN AL,PORTC ; is Acknowledge PC5 low?
TEST AL,20H
JNZ PRINT1
MOV AL,AH ;send character
OUT PORTB,AL
MOV AL,FEH
OUT PORTC,AL ;strobe output PC0
RET
ENDP

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Problem 4: An 8086-8255 based microcomputer is required to drive an LED connected to bit 2 of port B
based on two switch inputs connected to bit 6 and 7 of por. If both switch re either high or low. LED will
turn on; otherwise, it will remain OFF. Assume base address of 60H. write an assembly language program
to accomplish this:
Solution:
DATA SEGMENT
PORTA EQU 60H
PORTB EQU 61H
CTRL EQU 63H
CODE SEGMENT
MOV AL, 11010000B
OUT CTRL ,AL
MAIN:
IN AL,PORTA
AND AL,11000000B
JPE LEDON ;(JPE=jump if parity even, p=1)
MOV AL,00H
OUT PORTB,AL;
JMP MAIN;
LEDON:
MOV AL,00000100B
OUT PORTB,AL
JMP MAIN
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ENDS
PROBLEM 5. Figure below shows i8255A interfaced with 8086 microprocessor. Perform the following
a) Identify the port address
b) Identify the mode 0 control word to configure Port A and Port Cupper as output ports and port B and
Port C lower as input ports.
c) Write the program to read the DIP switches and display the reading from Port B at Port A and from
Port C lower at Port C upper

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Solution:

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Solution of problem 5(c) program OR Solution of problem5(c) program
DATA SEGMENT
DATA SEGMENT PPICR EQU 00FBH
PPICR EQU 00FBH PPIC EQU 00FAH
PPIC EQU 00FAH PPIB EQU PPF9H
PPIB EQU PPF9H PPIA EQU 00F8
PPIA EQU 00F8 ENDS
ENDS CODE SEGMENT
CODE SEGMENT MOV AL,83H
MOV AL,83H OUT PPICR,AL
OUT PPICR,AL IN AL,PPIB
IN AL,PPIB OUT PPIA,AL
OUT PPIA,AL IN AL,PPIC
IN AL,PPIC MOV CL,04H
AND AL,0FH ROL,AL,CL
MOV CL,04H OUT PPIC,AL
ROL,AL,CL HLT
OUT PPIC,AL ENDS
HLT
ENDS
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Exercise 1
a) Determine control words when the ports of Intel 8255 are defined as follows:
Port A as an input port. Mode of the Port A is Mode 0.
Port B as an input port. Mode of the Port B is Mode 0.
Port C upper and C lower are input ports.
b) Determine the control word for the following configuration of the ports of Intel 8255 for
Mode 1 operation:
Port A is used as input and operation mode of Port A is Mode 1.
Port B can be used as output and operates in Mode 1.
PC6 and PC7 act as input.
c) Write down the port addresses of the three counters and the control word register. The
Chip Select signal is derived on the basis of A7 - A4 =1111 and A3 – A2 = 00. Also, draw the
interfacing diagram of Programmable Interval Timer 8254 with 8086. Assume suitable
address mapping.

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EXERCISE 2
Interface an 8255 chip with 8086 microprocessor to work as an IO ports which is shown below in. Initialize
port B as input port connected to the push buttons, port A as output port connected to 7 seg display. So
that the ASM code should make a process to display decimal number when a corresponding pushbutton is
pressed. Control word register address should be 00FEH,PPI A0 is connected to 8086 microprocessor A1,
PPI A1 is connected to 8086 microprocessor A2

7-seg DISPLAY
U3
AD[0..15] AD0 34 4
D0 PA0
AD1 33 3
U2 AD2 32
D1 PA1
2
AD0 D2 PA2
3 2 AD3 31 1
D0 Q0 D3 PA3
AD1 4 5 AD4 30 40
D1 Q1 D4 PA4
AD2 7 6 AD5 29 39
D2 Q2 D5 PA5
AD3 8 9 AD6 28 38
D3 Q3 D6 PA6
AD4 13 12 AD7
27 37
D4 Q4 D7 PA7
AD5 14 15
D5 Q5
AD6 17 16 5 18
D6 Q6 RD PB0
AD[0..15]

AD7 18 19 36 19
D7 Q7 WR PB1
9 20
A0 PB2
1 8 21
OE A1 PB3
11 35 22
LE RESET PB4
23
PB5
74HC373 6 24
U1 CS PB6
25
21 PB7
RESET AD[0..15]
22
READY A[16..19] 14
24 PC0
INTA/QS1 15
18 25 PC1
INTR ALE/QS0 16
31 34 PC2
HOLD/GT1 BHE 17
30 27 PC3
HLDA/GT0 DT/R/S1 13
23 26 PC4
TEST DEN/S2 12
17 32 PC5
NMI RD 11
33 29 PC6
MN/MX WR/LOCK 10
19 28 PC7
CLK M/IO/S0
8086
8255A
PUSH BUTTONS
i8086 microporcessor 8255A PPI
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8237 DMA Controller interface technique
• DMA is an input output technique used for high speed data transfer
• Data transfer between system memory and floppy disk
• The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA
signals.
• When an external device wants to take control of the system bus, it signals to the 8086 by switching
HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters the hold state.
• The 8237 works in two modes i.e., master and slave modes.
• In slave mode, the 8237 functions as an input/output device. In this mode the system buses arc
controlled by microprocessor and hence the microprocessor is connected to the system bus.
• In master mode 8237 becomes the bus master and hence the microprocessor is isolated from the system
bus. This isolation is done by AEN signal.
• In minimum configuration, 8237 DMA controller is used to transfer the data. The peripheral chips are
interface as normal 10 ports. Figure shows the interfacing of DMA controller with 8086.
• In minimum mode the HOLD and HLDA signals are used to bus arbitration and in maximum mode
configuration RQ_0/GT_0; and RQ_1/GT_1.

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• The 8237 outputs only 16-bit memory address but not the complete 20-bit address of 8086. To
store the remaining four address hits A_16—A_19 a separate page latch is required.
• The 8237 is not compatible with 8086 in its maximum mode configuration. This is because RQ/GT
is not compatible with HRQ and HLDA of 8237.
• So if 8086 is to be interfaced with DMA controller, then 8089 10 processor is required.
• The 8089 interfaces to the 8086's local multiplexed buses. It shares the bus buffers and system
controller of the host system. It is compatible with the RQ/GT signals of 8086 and outputs the
complete 20-bit address.

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DMA interfacing Block diagram

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Different data transfer modes of 8237 DMA controller:

The 8237 is in the idle cycle if there is no pending request or the 8237 is waiting for a request from one of
the DMA channels. Once a channel requests a DMA service, the 8237 sends the HOLD request to the CPU
using its HRQ pin. If the CPU acknowledges the hold request on HLDA, the 8237 enters an active cycle. In
the active cycle, the actual data transfer takes place in one of the following transfer modes as is
programmed.

1. Single Transfer Mode: In this mode, the device transfers only one byte per request.
• The word count is decremented and the address is decremented or incremented (depending on
programming) after each such transfer.
• The Terminal Count (TC) state is reached when the count becomes zero.
• For each transfer the DREQ must be active until the DACK is activated, in order to get recognized.
After TC the bus will be relinquished for the CPU.
• For a new DREQ to 8237 it will again activate the HRQ signal to the CPU and the HLDA signal from
the CPU will push the 8237 again into the single transfer mode.
• This mode is also called as 'cycle stealing'.
2. Block Transfer Mode: In this mode, the 8237 is activated by DREQ to continue the transfer until a TC is
reached, i.e. a block of data is transferred.
• The transfer cycle may be terminated due to EOP (either internal or external) which forces
Terminal Count (TC).
• The DREO needs to be activated only till the DACK signal is activated by the DMA controller.
Auto-initialization may be programmed in this mode.
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3. Demand Transfer Mode: In this mode, the device continues transfers until a TC is reached or an
external EOP is detected or the DREQ signal goes inactive. Thus a transfer may exhaust the capacity
of data transfer of an I/O device.
• After the I/O device is able to catch up the service may be re-established activating the DREQ
signal again. Only the EOP generated by TC or external EOP can cause the auto-initialization, and
only if it is programmed for.
4. Cascade Mode: In this mode, more than one 8237 can be connected together to provide more than
four DMA channels.
• The HRQ and HLDA signals from additional 8237s are connected with DREQ and DACK pins of a
channel of the host 8237 respectively.
• The priorities of the DMA requests may be preserved at each level.
• The first device is only used for prioritizing the additional devices (slave 8237s), and it does not
generate any address or control signal of its own.
• The host 8237 responds to DREQ generated by slaves and generates the DACK and the HRQ
signals to coordinate all the slaves. All other outputs of the host 8237 are disabled.
5. Memory to memory Transfer: To perform the transfer of a block of data from one set of memory
address to another one, this transfer mode is used.
• Programming the corresponding mode bit in the command word, sets the channel 0 and I to
operate as source and destination channels, respectively.
• The transfer is initialized by setting the DREQ0 using software commands.
• The 8237 sends HRQ (Hold Request) signal to the CPU as usual and when the HLDA signal is
activated by the CPU. the device starts operating in block transfer mode to read the data from
memory.
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• The channel 0 current address register acts as a source pointer.
• The byte read from the memory is stored in an internal temporary register of 8237.
• The channel 1 current address register acts as a destination pointer to write the data from the
temporary register to the destination memory location.
• The pointers are automatically incremented or decremented, depending upon the programming.
• The channel 1 word count register is used as a counter and is decremented after each transfer.
• When it reaches zero, a TC is generated, causing EOP to terminate the service.
• The 8237 also responds to external EOP signals to terminate the service.
• This feature may be used to scan a block of data for a byte. When a match is found the process may
be terminated using the external EOP.
• Under all these transfer modes, the 8237 carries out three basic transfers namely, write transfer, read
transfer and verify transfer.
• In write transfer, the 8237 reads from an I/O device and writes to memory under the control of IOR
and MEMW signals.
• In read transfer, the 8237 reads from memory and writes to an I/O device by activating the MEMR and
IOW signals.
• In verify transfers, the 8237 works in the same way as the read or write transfer but does not generate
any control signal.

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 8086 - Interfacing Some Important Points
Memory Interfacing
1. While interfacing memory to 8086 ensure that at least 4K of ROM is available in the beginning locations -
starting at 00000H - as IVT is stored in this location.
2. While interfacing memory to 8086 ensure that at least 4K of ROM is available in the last locations -
ending at location FFFFFH. This is due to the fact that on reset the first instruction is executed from
location FFFF0H.
3. The 2K restriction is because the smallest memory chip available is 2K. 2K E and 2K O adds up to 4K.
4. If you are designing an Embedded System it is okay to use incremental addressing but while designing a
general purpose system it is better to use absolute addressing.

I/O Interfacing
1. All I/O peripherals that are covered in this course are 8-bit so they have to be interfaced only to D0-D7 or
D8-D15 - not to both the buses.
2. If I/O device is connected to D0-D7 then only even addresses must be assigned.
3. If I/O device is connected to D8-D15 then only odd addresses must be assigned.
4. When using fixed addressing - then it is suffice to use Address lines A0-A7 for decoding and addressing.
5. When using variable addressing - then you need to use Address lines A0-A15 for decoding and
addressing.
6. With I/O mapped I/O IOR and IOW should be used for read and write.
7. If memory mapped I/O use MEMR and MEMW.
8. In case of memory mapped I/O you need to ensure that there is no clash between memory and I/O
address - for eg. address 01000H should not be assigned to both memory and I/O devices.
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8255 Interfacing

1. The ports of 8255 in an un-programmed state are input ports- this because if they are output in
unconfigured state and any input device is connected to it - the input device will also be generating an
output on the port lines and 8255 will also be producing an output. When two outputs are tied
together it results in the destruction one of /both the devices.
2. The output pins of 8255 cannot be used for powering-up devices - as they will not be able to supply
the required driving current.
3. When connecting motors/lamps/speakers etc.. to 8255 - check the current rating of 8255 and the
devices - in the case where 8255 is not able to supply the required driving current make use of
amplifiers such as 7406 (inverting) and 7407(non-inverting amplifiers. In the case of large current
requirements make use of transistors in a Darlington Pair configuration. Click on link below for a brief
description of Darlington pair transistors. Darlington Pair.
4. When interfacing Dc motors to 8255 - select appropriate H-Bridges according to motor specification.
5. H-bridges allows DC motors to run in both directions - you can look at this blog post to understand
how H-Bridges work. H-Bridge operation
6. Port A and Port B can be used only as 8-bit ports - so all pins of Port A/Port B have to be input or
output.
7. Port C can be used as 8-bit port, 4-bit port or as individual port bits in BSR.
8. When connecting AC powered devices to 8255 make use of a relay.
9. When Port A/Port B are programmed in Mode 1/Mode 2 Port C cannot function as normal I/O port.

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8253/8254 Interfacing

1. 8253 works at a maximum clock frequency of 2.6 MHz

2. 8253 does not support read back.
3. It is preferred that clock input to 8253/8254 is derived from the microprocessors clock.
4. As in case of 8255 the 8253 inputs cannot be directly connected to high power devices.
5. Do not connect output from 8253/8254 to 8255 and poll it to find whether it is high or low-
because that defeats the purpose of using a timer. It is better to use timing signals as Interrupts.

8259 Interfacing

1. 8259 has only two addressable - so the order in which the command words are written are important.
2. OCWs are always written after the ICWs.
3. SP/EN in case of single 8259 - must always be connected to Vcc.
4. Unless you are sure about how long an interrupt request will be held high - do not use level triggering.
5. Edge triggering is preferred.
6. Since 8086 is used Do of ICW1 will always be set and ICW4 will always have to be provided.
7. It is preferred that AEOI is not used as this may violate the interrupt priorities.
8. Do not use reserved vector numbers - it is always safe to start with vector 40H.
9. If you have not used AEOI - make sure that a non-specific EOI is given at the end of the ISR before IRET
statement.
10. Make sure that IVT is initialized before using interrupts.

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Interfacing of i8086 with i8087:

1. As a coprocessor (8087) is connected to 8086, 8086 operates in maximum mode. Thus the MN/𝑀𝑋 is
grounded.
2. 8284 provides the common CLK, RESET and READY signals. 8282 are used to latch the address.
8286 are used as data trans-receivers. 8288 generates control signals using 𝑆2 , 𝑆ഥ1 and 𝑆0 as input
from the currently active processor. 8259 PIC is used to accept the interrupt from 8087 and send it to
the microprocessor.
3. This interface is also called as coprocessor configuration. Here 8086 is called as the host and 8087 as
coprocessor as it cannot operate all by itself.
4. We write a homogeneous program which contains both 8086 as well as 8087 instructions.
5. Only 8086 can fetch instructions but these instructions also enter 8087. 8087 treats 8086
instructions as NOP.
6. ESC is used as a prefix for 8087 instructions. When as instruction with ESC prefix (5 MSB bits as
11011) is encountered, 8087 is activated.
7. The ESC instruction is decoded by both 8086 and 8087.
8. If the 8087 instruction has only an opcode (no operands) then 8087 will start execution and 8086 will
immediately move its next instruction.
9. But if the instruction requires a memory operand, then 8086 will have to fetch the first word of the
operand as 8087 cannot calculate the physical address. This word will be captured by 8087. Now the
remaining words (for a large operand) can be fetched by 8087 by simply incrementing the address of
the first word. Thus 8087 need help from 8086.
10. Once 8087 gets its operand, it begins processing by making the BUSY output high. This BUSY
output is connected to the TEST input of the microprocessor. Now 8087 execute its instruction and
8086 moves ahead with its next instruction. Hence multiprocessing takes place.
11. During execution, if 8087 needs to read/ write more words from the memory, then it does so by
stealing bus cycles from the microprocessor in the following manner. The 𝑅𝑄 / 𝐺𝑇0 of 8087 is
connected to 𝑅𝑄 / 𝐺𝑇0 of the microprocessor. 8087 gives an active low request pulse. 8086
completes the current bus cycle and gives the grant pulse and enters the hold state. 8087 uses the
shared system bus to perform the data transfer with the memory. 8087 gives the release pulse and
returns the system bus back to the microprocessor.
12. If 8086 requires the result of the 8087 operation, it first executes the WAIT instruction. WAIT makes
the microprocessor check the TEST pin. If the TEST pin is high (8087 is BUSY), then the
microprocessor enters WAIT state. It comes out of it only when TEST is low (8087 has finished its
execution). Thus 8086 get the correct result of an 8087 operation.
13. During the execution if an exception occurs, which is unmasked, 8087 interrupts microprocessor
using the INT output pin through the PIC 8259.
14. The QS0 and QS1 lines are used by 8087 to monitor the queue of 8086. 8087 needs to know when
8086 will decode the ESC instruction so it synchronizes its queue with 8086 using QS0 and QS1 as
follows:

QS1QS1 QS0QS0 8087 operation

0 0 NOP
0 1 8087 compares the 5 MSB bits with 11011
(ESC code)
1 0 8087 clears its queue
1 1 If earlier comparison succeeds, 8087 fetches
the subsequent byte else NOP

This is the complete inter-processor communication between 8086 and 8087 to form a
homogeneous system.
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Below is another example of i8087 assembly code that calculates the volume of a cylinder (volume = π *
radius² * height). This example demonstrates more FPU stack operations and data conversions:
DATA SEGMENT
radius dd 3.0 ; Radius (32-bit float)
height dd 10.0 ; Height (32-bit float)
volume dd 0.0 ; Result (32-bit float)
pi dt 3.14159265358979323846 ; 80-bit extended precision Pi
CODE SEGMENT
START:
FINIT ; INITIALIZE THE FPU
; LOAD RADIUS INTO ST0 AND SQUARE IT
FLD DWORD [RADIUS] ; ST0 = 3.0
FMUL ST0, ST0 ; ST0 = 3.0^2 = 9.0
; MULTIPLY BY PI (ST0 = 9.0 * PI)
FLD TWORD [PI] ; ST0 = PI, ST1 = 9.0
FMULP ST1, ST0 ; ST0 = 9.0 * PI ≈ 28.2743
; MULTIPLY BY HEIGHT (ST0 = 28.2743 * 10.0)
FLD DWORD [HEIGHT] ; ST0 = 10.0, ST1 = 28.2743
FMULP ST1, ST0 ; ST0 = 28.2743 * 10.0 ≈ 282.743
; STORE RESULT AND POP THE STACK
FSTP DWORD [VOLUME] ; [VOLUME] = 282.743
; EXIT PROGRAM (LINUX SYSCALL EXAMPLE)
MOV EAX, 1 ; SYS_EXIT
XOR EBX, EBX ; EXIT CODE 0
INT 0X80

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Step-by-Step FPU Stack Visualization:
Instruction Stack After Execution (ST0 → ST7)
FLD [radius] [3.0]
FMUL st0, st0 [9.0]
FLD [pi] [Pi, 9.0]
FMULP ST1, ST0 [28.2743] (Pi * 9.0, stack popped)
FLD [height] [10.0, 28.2743]
FMULP ST1, ST0 [282.743] (28.2743 * 10.0, stack popped)
FSTP [volume] [] (result stored, stack empty)

Key i8087 Instructions Used:

FLD: Loads a value onto the FPU stack.
FLD DWORD [radius] pushes a 32-bit float.
FLD TWORD [pi] pushes an 80-bit extended-precision float.
FMULP: Multiplies two values on the stack, then pops the stack.
FMULP ST1, ST0 calculates ST1 * ST0, stores the result in ST1, and removes ST0.
FSTP: Stores the value in ST0 to memory and pops the stack.

Advanced i8087 Features Demonstrated:

Extended Precision: The pi constant uses 80-bit precision (dt) for maximum accuracy.
Stack Management: The FPU stack is manipulated dynamically to hold intermediate results.
Mixed Data Types: Combines 32-bit (dd) and 80-bit (dt) floats seamlessly.

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