Scribd
Upload
6 views4 pages

Lab6 - ING

The document outlines the objectives and procedures for Experiment 6 on multiplexers and demultiplexers in a computer engineering lab at Istanbul Health and Technology University. It includes information on implementing boolean functions using various types of multiplexers and decoders, along with a prelab assignment for students to design circuits. The lab equipment required for the experiment is also listed.

Uploaded by

ozkansercan55
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
6 views4 pages

Lab6 - ING

The document outlines the objectives and procedures for Experiment 6 on multiplexers and demultiplexers in a computer engineering lab at Istanbul Health and Technology University. It includes information on implementing boolean functions using various types of multiplexers and decoders, along with a prelab assignment for students to design circuits. The lab equipment required for the experiment is also listed.

Uploaded by

ozkansercan55
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

Istanbul Health and Technology University

Department of Computer Engineering

LABORATORY WEEK 6
Spring 2024-2025

Name-Surname:

Student No:

Instructor:
Dr. Lecturer
Nazlı Tokatlı

6-1
EXPERIMENT 6: MULTIPLEXERS AND DEMULTIPLEXERS
2014 Fall

Objective:

Introduction to the function and use of multiplexers and demultiplexers in


digital circuits.

General Information:

As it is known, an (n+1) variable boolean function can be realized using an n-


select input MUX, if the number of variables is graeter than n+1, it may be necessary
to use AND and OR gates. In the following truth table (Table 5.1), output F is 1 for
minterms 0, 1, 3 and 4, and it is 0 for minterms 2, 5, 6, 7. F function can be
implemented using A, B and C as select-line inputs to an 8-to-1 multiplexer, and
connecting 1 to inputs I0, I1,I3 and I4. And 0 to inputs I2, I5, I6 and I7 (Fig. 5.1).

F = ABC + ABC + ABC + ABC

A B C F
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0

Table 5.1 – Truth Table

1
F
1

A B C

Figure 5.1 – 8-to-1 Multiplexer

6-2
To implement the same circuit using 4-to-1 MUX, use one of the variables (C) as
input to the MUX and other variables (A and B) as select lines (Fig. 5.2).
1 I0
C I1
F
C I2
0 I3

A B

Figure 5.2 – 4-to-1 Multiplexer

Functions can also be implemented using decoders. Consider a 3-to-8 decoder and the
truth table in Table 6.1, outputs corresponding to minterms 0, 1, 3, 4 can be connected
by an invert-OR gate to obtain the function F (Fig. 5.3).

F0

F1
F
F2

F3
0 DI
F4

F5

F6

F7

A B C

Figure 5.3 - 3-to-8 Decoder (ROM)

Prelab:

1. Design circuits to implement the following expression using:

NOTE: IMPLEMENT THE DESIGN FOR A,B,C AND PRELAB SECTION 2


ON PAPER AND YOU SHOULD BRING IT WITH YOU NEXT WEEK IN
LAB SECTION .
a. An 8-to-1 MUX
b. A 4-to-1 MUX
c. A 3-to-8 Decoder

F = ABC + ABC + ABC + ABC

2. Design a 4:1 multiplexer circuit using only 2:1 multiplexers.

6-3
Lab Equipment:

74LS153 Dual 4-Input Multiplexer


74LS157 Quad 2-Input Multiplexer
74LS151 8-Input Multiplexer
74LS138 1-of-8 Decoder/Demultiplexer
74LS20 Dual 4-Input NAND Gate

Procedure:

1. Wire the circuits you designed for prelab section 1 step a, b and c.

2. Wire the circuit you designed for prelab section 2.

6-4

You might also like