Gate-Level Minimization

Logic and Digital System Design - CS 303

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 Complexity of Digital Circuits
• Directly related to the complexity of the algebraic
expression we use to build the circuit.
• Truth table
– may lead to different implementations
– Question: which one to use?
• Optimization techniques of algebraic expressions
– So far, ad hoc.
– Need more systematic (algorithmic) way
• Karnaugh (K-) map technique
• Quine-McCluskey
• Espresso 2
 Two-Variable K-Map
• Two variables: x and y
– 4 minterms:
• m0 = x’y’  00
• m1 = x’y  01
• m2 = xy’  10
• m3 = xy  11

y y
x 0 1 x 0 1
0 m0 m1 0 x’y’ x’y
1 m2 m3 1 xy’ xy

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 Example: Two-Variable K-Map
y
x 0 1
0 1 1
1 1 0

– F = m0 + m1 + m2 = x’y’ + x’y + xy’

– F=…
– F=…
– F=…
– F = x’ + y’
• We can do the same optimization by combining adjacent
cells.
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 Three-Variable K-Map
yz
x 00 01 11 10
0 m0 m1 m3 m2
1 m4 m5 m7 m6

• Adjacent squares: they differ by only one variable, which

is primed in one square and not primed in the other
– m2 m6 , m3 m7
– m2 m0 , m6 m4

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 Example: Three-Variable K-Map
• F1(x, y, z) = (2, 3, 4, 5)
yz
x 00 01 11 10
0 0 0 1 1
1 1 1 0 0

• F1(x, y, z) = xy’ + x’y

• F2(x, y, z) = (3, 4, 6, 7)
yz
x 00 01 11 10
0 0 0 1 0
1 1 0 1 1
• F1(x, y, z) = xz’ + yz 6
 Three Variable Karnaugh Maps

• One square represents one minterm with three literals

• Two adjacent squares represent a term with two literals
• Four adjacent squares represent a term with one literal
• Eight adjacent squares produce a function that is
always equal to 1.

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 Example

• F1(x, y, z) = (0, 2, 4, 5, 6)

y
yz
x 00 01 11 10
0 1 0 0 1
x 1 1 1 0 1

F1(x, y, z) =
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 Finding Sum of Minterms
• If a function is not expressed in sum of minterms form, it
is possible to get it using K-maps
– Example: F(x, y, z) = x’z + x’y + xy’z + yz

yz
x 00 01 11 10
0 1 1 1
1 1 1

F(x, y, z) = x’y’z + x’yz + x’yz’ + xy’z + xyz

F(x, y, z) =
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 Four-Variable K-Map
• Four variables: x, y, z, t
– 4 literals
– 16 minterms
z
zt
xy 00 01 11 10
00 m0 m1 m3 m2
01 m4 m5 m7 m6
y
11 m12 m13 m15 m14
x
10 m8 m9 m11 m10

t
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 Example: Four-Variable K-Map
– F(x,y,z,t) = (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14)

zt
xy 00 01 11 10
00 1 1 0 1
01 1 1 0 1
11 1 1 0 1
10 1 1 0 0

– F(x,y,z,t) = z’ + x’t’ + yt’

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 Example: Four-Variable K-Map
• F(x,y,z,t) = x’y’z’ + y’zt’ + x’yzt’ + xy’z’

zt
xy 00 01 11 10
00 1 1 0 1
01 0 0 0 1
11 0 0 0 0
10 1 1 0 1

• F(x,y,z,t) = y’t’ + y’z’ + x’zt’

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 Prime Implicants
• A product term
– obtained by combining maximum possible number of
adjacent squares in the map
• If a minterm is covered by only one prime implicant, that
prime implicant is said to be essential.
– A single 1 on the map represents a prime implicant if it is not
adjacent to any other 1’s.
– Two adjacent 1’s form a prime implicant, provided that they
are not within a group of four adjacent 1’s.
– So on
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 Example: Prime Implicants
• F(x,y,z,t) = (0, 2, 3, 5, 7, 8, 9, 10, 11, 13, 15)
zt
xy 00 01 11 10
00 1 0 1 1
01 0 1 1 0
11 0 1 1 0
10 1 1 1 1

• Prime implicants
• y’t’ – essential since m0 is covered only in it
• yt - essential since m5 is covered only in it
• They together cover m0, m2, m8, m10, m5, m7, m13, m15
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 Example: Prime Implicants
zt
xy 00 01 11 10
00 1 0 1 1
01 0 1 1 0
11 0 1 1 0
10 1 1 1 1

• m3, m9, m11 are not yet covered.

• How do we cover them?
• There are actually more than one way.

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 Example: Prime Implicants
zt
1
xy 00 01 11 10
2
00 1 0 1 1
01 0 1 1 0
3
11 0 1 1 0
10 1 1 1 1
4

• Both y’z and zt covers m3 and m11.

• m9 can be covered in two different prime implicants:
– xt or xy’
• m3, m11  zt or y’z
• m9  xy’ or xt
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 Example: Prime Implicants
• F(x, y, z, t) = yt + y’t’ + zt + xt or
• F(x, y, z, t) = yt + y’t’ + zt + xy’ or
• F(x, y, z, t) = yt + y’t’ + y’z + xt or
• F(x, y, z, t) = yt + y’t’ + y’z + xy’
• Therefore, what to do
– Find out all the essential prime implicants
– Other prime implicants that covers the minterms not covered
by the essential prime implicants
– Simplified expression is the logical sum of the essential
implicants plus the other implicants
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 Five-Variable Map
• Downside:
– Karnaugh maps with more than four variables are not simple
to use anymore.
– 5 variables  32 squares, 6 variables  64 squares
– Somewhat more practical way for F(x, y, z, t, w)

tw tw
yz 00 01 11 10 yz 00 01 11 10
00 m0 m1 m3 m2 00 m16 m17 m19 m18
01 m4 m5 m7 m6 01 m20 m21 m23 m22
11 m12 m13 m15 m14 11 m28 m29 m31 m30
10 m8 m9 m11 m10 10 m24 m25 m27 m26

x=0 x=1 18
 Many-Variable Maps
• Adjacency:
– Each square in the x = 0 map is adjacent to the corresponding
square in the x = 1 map.
– For example, m4  m20 and m15  m31
• Use four 4-variable maps to obtain 64 squares required
for six variable optimization
• Alternative way: Use computer programs
– Quine-McCluskey method
– Espresso method

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 Example: Five-Variable Map
• F(x, y, z, t, w) = (0, 2, 4, 6, 9, 13, 21, 23, 25, 29, 31)

tw tw
yz 00 01 11 10 yz 00 01 11 10
00 1 1 00
01 1 1 01 1 1
11 1 11 1 1
10 1 10 1

x=0 x=1
• F(x,y,z,t,w) = x’y’w’ + xzw + yt’w
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 Product of Sums Simplification
• So far
– simplified expressions from Karnaugh maps are in sum of
products form.
• Simplified product of sums can also be derived from
Karnaugh maps.
• Method:
– A square with 1 actually represents a “minterm”
– Similarly an empty square (a square with 0) represents a
“maxterm”.
– Treat the 0’s in the same manner as we treat 1’s
– The result is a simplified expression in product of sums form.
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 Example: Product of Sums
• F(x, y, z, t) = (0, 1, 2, 5, 8, 9, 10)
– Simplify this function in
a. sum of products
b. product of sums
zt
xy 00 01 11 10
00 1 1 1
01 1
11
10 1 1 1

F(x, y, z, t) = y’t’ + y’z’ + x’z’t

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 Example: Product of Sums
• F’(x,y,z,t) = zt + yt’ + xy
• Apply DeMorgan’s theorem (use dual theorem)
• F=
zt
xy 00 01 11 10
00 1 1 0 1
01 0 1 0 0
11 0 0 0 0
10 1 1 0 1

F(x,y,z,t) = y’t’ + y’z’ + x’z’t

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 Example: Product of Sums
y’
t’
y’
F
z’
x’
z’
t
F(x,y,z,t) = y’t’ + y’z’ + x’z’t: sum of products implementation

y’
t
x’
F
y’
z’
t’
F = (y’ + t)(x’ + y’)(z’ + t’): product of sums implementation 26
 Product of Maxterms
• If the function is originally expressed in the product of
maxterms canonical form, the procedure is also valid
• Example:
– F(x, y, z) = (0, 2, 5, 7)

yz
x 00 01 11 10
0 0 1 1 0
1 1 0 0 1

F(x, y, z) =
F(x, y, z) = x’z + xz’ 27
 Product of Sums
• To enter a function F, expressed in product of sums, in
the map
1. take its complement, F’
2. Find the squares corresponding to the terms in F’,
3. Fill these square with 0’s and others with 1’s.
• Example:
– F(x, y, z, t) = (x’ + y’ + z’)(y + t)
– F’(x, y, z, t) = xyz + y’t’ zt
xy 00 01 11 10
00 0 0
01
11 0 0
10 0 0 28
 Don’t Care Conditions 1/2

• Some functions are not defined for certain input

combinations
– Such function are referred as incompletely specified functions
– For instance, a circuit defined by the function has never certain
input values;
– therefore, the corresponding output values do not have to be
defined
– This may significantly reduces the circuit complexity

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 Don’t Care Conditions 2/2
• Example: A circuit that takes the 10’s complement of
decimal digits

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 Unspecified Minterms
• For unspecified minterms, we do not care what the
value the function produces.
• Unspecified minterms of a function are called don’t care
conditions.
• We use “X” symbol to represent them in Karnaugh map.
• Useful for further simplification
• The symbol X’s in the map can be taken 0 or 1 to make
the Boolean expression even more simplified

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 Example: Don’t Care Conditions
• F(x, y, z, t) = (1, 3, 7, 11, 15) – function
• d(x, y, z, t) = (0, 2, 5) – don’t care conditions

zt
xy 00 01 11 10 F = zt + x’y’t
00 X 1 1 X
01 0 X 1 0 F1 = zt + x’y’ or
11 0 0 1 0
10 0 0 1 0 F2 = zt + x’t

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 Example: Don’t Care Conditions
• F1 = zt + x’y’ = (0, 1, 2, 3, 7, 11, 15)
• F2 = zt + x’t = (1, 3, 5, 7, 11, 15)
• The two functions are algebraically unequal
– As far as the function F is concerned both functions are
acceptable
• Look at the simplified product of sums expression for the
same function F.
zt
xy 00 01 11 10
00 X 1 1 X F’ = t’ + xz’
01 0 X 1 0
F = t(x’+z)
11 0 0 1 0
10 0 0 1 0 33
 NAND and NOR Gates
• NAND and NOR gates are easier to fabricate
VDD

C = (AB)’
A

CMOS 2-input AND gates requires

B 6 CMOS transistors
CMOS 3-input NAND gates requires
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6 CMOS transistors
 Design with NAND or NOR Gates
• It is beneficial to derive conversion rules from Boolean
functions given in terms of AND, OR, an NOT gates into
equivalent NAND or NOR implementations

x (x x)’ = x’  NOT

x
y [ (x y)’ ]’ = x y  AND

x
(x’ y’ )’ = x + y  OR
y
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 New Notation
x x x’ + y’ + z’
y (xyz)’ y
z z
AND-invert Invert-OR
• Implementing a Boolean function with NAND gates is
easy if it is in sum of products form.
• Example: F(x, y, z, t) = xy + zt
x x
y y

z z
t t
F(x, y, z, t) = xy + zt F(x, y, z, t) = ((xy)’)’ + ((zt)’)’
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 The Conversion Method
x x
y y
z z
t t

((xy)’)’ + ((zt)’)’ = xy + zt = [ (xy)’ (zt)’ ] ’

• Example: F(x, y, z) = (1, 3, 4, 5, 7)

yz F = z + xy’
x 00 01 11 10
0
F = (z’)’ + ((xy’)’)’
1 1
1 1 1 1
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 Example: Design with NAND Gates
x x
y’ y’
F F
z’ z’

F = (z’)’ + ((xy’)’)’ F = z + xy’

• Summary
1. Simplify the function
2. Draw a NAND gate for each product term
3. Draw a NAND gate for the OR gate in the 2nd level,
4. A product term with single literal needs an inverter in the
first level. Assume single, complemented literals are
available. 38
 Multi-Level NAND Gate Designs
• The standard form results in two-level implementations
• Non-standard forms may raise a difficulty
• Example: F = x(zt + y) + yz’
– 4-level implementation

z
t
y
F
x
y
z’
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 Example: Multilevel NAND…
F = x(zt + y) + yz’

z
t
y’
x F
y
z’

z
t
y’
x F
y
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z’
 Design with Multi-Level NAND Gates
• Rules
1. Convert all AND gates to NAND gates
2. Convert all OR gates to NAND gates
3. Insert an inverter (one-input NAND gate) at the output
if the final operation is AND
4. Check the bubbles in the diagram. For every bubble
along a path from input to output there must be
another bubble. If not so,
a. complement the input literal

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 Another (Harder) Example
• Example: F = (xy’ + xy)(z + t’)
– (three-level implementation)

x
y’
x
y F
z
t’

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 Example: Multi-Level NAND Gates
x F = (xy’ + xy)(z + t’)
y’
x
y G = [ (xy’ + xy)(z’ + t) ]’
z
t’ F = (xy’ + xy)(z + t’)

x
y’
x
y
z’
t F = (xy’ + xy)(z + t’)
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 Design with NOR Gates
• NOR is the dual operation of NAND.
– All rules and procedure we used in the design with NAND gates
apply here in a similar way.
– Function is implemented easily if it is in product of sums form.

x (x + x)’ = x’  NOT

x
y [ (x+ y)’ ]’ = x + y  OR

x
(x’ + y’ )’ = x · y  AND
y 44
 Example: Design with NOR Gates
• F = (x+y) (z+t) w
x
y
F
z
t
w

x
y
z
t F = (x + y) (z + t) w
w’

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 Example: Design with NOR Gates
• F = (xy’ + zt) (z + t’)
x
y’
z F
t
z
t’

x’
y
z’
t’ F = [((x’ + y)’ + (z’ + t’)’)’ + (z + t’)’]’
z = ((x’ + y)’ + (z’ + t’)’)(z + t’)
t’ = (xy’ + zt) (z + t’) 46
 Harder Example
• Example: F = x(zt + y) + yz’
z
t
y
F
x
y
z’

z’
t’
y
x’
y’ F
z
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 Exclusive-OR Function
• The symbol:
– x y = xy’ + x’y
– (x y)’ = xy + x’y’
• Properties
1. x 0=x
2. x 1 = x’
3. x x=0
4. x x’ = 1
5. x y’ = x’ y = (x y)’ - XNOR
• Commutative & Associative
– x y=y x
– (x y) z = x (y z)
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 Exclusive-OR Function
• XOR gate is not universal
– Only a limited number of Boolean functions can be expressed
in terms of XOR gates
• XOR operation has very important application in
arithmetic and error-detection circuits.
• Odd Function
– (x y) z = (xy’ + x’y) z
= (xy’ + x’y) z’ + (xy’ + x’y)’ z
= xy’z’ + x’yz’ + (xy + x’y’) z
= xy’z’ + x’yz’ + xyz + x’y’z
= (4, 2, 7, 1)
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 Odd Function

• If an odd number of variables are equal to 1, then the

function is equal to 1.
• Therefore, multivariable XOR operation is referred as
“odd” function.
yz
x 00 01 11 10
0 0 1 0 1 Odd function
1 1 0 1 0
yz
x 00 01 11 10
0 1 0 1 0 Even function
1 0 1 0 1 50
 Odd & Even Functions
x
y x y z Odd function
z

• (x y z)’ = ((x y) z)’

x
y (x y z)’

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 Adder Circuit for Integers
• Addition of two-bit numbers
– Z=X+Y
– X = (x1 x0) and Y = (y1 y0)
– Z = (z2 z1 z0)
• Bitwise addition
1. z0 = x0 y0 (sum)
c1 = x0 y0 (carry)
2. z1 = x1 y1 c1
c2 = x 1 y1 + x 1 c1 + y 1 c1
3. z2 = c2

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 Adder Circuit
z1 = x1 y1 c1 z0 = x0 y0
z2 = c2 c2 = x 1 y 1 + x 1 c1 + y 1 c1 c1 = x 0 y0

y1 x1 y0 x0

c1
FA

c2= z2 z1 z0

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 Comparator Circuit with NAND gates
• F(X>Y)
– X = (x1 x0) and Y = (y1 y0)

y1y0
x1x0 00 01 11 10
00 0 0 0 0
01 1 0 0 0
11 1 1 0 1
10 1 1 0 0

– F(x1, x0, y1, y0) = x1y1‘ + x1x0y0‘ + x0y0‘y1‘

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 Comparator Circuit - Schematic
– F(x1, x0, y1, y0) = x1y1‘ + x1x0y0‘ + x0y0‘y1‘

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Comparator Circuit - Simulation

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