JANUARY 2021

DIPLOMA IN ELECTRICAL ENGINEERING

STUDY GUIDE

DIGITAL SYSTEMS I
(DSY1501)

DEPARTMENT OF ELECTRICAL AND MINING ENGNIEERING

UNIVERSITY OF SOUTH AFRICA (UNISA)
Lecturer: Mrs. Idah M. Masopoga
Email: [email protected]

compiled by: Dr. M.E. Migabo

Copyright © University of South Africa 2021
Copyright © University of South Africa 2021

P UBLISHED BY UNISA

HTTPS :// WWW. UNISA . AC . ZA /

First version, April 2021

 Contents

I Introduction Unit
0.1 Prescribed Textbook 11
0.2 Recommended textbook 11
0.3 Overview of the module 13
0.4 How do I go about studying this module? 13
0.5 Tutorial matter for the module 14
0.6 What are some of the main features of this study guide? 15
0.7 List Of Terms 15

II Course Content

1 Introduction to Digital Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

1.1 Analogue, Discrete and Digital Signals 19
1.1.1 Analogue Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.2 Discrete Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.1.3 Digital Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.2 The Binary system, Logic levels and Digital Waveforms 21
1.2.1 Logic levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.2.2 Digital Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.3 Worked Example 24
1.4 Self-assessment Activity 25
1.5 Reference 26
2 Number Systems and Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.1 A Revision of the Decimal Number Systems 28
2.1.1 What is the Decimal number system? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1.2 Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1.3 Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.1.4 Brief Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2 Binary Numbers 28
2.2.1 What is the Binary number system? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.2 Notations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2.2.3 Counting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.4 Binary to Decimal conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2.5 Decimal to Binary conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.6 Decimal to any number system conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.2.7 Brief Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.3 Binary Arithmetic 31
2.3.1 Binary Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3.2 Binary subtraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.3.3 Complements of binary numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.3.4 Binary Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3.5 Binary division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3.6 Signed Binary Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3.7 Floating Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.3.8 Arithmetic Operations with Signed Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.3.9 Brief Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4 Hexadecimal Numbers 37
2.4.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.4.2 Hexadecimal to Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2.5 Octal Numbers 39
2.5.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.5.2 Octal to Binary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2.6 Digital Codes 40
2.6.1 Binary Coded Decimal (BCD) numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.6.2 Gray Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.6.3 ASCII Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.7 Error detection Codes 42
2.7.1 Parity Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.7.2 Cyclic Redundancy Check (CRC) Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
2.8 Self-assessment Activity 44
2.9 Reference 45

3 Logic gates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.1 Introduction 47
3.2 The NOT gate: Inverter 48
3.2.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3 The AND gate 49
3.3.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.3.2 Example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.3.3 Application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4 The OR gate 50
3.4.1 Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.4.2 Example: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5 The Derived Logic Gates 51
3.5.1 The NAND gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
3.5.2 The NOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
3.5.3 The XOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
3.5.4 The XNOR gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6 Integrated Circuits (ICs) 54
3.6.1 The 7400 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
3.6.2 The 7404 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.6.3 The 7408 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.6.4 The 7432 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.6.5 The 7486 IC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3.7 NOMENCLATURE OF ICs 57
3.8 Self-assessment Activity 58
3.9 my UNISA ACTIVITY: 59
3.10 References: 59
3.11 Experiments 59
3.11.1 Experiment 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.11.2 Experiment 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4 Boolean Algebra and Logic Simplification . . . . . . . . . . . . . . . . . . . . . 65

4.1 Introduction 65
4.2 Boolean Operations and Expressions 66
4.2.1 Boolean addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.2.2 Boolean multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
4.3 Rules of Boolean Algebra 66
4.4 DE MORGAN’S THEOREMS 68
4.5 STANDARD FORMS OF BOOLEAN EXPRESSIONS 68
4.6 CONSTRUCTING A TRUTH TABLE FOR A LOGIC CIRCUIT 70
4.7 Karnaugh Maps 72
4.8 Examples 75
4.8.1 Example 4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
4.8.2 Example 4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
4.9 Code Converters 77
4.9.1 Example 4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
4.10 A Simple Design Question 79
4.11 Summary 81
4.12 Self-assessment Activity 81
4.13 myUNISA Activity 81
4.14 Reference 82
4.15 Experiment 82

5 Combinational logic circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

5.1 GATE UNIVERSALITY: IMPLEMENTATION OF OTHER LOGIC GATES USING NAND
GATES ONLY 85
5.2 GATE UNIVERSALITY: IMPLEMENTATION OF OTHER LOGIC GATES USING NOR
GATES ONLY 87
5.3 Examples 88
5.3.1 Example 5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
5.3.2 Example 5.2: Solved example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
5.4 Summary 90
5.5 Activities 90
5.5.1 Activity 5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
5.5.2 Activity 5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
5.6 myUNISA ACTIVITY 91
5.7 Reference 91
5.8 Experiment 91

6 Functions of combinational logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6.1 Basic Adders 93
6.1.1 Half-adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.1.2 Full-Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.2 Parallel Adders 98
6.2.1 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3 COMPARATORS 101
6.4 DECODERS 104
6.4.1 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.5 Encoders 109
6.6 MULTIPLEXERS 112
6.6.1 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
6.7 Examples 116
6.7.1 Example 6.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.8 Summary 117
6.9 Activity 6.1 118
6.9.1 Activity 6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.10 myUNISA ACTIVITY 118
6.11 REFERENCE 119

7 And-or-invert (AOI) ICs for implementing SOP expressions . . . . . 121

7.1 Introduction 121
7.2 The 74S64 4-WIDE 4-2-3-2 AOI 122
7.3 THE 74LS54 4-WIDE 2-3-3-2 AOI 124
7.4 The 74LS51 AND-OR-INVERT (AOI) GATES 125
7.5 Summary 127
7.6 Activity 7.1 128

8 FEEDBACK ON ACTIVITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.1 ACTIVITY 1.1 129
8.2 ACTIVITY 2.1 129
8.3 ACTIVITY 3.1 130
8.4 ACTIVITY 3.2 130
8.5 ACTIVITY 4.1 130
8.6 ACTIVITY 4.2 130
8.7 ACTIVITY 5.1 131
8.8 ACTIVITY 5.2 131
8.9 ACTIVITY 6.1 132
8.10 ACTIVITY 6.2 132
8.11 ACTIVITY 7.1 132
I
Introduction Unit

0.1 Prescribed Textbook

0.2 Recommended textbook
0.3 Overview of the module
0.4 How do I go about studying this module?
0.5 Tutorial matter for the module
0.6 What are some of the main features of this study
guide?
0.7 List Of Terms
 Reference Textbooks

0.1 Prescribed Textbook

Thomas, L. Floyd. Digital Fundamentals, Global Edition, 11th edition, Person (intl), ISBN:9781292075983,
1292075988; eISBN: 9781292075990, 1292075996

0.2 Recommended textbook

John Crowe and Barrie Hayes-Gill, Introduction to Digital Electronics.
 Getting Started

0.3 Overview of the module

Together with this study guide, we use the following textbook:
Digital Fundamentals, Global Edition, 11th edition, Pearson (intl), ISBN: 9781292075983, 1292075988;
eISBN: 9781292075990, 1292075996.
You will see that this study guide contains various assessment opportunities in the form of
examples or self-assessment activities, which are included in each study unit. Ensure that you
complete as many of these as possible, as this will give you an indication of your comprehension of
the subject matter. More guidance and feedback will also be given on the myUnisa website.
Digital systems represent signals by discrete bands of analogue levels, rather than by continuous
range. All levels within a band represent the same signal state. Relatively small changes to the
analogue signal levels due to manufacturing tolerance, signal attenuation or parasitic noise do not
leave the discrete envelope, and as a result are ignored by signal sensing circuitry. In most cases
there are two such states, and they are represented by two voltage bands: one near the reference
value (ground or zero) and another value near the supply voltage, corresponding to the false (0)
and true (1) values of Boolean domain respectively. Basically knowledge regarding digital systems
is applied in the industry for purposes of designing digital circuits such as alarms, sensor circuits,
embedded systems design, programming micro-controllers, etc.

0.4 How do I go about studying this module?

We have essentially used an outcomes-based approach in developing this module. This means
that, instead of using a set of topics as a starting point, we used certain outcomes or results of
learning. We considered the kind of tasks that you will have to carry out in the work environment,
and planned the module in such a way that it will help you to acquire the necessary competences to
perform these tasks. These tasks are reflected in the purpose of the module mentioned above, as
well as in the learning outcomes that appear at the beginning of every study unit. The teaching in
this module is also based on the principle of “active learning”. It has been shown that the more
actively one is involved in reading and learning, the more clearly one understands what one is
 14

learning, and the more effectively one can apply one’s knowledge and skills in real-life situations.
To help you work through this study guide actively – rather than just reading it passively – we
have included a large number of activities, examples and self-assessment questions. By completing
these, you will ensure that what you are learning is meaningful to you, and you will start to develop
the practical skills that will be required in your work situation.

0.5 Tutorial matter for the module

• The website myUnisa, for which you will need to register
• Tutorial Letter 101
• This online study guide, composed of study units 1 to 7
• Other tutorial letters that you may receive on myUnisa during the course of the semester
You should start by reading Tutorial Letter 101, if you have not already done so. It will tell
you more about the general arrangements relating to the module, and give you details about your
assignments and assignment questions. Announcements concerning introductions to subject areas,
discussions of problem areas experienced by you and by other students, and information concerning
the examination will appear on myUnisa. You should access myUnisa regularly to check for updates
in the form of announcements, submission deadlines for assignments, course material in the form
of tutorial letters, memos for tutorial letters and so forth.
This module is 12 credits. This means, you should spend a total of about 120 hours on studying
this module. I suggest that you draw up a study schedule to ensure that you will be able to achieve
the module outcomes in the time you have available this semester.
Note the following guidelines:
• Skim through this study guide and look at some of the typical activities you will need to
complete as you work through it. (There are some activities in every study unit, and usually
also a larger set of revision activities at the end of every chapter in the textbook as well.)
Estimate how long it might take you to work through the study guide.
• Also look at the assignments you will need to complete, and think about the time you will
need to spend on them.
• Furthermore, take into account that you will need to revise your study guide to prepare for
the examination. The more thoroughly you have worked through the study guide, the easier
your revision process will be.
• By the time you write the final examination paper, you should be confident in performing the
kind of activities you will have encountered in assignments.
Once you have considered the above questions, draw up your study schedule. When allocating
time to work through each of the study units in this study guide, remember that the study units are
not all of the same length, so you should assign more time for longer study units to ensure that your
schedule is achievable.
Once you have drawn up your schedule and skimmed through the study guide, you can start
working through the materials in earnest. Please attempt to complete all the activities, since only by
doing so will you find the material really meaningful. You may want to work through the material
first before starting your assignment, or may want to work on the materials and the assignments
simultaneously.
In Tutorial Letter 101 you will find more information on how to approach your assignments
and answer the assignment questions. It also contains information on the examination.
 0.6 What are some of the main features of this study guide? 15

0.6 What are some of the main features of this study guide?
The main features of this study guide are the following:
• LEARNING OUTCOMES
The learning outcomes and assessment criteria contained in each study unit can be regarded
as a checklist of the things you should be able to do once you have studied that particular
study unit. In other words, they tell you what the purpose of your learning in that particular
study unit is. When you are reviewing the module, you should look back at the assessment
criteria and check whether you have achieved them all. They will give you an overview of
the knowledge and skills you should have acquired in the module.
• WORKED EXAMPLES
Each study unit contains worked examples providing feedback on how a particular problem
should be attempted. These will give you an indication of how well you have grasped the
study material.
• SELF-ASSESSMENT ACTIVITY
Completing the activities will help you to acquire the knowledge and skills that are taught in
every unit, and will therefore enable you to achieve the learning outcomes. Feedback on the
activities is provided at the back of the study guide.
• FEEDBACK ON ACTIVITIES
Most activities are followed by some form of feedback (comments on or suggested answers
to) the questions in the activity. Sometimes this feedback appears as part of the study unit.
In many cases, however, we have included feedback at the end of this study guide. Please
note, however, that you should try to complete activities on your own first before checking
the feedback.
• myUnisa ACTIVITIES
At the end of each study unit you will find a myUnisa activity. Log on to myUnisa and check
the activity related to the specific study unit.
• REFERENCES
At the end of each study unit, you will find references to sources you can consult to, read
more on that particular topic.
• EXPERIMENTS
At the end of each study unit, you fill find practical experiments that you will need to do, that
will contribute to your year-end mark for the practical part of this module. If you complete
these experiments after studying the relevant study units, the experiments should not present
you with any problems.

0.7 List Of Terms

16

ASCII American Standard Code for Information Interchange;

the most widely used alphanumeric code.
BCD Binary Coded Decimal; a digital code in which each of
the decimal digits, 0 through 9, is represented by a group
of four bits.
CRC Cyclic Redundancy Check; A type of error detection code.
Duty Cycle The ratio of pulse width to period expressed as
a percentage.
Even Parity The condition of having an even number of 1s
in every group of bits.
Hexadecimal Describes a number system with a base of 16.
Integrated Circuit (IC) A type of circuit in which all
of the components are integrated on a single chip of
semiconductive material of very small size.
Karnaugh map – An arrangement of cells representing the
combinations of literals in a Boolean expression and used
for a systematic simplification of the expression.
Logic In digital electronics, the decision-making
capability of gate circuits, in which a HIGH represents a
true statement and a LOW represents a false one.
Least significant bit (LSB) Generally, the right-most bit in
a binary whole number or code.
Most significant bit (MSB) The left-most bit in a binary whole
number or code.
Octal Describes a number system with a base of eight.
Odd Parity The condition of having an odd number of
1s in every group of bits.
Product-of-Sums (POS) A form of Boolean expression
that is basically the ANDing of ORed terms.
Sum-of-Products (SOP) A form of Boolean expression that
is basically the ORing of ANDed terms.
Sign bit The left-most bit of a binary number that
designates whether the number is positive (0) or negative (1).
TTL Transistor-transistor logic; a class of integrated
logic circuit that uses bipolar junction transistors.
Also called bipolar.
Truth Table A table showing the inputs and corresponding
output level of a logic circuit.

Table 1: List of terms

 4 Boolean Algebra and Logic Simplification
65
4.1 Introduction
4.2 Boolean Operations and Expressions
4.3 Rules of Boolean Algebra
4.4 DE MORGAN’S THEOREMS
4.5 STANDARD FORMS OF BOOLEAN EXPRESSIONS
4.6 CONSTRUCTING A TRUTH TABLE FOR A LOGIC CIR-

II
4.7
4.8
Course Content
CUIT
Karnaugh Maps
Examples
4.9 Code Converters
4.10 A Simple Design Question
4.11 Summary
4.12 Self-assessment Activity
4.13 myUNISA Activity
4.14 Reference
4.15 Experiment

5 Combinational logic circuits . . . . . . . . . 85

5.1 GATE UNIVERSALITY: IMPLEMENTATION OF OTHER
LOGIC GATES USING NAND GATES ONLY
5.2 GATE UNIVERSALITY: IMPLEMENTATION OF OTHER
LOGIC GATES USING NOR GATES ONLY
5.3 Examples
5.4 Summary
5.5 Activities
5.6 myUNISA ACTIVITY
5.7 Reference
5.8 Experiment

6 Functions of combinational logic . . . . . 93

6.1 Basic Adders
6.2 Parallel Adders
6.3 COMPARATORS
6.4 DECODERS
6.5 Encoders
6.6 MULTIPLEXERS
6.7 Examples
6.8 Summary
6.9 Activity 6.1
6.10 myUNISA ACTIVITY
6.11 REFERENCE

7 And-or-invert (AOI) ICs for implementing

SOP expressions . . . . . . . . . . . . . . . . . . . . 121
7.1 Introduction
7.2 The 74S64 4-WIDE 4-2-3-2 AOI
7.3 THE 74LS54 4-WIDE 2-3-3-2 AOI
7.4 The 74LS51 AND-OR-INVERT (AOI) GATES
7.5 Summary
7.6 Activity 7.1

8 FEEDBACK ON ACTIVITIES . . . . . . . . . . . . 129

8.1 ACTIVITY 1.1
8.2 ACTIVITY 2.1
8.3 ACTIVITY 3.1
8.4 ACTIVITY 3.2
8.5 ACTIVITY 4.1
8.6 ACTIVITY 4.2
8.7 ACTIVITY 5.1
8.8 ACTIVITY 5.2
8.9 ACTIVITY 6.1
8.10 ACTIVITY 6.2
8.11 ACTIVITY 7.1
 1. Introduction to Digital Concepts

Overview of the Study Unit

This study unit introduces you to digital electronics and provides you with a broad overview of a
number of important concepts – in particular the difference between analogue and digital signals.
To complete this unit, study Chapter 1 in your prescribed textbook: Thomas, L Floyd. Digital
Fundamentals.

Learning Outcomes of this Unit

After completing this study unit, you should be able to:
• Explain the difference between digital and analogue signals
• Show how voltage levels are used to represent digital quantities
• Describe the various parameters of a pulse waveform such as rise time, fall time, pulse width,
frequency, period, and duty cycle

Assessment criteria for this unit

• The difference between a digital signal and an analogue signal is explained.
• The duty cycle of a pulse is calculated.

1.1 Analogue, Discrete and Digital Signals

A signal is a function of time that describes how a physical quantity (temperature, voltage, pressure
etc.) vary with respect to time (as time elapses). There are may types of signals among which
electrical signals consist of variation of voltage, current etc. electrical quantities. In digital systems,
our focus is on voltage signals.
 20 Chapter 1. Introduction to Digital Concepts

1.1.1 Analogue Signals

A signal is called analogue when it is defined in all instances of time. This means it is continuous
in time. In simpler terms, it means that for every instance of time t, there exists a defined value
of the signal. Majority of physical quantities exist in nature in the analogue form. An example of
an analogue signal is ambient temperature. As illustrated in figure 1.1 below, it does not suddenly
change from 75 to 76 degree Celsius, it goes through an infinite number of values including 75.01,
75.23 degree Celsius etc.

Figure 1.1: Illustration of a continuous time (analogue) signal (Floyd, 2015)

1.1.2 Discrete Signals

Because, an analogue signal is continuous, its number of values is infinite and should them be
required to be stored, that would be impossible. Let us now assume that the ambient temperature
was only measured every hour. This means that the values of interest are only hourly values in
this case and not all the values. These values are said to be sampled and the set of these values
defined only at specific instances of time for what we call a discrete signal as illustrated in figure
1.2. The discrete signal is also said to be discontinuous in time. The signal in figure 1.1 is said

Figure 1.2: Illustration of a discontinuous time (discrete) signal (Floyd, 2015)

to be sampled and quantized to generate the discrete signal in figure 1.2. Quantization is the
process of mapping continuous infinite values to a smaller set of discrete finite values.
For a further explanation watch the video clip:
Continuous and Discrete Time Signals by Neso Academy (10:56)
https://youtu.be/H4hk6N5vC1Q

1.1.3 Digital Signals

After obtaining of a discrete signal as per figure 1.2, a step further can be taken to represent each
discrete value by representing it as a code that consists of a series of 1s and 0s, to form what is called
a digital signal. The term digital comes from digit and has to do with the fact that initially people
used their digits to count. Since, most operations of digital systems are performed by counting,
hence the term digital. What is the benefit of digital signals over analogue signals in electronic
 1.2 The Binary system, Logic levels and Digital Waveforms 21

applications?
The benefit of digital signals over analogue signals is two fold:
• Firstly, digital signals can be processed and transmitted more efficiently and reliably than
analogue signals.
• Secondly, digital signals can be stored unlike analogue signals.
Watch the video clip below for a short summary of the difference between analogue and digital:
Analog vs Digital by Sunny classroom (3:52):https://youtu.be/gGxpUZ_iuYA

1.2 The Binary system, Logic levels and Digital Waveforms

A system consists of a set of one or more input signals on which processing is applied to generate
one or more output signals. One of such is a digital system which consists of one or more digital
input signals on which is performed digital processing to generate one or more digital output signals.
The processing of digital signals works according to a number of rules and theorems within a well
specified number system that is known as the binary number system.
• The binary number system is called binary because it only considers two possible states.
• These states are represented by two different voltage levels (A HIGH and LOW voltage
levels).
• The two states are represented by two digits known as binary digits (in short bits), namely
’0’ for the LOW state and ’1’ for the HIGH state.
• The combination of these bits forms digital codes.

1.2.1 Logic levels

The voltages used to represent the bits ’0’ and ’1’ are called logic levels. Ideally, logic levels
would be fixed voltage values (one to represent ’1’ and another to represent ’0’). In practice, they
correspond to ranges of voltages instead as illustrated in figure 1.3. From figure 1.3, it can be

Figure 1.3: Ranges of voltage representation of logic levels (Floyd, 2015)

seen that, besides the voltage ranges for the LOW and the HIGH logic levels, there is a range of
voltage ranges of voltages considered to be unacceptable for the operation of digital circuits. In
digital systems, there are two major families of logic levels. These are the Transistor Transistor
Logic (TTL) and the Complementary Metal Oxide Semiconductor (CMOS) logic summarized
in table 1.1.

Voltage range TTL CMOS Logic Levels

[VL(min) , VL(max) ] [0V, 0.8V] [0V, 0.8V] LOW
[VL(max) , VH(min) ] [0.8V, 2V] [0.8V, 2V] Unacceptable
[VH(min) , VH(max) ] [2V, 5V] [2V, 3.3V] HIGH

Table 1.1: TTL and CMOS logic levels summary

 22 Chapter 1. Introduction to Digital Concepts

1.2.2 Digital Waveforms

One key aspect in the analysis of digital signals and systems is the ability to graphically represent
digital signals. A bit can be graphically represented by what is called a digital pulse. The bit ’1’
is graphically represented by a HIGH pulse (also called positive-going pulse) while the bit ’0’ is
graphically represented by a LOW pulse (also called Negative-going pulse).
The digital pulse in figure 1.4 has two edges: a leading edge and a trailing edge. Depending
on whether, it is a HIGH pulse or a LOW pulse, these two edges can also be referred to as per table
1.2.

Edges HIGH pulse LOW pulse

Leading edge Rising edge Falling edge
Trailing edge Falling edge Rising edge

Table 1.2: Summary on edges of digital pulses

Figure 1.4: The ideal digital pulse (Floyd, 2015)

It is important to note that the digital pulses as represented in figure 1.4 are ideal. They are
represented as such for ease of analysis.

Figure 1.5: The real (non-ideal) digital pulse

1.2 The Binary system, Logic levels and Digital Waveforms 23

In reality, a real (non-ideal) digital pulse looks as per figure 1.5. This is the actual type of signal
you expect to measure on an oscilloscope or a logic analyzer during a laboratory measurement. A
real digital pulse has got the following main characteristics:
• The amplitude: The height from the baseline to 90% of the pulse.
• The rise time (tr ): The time it takes the pulse to go from 10% to 90% of its amplitude as it
transits from LOW state to HIGH state.
• The fall time (t f ): he time it takes the pulse to go from 90% to 10% of its amplitude as it
transits from HIGH state to LOW state.
• Pulse width: duration of the pulse as measured from 50% of the amplitude on the leading
edge to 50% of the amplitude on the trailing edge.
• Ringing: is the part of the pulse that oscillates between high and low amplitude heights
around the high or the low states of the pulse
• Droop: Is the part of the amplitude of the pulse where it starts to decay before going from
high state to low state.
• Overshoot: is the highest amplitude point of the pulse.
• Undershoot: is the lowest amplitude point of the pulse.

A series of multiple pulses that graphically represent the digital signal is called a digital waveform
(pulse train). A digital wave form is either:
• Periodic: when it repeats itself at a fixed interval of time know as period (T ). The rate
at which this signal repeats it self is known as its frequency ( f ). The unit of a the pe-
1
riod is seconds as it is a duration while the unit of frequency is known as Hz = second .
Therefore:

Theorem 1.2.1 f = T1 and T = 1f

– The duration of the HIGH state and the one of the LOW state are not always the same
in a periodic digital waveform.
– How the duration of the HIGH state also known as the Pulse width (tW = TON ) or ON
time relates to the entire duration of a full period T , is measured by means of what is
known as the duty cycle of a the periodic waveform.
– The duration of a period during which the waveform is in LOW state is also known as
the OFF time=TOFF .
The duty cycle is calculated as percentage as follows:

Theorem 1.2.2 dutycycle = ( tTW ) × 100% and T = TON + TOFF

• Nonperiodic: A digital waveform that does not repeat itself at a fixed interval of time.

Figure 1.6: The periodic digital waveform

• A special type of periodic waveform used in digital systems as the reference timing waveform
 24 Chapter 1. Introduction to Digital Concepts

is called the digital clock.

• The period of a clock is also known as the bit time.
• Timing diagram is a graph of multiple digital waveforms showing the actual time relation-
ship between them. It is important for analysis as it often show how digital waveforms relate
to each other and with respect to the reference waveform (clock) in terms of time as per
figure 1.7.

Figure 1.7: A typical timing diagram

• Data: is a group of bits that convey some type of meaningfull information.

• In digital system, data is often exchanged between different sub-systems of the same digital
system or even between different digital systems. This movement of data is know as data
transfer can either be serial or parallel.
• Serial data transfer: Is when data is transferred one bit a time on the same.
• Parallel data transfer: Is when data is transferred all bits at the same time on multiple
lines.
For a further explanation you can watch the video clip.
Binary Digits Logic Levels and Digital Waveforms by Columbia Gorge Community College (23:31)
https://youtu.be/HnhJ1-P-gFs

1.3 Worked Example

1. A periodic waveform has a pulse width tW two times bigger than its OFF time (TOFF ).
a) Calculate its duty cycle percentage given that it has a frequency of 0.25 kHz.
b) Calculate its period T , its pulse width tW and its time OFF (TOFF ) duration.
c) Draw two cycles of the signal’s waveform.
solution
a) tW = 2 × TOFF
tW + TOFF = T
duty cycle = ( tTW ) × 100% = ( (2×T2×T OFF
OFF )+TO FF
) × 100% = ( 32 ) × 100% = 66.667%
b) f = 0.25 kHz = 250 Hz
f = T1 , T = 1f = 2501
= 0.004sec = 4ms
T = tW + TOFF = 2 × TOFF + TOFF = 3 × TOFF
TOFF = T3 = 4 3ms = 1.333 ms
tW = 2 × TOFF = 2 × (1.333 ms) = 2.667 ms
c) Two cycles of the waveform are shown as below:
 1.4 Self-assessment Activity 25

1.4 Self-assessment Activity

1. The frequency of a signal is 1 kHz and the duty cycle is 25%. The amplitude of this signal at
10% is of 2V at a time instant of 200 us and the amplitude at 90% occurs at a time instant
of 300 us. Considering that the fall time of this signal is equal to its rise time, fill in all the
blanks (values and units)

2. In a TTL digital system, an input voltage of 3.5V would be classified as a:

a) HIGH logic level
b) LOW logic level
c) Unallowed logic level
d) None of the above

3. The frequency of a pulse generator circuit is 1 kHz and the pulse width is of 250 us, what is
the duty cycle percentage of the signal?
4. what is the frequency of a signal where TON = 5 ms, TOFF = 3 ms and the amplitude is of
5V?
5. In a certain digital wave form, the period is four times the pulse width. Calculate the duty
cycle of the signal.
6. A quantity having a continuous set of values is a/an ....................quantity.
7. What is the frequency of a signal where TON = 2ms, TOFF = 3 ms and the amplitude is 5V ?
8. The frequency of a pulse generator is 2 kHz and the pulse width is 125 s. What is the
percentage duty cycle of the signal?
9. The time interval on the leading edge of a pulse between .... % and ....% of the amplitude is
the rise time.
10. The pulse width (tw ) is the duration between the ......% points of the rise and fall times.
 26 Chapter 1. Introduction to Digital Concepts

11. The period of a signal is 5 times the pulse width. Calculate the duty cycle percentage. What
is the OFF time if the signal has a frequency of 25 Hz?

1.5 Reference
Refer to the chapter “Introductory concepts” in the prescribed book by Thomas Floyd
 2. Number Systems and Codes

Overview of the Study Unit

This study unit focuses on describing key numbers systems used in digital systems. It pays a special
focus on the binary number system and its relationship (conversion from and to) with other number
systems such as the octal, hexadecimal and decimal number systems. In this chapter, we also study
the basic arithmetic operations in each of these number systems. Finally, this chapter pays a close
attention to digital codes such as binary coded decimal (BCD), the Gray code as well as the ASCII
code as commonly used in digital systems.

Learning Outcomes of this Unit

After completing this study unit, you should be able to:
• Understand the structure and be able to count in the binary, octal, hexadecimal and decimal
number systems.
• Convert from any number system to another.
• Perform the basic arithmetic operations using the various numbering systems including
complements of numbers.
• Express decimal numbers in binary coded decimal (BCD) form and perform addition in BCD
• Convert from binary to gray code and vice versa
• Understand and interpret the ASCII codes

Assessment criteria for this unit

• Decimal to binary and binary to decimal conversions are applied logically.
• Subtraction of binary numbers using 1s and 2s complements are performed according to
standard procedures.
• Conversions between the various number systems and the hexadecimal system are applied
correctly.
• The various digital codes and their uses are identified and explained.
 28 Chapter 2. Number Systems and Codes

2.1 A Revision of the Decimal Number Systems

2.1.1 What is the Decimal number system?
The position of each digit in a weighted number system is assigned a weight based on the base or
radix of the system. The radix of decimal numbers is ten, because only ten symbols (0 through 9)
are used to represent any number and are called decimal digits.
The column weights of decimal numbers are powers of 10 that increase from right to left
beginning with 100 = 1: . . . 105 104 103 102 101 100
For fractional decimal numbers, the column weights are negative powers of 10 that decrease
from left to right: 102 101 100 .10−1 10−2 10−3 10−4 . . .
Decimal numbers can be expressed as the sum of the products of each digit times the column
value for that digit. Thus, the number 125.23 can be expressed as:
(1 × 102 ) + (2 × 101 ) + (5 × 100 ) + (2 × 10−1 ) + (3 × 10−2 ) (2.1)

2.1.2 Notations
In general, Decimal number systems are noted as: ...XYZ.FGH... or alternatively ...XY Z.FGH...10
E.g. 1456.235 or 1456.23510

2.1.3 Counting
To count in decimal number system one first goes through all the elements below the base value of
10: 0,1,2,3,4,5,6,7,8,9; then starts to combine them taking the digits from 1 to 9 and combine it
with the entire set of digits from 0 through 9 to give (10,11,12,13,....,19), then combining digits two
by two in their increasing order (e.g. 100,101,102, etc.) and then three by three in three increasing
order etc.

2.1.4 Brief Tutorial

1. Express the decimal number 5270.42 as the sum of values of each digit.
2. What is the base of the decimal number system?
3. Is the number 11 part of the decimal number system symbols?

2.2 Binary Numbers

2.2.1 What is the Binary number system?
The concept of binary numbers is very similar to the one of decimal numbers. The difference
between the two is the fact that binary numbers use a base=radix of 2 and, therefore uses only two
symbols namely 0,1.. The binary number system is the most commonly used number system in
digital systems. This is due to the fact that digital systems also known as digital electronics works
on two voltage levels namely the HIGH and the LOW voltage levels as studied in the previous
chapter with HIGH=1 and LOW=0. 0 and 1 are called binary digits (in short bits).
The column weights of binary numbers are powers of 2 that increase from right to left beginning
with 20 = 1: . . . 25 24 23 22 21 20
For fractional binary numbers, the column weights are negative powers of 2 that decrease from
left to right: 22 21 20 .2−1 2−2 2−3 2−4 . . .

2.2.2 Notations
In general, Binary number systems are noted as: ...XY Z.FGH...2 Binary numbers can be expressed
as the sum of the products of each digit times the column value for that digit. Thus, the number
101.10 represents the decimal value:
(1 × 22 ) + (0 × 21 ) + (1 × 20 ) + (1 × 2−1 ) + (0 × 2−2 ) = 5.510 (2.2)
 2.2 Binary Numbers 29

2.2.3 Counting
A binary counting sequence for numbers from zero to fifteen is shown in figure 2.1.

Figure 2.1: Counting in Binary number system (Floyd, 2015)

Notice the pattern of zeros and ones in each column. Application: Digital counters frequently
have this same pattern of digits.

2.2.4 Binary to Decimal conversion

The decimal value of any binary number can be found by adding the weights of all bits that are 1
and discarding the weights of all bits that are 0.

Example: The decimal value of any binary number can be found by adding the weights of
all bits that are 1 and discarding the weights of all bits that are 0.
 30 Chapter 2. Number Systems and Codes

Solution: The decimal value of any binary number can be found by adding the weights of all bits
that are 1 and discarding the weights of all bits that are 0.

2.2.5 Decimal to Binary conversion

Sum-of-weights method
You can convert a decimal whole number to binary by reversing the procedure. Write the decimal
weight of each column and place 1’s in the columns that sum to the decimal number.

Example: Convert the decimal number 49 to binary.

Solution: The column weights double in each position to the right. Write down column weights
until the last number is larger than the one you want to convert.

Repeated Division-by-2 Method

You can convert a decimal fraction to binary by repeatedly multiplying the fractional results of
successive multiplications by 2. The carries form the binary number. Example: Convert the
decimal fraction 0.188 to binary by repeatedly multiplying the fractional results by 2.

Solution:

2.2.6 Decimal to any number system conversion

You can convert decimal to any other base by repeatedly dividing by the base. For binary, repeatedly
divide by 2, for a base 8 number system called Octal number system by repeatedly dividing by
8, for hexadecimal number system by repeatedly dividing by the base=16. For any other number
system, by repeatedly dividing by its base N.

2.2.7 Brief Tutorial

1. What is the largest decimal number that can be represented in binary with eight bits?
2. Determine the weight of the 1 in the binary number 10000.
 2.3 Binary Arithmetic 31

3. Convert the binary number 10111101.011 to decimal

4. Convert the decimal number 45.75 to binary by sum-of weights method
5. Convert the decimal number 49 to binary by repeatedly dividing by 2.

2.3 Binary Arithmetic

2.3.1 Binary Addition
The rules for binary addition are:

When an input carry = C= 1 due to a previous result, the rules are:

Example: Add the binary numbers 00111 and 10101 and show the equivalent decimal addition

Solution:
 32 Chapter 2. Number Systems and Codes

2.3.2 Binary subtraction

The rules for binary subtraction are

Example: Subtract the binary number 00111 from 10101 and show the equivalent decimal subtrac-
tion.

Solution:

2.3.3 Complements of binary numbers

Similarly to the decimal number system where the complement of a given number is a number
of the same magnitude as the given number but of opposite sign, there also exists complement
of binary numbers. When it comes to complements of binary numbers, there are various types
including the following:

1’s complement
The 1’s complement of a binary number is just the inverse of the digits. To form the 1’s complement,
change all 0’s to 1’s and all 1’s to 0’s. For example, the 1’s complement of 110010102 is 001101012
In digital circuits, the 1’s complement is formed by using inverters:

Figure 2.2: Figure adapted from (Floyd, 2015)

 2.3 Binary Arithmetic 33

2’s complement
The 2’s complement of a binary number is found by adding 1 to the LSB of the 1’s complement.

Figure 2.3: Figure adapted from (Floyd, 2015)

2.3.4 Binary Multiplication

The four basic rules for multiplying bits are as follows: Multiplication is performed with binary

numbers in the same manner as with decimal numbers. It involves forming partial products,
shifting each successive partial product left one place, and then adding all the partial products.
Example 2.4 below illustrates the procedure; the equivalent decimal multiplications are shown for
reference. The numbers in a multiplication are the multiplicand, the multiplier, and the product.

Figure 2.4: Multiplication Example

These are illustrated in the following decimal multiplication: The multiplication operation in most
computers is accomplished using addition. As you have already seen, subtraction is done with an
adder; now let’s see how multiplication is done. Direct addition and partial products are two basic
methods for performing multiplication using addition. In the direct addition method, you add the
multiplicand a number of times equal to the multiplier. In the previous decimal example (8 × 3),
34 Chapter 2. Number Systems and Codes

Figure 2.5: Multiplication Example

three multiplicands are added: 8 + 8 + 8 = 24. The disadvantage of this approach is that it becomes
very lengthy if the multiplier is a large number. For example, to multiply 350 × 75, you must add
350 to itself 75 times. Incidentally, this is why the term times is used to mean multiply. When two
binary numbers are multiplied, both numbers must be in true (uncomplemented) form. The direct
addition method is illustrated in Example below adding two binary numbers at a time. Example:
Multiply the signed binary numbers: 01001101 (multiplicand) and 00000100 (multiplier) using the
direct addition method.
Solution:
Since both numbers are positive, they are in true form, and the product will be positive. The decimal
value of the multiplier is 4, so the multiplicand is added to itself four times as follows:

Figure 2.6: Multiplication Example

The sign of the product of a multiplication depends on the signs of the multiplicand and the
multiplier according to the following two rules:
• If the signs are the same, the product is positive.
• If the signs are different, the product is negative.
If the signs are different, the product is negative.
• Determine if the signs of the multiplicand and multiplier are the same or different. This
determines what the sign of the product will be
• Change any negative number to true (uncomplemented) form. Because most computers
store negative numbers in 2’s complement, a 2’s complement operation is required to get the
negative number into true form.
• Starting with the least significant multiplier bit, generate the partial products. When the
multiplier bit is 1, the partial product is the same as the multiplicand. When the multiplier bit
is 0, the partial product is zero. Shift each successive partial product one bit to the left.
• Add each successive partial product to the sum of the previous partial products to get the
final product.
• Add each successive partial product to the sum of the previous partial products to get the
final product.
 2.3 Binary Arithmetic 35

2.3.5 Binary division

Division in binary follows the same procedure as division in decimal, as Example below illustrates.
The equivalent decimal divisions are also given.

2.3.6 Signed Binary Numbers

There are several ways to represent signed binary numbers. In all cases, the MSB in a signed
number is the sign bit, that tells you if the number is positive or negative. Computers use a modified
2’s complement for signed numbers. Positive numbers are stored in true form (with a 0 for the sign
bit) and negative numbers are stored in complement form (with a 1 for the sign bit). For example,
the positive number 58 is written using 8-bits as:

Negative numbers are written as the 2’s complement of the corresponding positive number. The
negative number -58 is written as:

An easy way to read a signed number that uses this notation is to assign the sign bit a column weight
of -128 (for an 8-bit number). Then add the column weights for the 1’s. Example: Assuming that
the sign bit = -128, show that 11000110 = -58 as a 2’s complement signed number:

Solution: Column weights:

2.3.7 Floating Point Numbers

Floating point notation is capable of representing very large or small numbers by using a form of
scientific notation. A 32-bit single precision number is illustrated.

Example: Express the speed of light, c, in single precision floating point notation. (c = 0.2998 ×
109 )
 36 Chapter 2. Number Systems and Codes

Solution: In binary,
c = 000100011101111010010101110000002 . In scientific notation, c = 1.001110111101001010111000000×228
S = 0 because the number is positive. E = 28 + 127 = 15510 = 100110112
F is the next 23 bits after the first 1 is dropped.
In floating point notation,

2.3.8 Arithmetic Operations with Signed Numbers

Using the signed number notation with negative numbers in 2’s complement form simplifies addi-
tion and subtraction of signed numbers. Rules for addition: Add the two signed numbers. Discard
any final carries. The result is in signed form. Examples:

Note that if the number of bits required for the answer is exceeded, overflow will occur. This occurs
only if both numbers have the same sign. The overflow will be indicated by an incorrect sign bit.
Two examples are:

Rules for subtraction: 2’s complement the subtrahend and add the numbers. Discard any final
carries. The result is in signed form.
Repeat the examples done previously, but subtract:
 2.4 Hexadecimal Numbers 37

2’s complement subtrahend and add:

2.3.9 Brief Tutorial

1. Add the following binary numbers: 101012 and 1012
2. Perform the following binary subtractions: (a) 11012 - 1012 (b) 10112 - 102
3. Express the decimal number 239 as an 8-bit number in the sign-magnitude, 1’s complement,
and 2’s complement forms.
4. Determine the decimal value of this signed binary number expressed in sign-magnitude:
10010101
5. Convert the decimal number 3.248 × 104 to a single-precision floating-point binary number
6. Add the signed numbers: 01000100, 00011011, 00001110, and 00010010.
7. Perform each of the following subtractions of the signed numbers: (a) 00001000 - 00000011
(b) 10001000 - 11100010

2.4 Hexadecimal Numbers

Base=16 Hexadecimal digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Hexadecimal uses sixteen characters to represent numbers: the numbers 0 through 9 and the
alphabetic characters A through F.

2.4.1 Notation
In general, hexadecimal numbers are noted as: ...GHI.JKL...16 alternatively OX...GHI.JKL...
or even as: ...GHI.JKL...H .
Example: 1AC2.2A16 = 0x1AC2.2A = 1AC2.2AH

2.4.2 Hexadecimal to Binary

Large binary number can easily be converted to hexadecimal by grouping bits 4 at a time and
writing the equivalent hexadecimal character.
Example: Express 10010110000011102 in hexadecimal.
Solution: Group the binary number by 4-bits starting from the right. Thus: 10010110000011102 =
960E16
38 Chapter 2. Number Systems and Codes

A summary conversion table from hexadecimal digits to binary and decimal numbers is
shown in the table below:

Hexadecimal is a weighted number system. The column weights are powers of 16, which
increase from right to left.

Example: Express 1A2F16 in decimal.

Solution: Start by writing the column weights:
 2.5 Octal Numbers 39

2.5 Octal Numbers

Base=8 Hexadecimal digits: 0,1,2,3,4,5,6,7
Octal uses 8 characters to represent numbers: the numbers 0 through 7.

2.5.1 Notation
In general, Octal numbers are noted as: ...GHI.JKL...8 alternatively as ...GHI.JKL...O .
Example: 134.148 = 134.14O

2.5.2 Octal to Binary

Large binary number can easily be converted to Octal by grouping bits 3 at a time and writing
the equivalent Octal digit.
Example: Express 10010110000011102 in Octal.
Solution: Group the binary number by 3-bits starting from the right. Thus: 0010010110000011102 =
1130168
A summary conversion table from Octal digits to binary and decimal numbers is shown in the table
below:

Octal is also a weighted number system. The column weights are powers of 8, which increase from
right to left.

Example: Express 37028 in decimal.

Solution: Start by writing the column weights:
 40 Chapter 2. Number Systems and Codes

2.6 Digital Codes

Many specialized codes are used in digital systems. The Binary Coded Decimal (BCD), Gray Code
and ASCII code are some of the most commonly used ones.

2.6.1 Binary Coded Decimal (BCD) numbers

Binary coded decimal (BCD) is a weighted code that is commonly used in digital systems when it
is necessary to show decimal numbers such as in clock displays.
The table illustrates the difference between straight binary and BCD. BCD represents each
decimal digit with a 4-bit code. Notice that the codes 1010 through 1111 are not used in BCD.

Figure 2.7: Table adapted from (Floyd, 2015)

You can think of BCD in terms of column weights in groups of four bits. For an 8-bit BCD number,
the column weights are: 80 40 20 10 8 4 2 1.
Example: What are the column weights for the BCD number 1000 0011 0101 1001?
Solution:
8000 4000 2000 1000 800 400 200 100 80 40 20 10 8 4 2 1
Note that you could add the column weights where there is a 1 to obtain the decimal number. For
this case:
8000 + 200 + 100 + 40 + 10 + 8 + 1 = 835910

2.6.2 Gray Code

Gray code is an unweighted code that has a single bit change between one code word and the next
in a sequence. Gray code is used to avoid problems in systems where an error can occur if more
than one bit changes at a time.
Application: A shaft encoder is a typical application. Three IR emitter/detectors are used to
 2.6 Digital Codes 41

encode the position of the shaft. The encoder on the left uses binary and can have three bits change
together, creating a potential error. The encoder on the right uses gray code and only 1-bit changes,
eliminating potential errors.

Binary to gray code Conversion

Conversion between binary code and Gray code is sometimes useful. The following rules explain
how to convert from a binary number to a Gray code word:
• The most significant bit (left-most) in the Gray code is the same as the corresponding MSB
in the binary number.
• Going from left to right, add each adjacent pair of binary code bits to get the next Gray code
bit. Discard carries.
Example:
Convert the binary number 101102 to Gray code.
solution:

The gray code is: 11101

Gray code to Binary Conversion

To convert from Gray code to binary, use a similar method; however, there are some differences.
The following rules apply:
• The most significant bit (left-most) in the binary code is the same as the corresponding bit in
the Gray code.
• Add each binary code bit generated to the Gray code bit in the next adjacent position. Discard
carries.
For example, the conversion of the Gray code word 11011 to binary is as follows:

2.6.3 ASCII Codes

ASCII=American Standard Code for Information Interchange
ASCII is a code for alphanumeric characters and control characters. In its original form, ASCII
encoded 128 characters and symbols using 7-bits. The first 32 characters are control characters,
that are based on obsolete teletype requirements, so these characters are generally assigned to other
functions in modern usage.
In 1981, IBM introduced extended ASCII, which is an 8- bit code and increased the character
set to 256. Other extended sets (such as Unicode) have been introduced to handle characters in
languages other than English. The ASCII table can be downloaded from the Internet on the
following weblink:
https://www.asciitable.com/
 42 Chapter 2. Number Systems and Codes

2.7 Error detection Codes

2.7.1 Parity Method

The parity method is a method of error detection for simple transmission errors involving one bit
(or an odd number of bits). A parity bit is an “extra” bit attached to a group of bits to force the
number of 1’s to be either even (even parity) or odd (odd parity).
Example: The ASCII character for “a” is 1100001 and for “A” is 1000001. What is the correct bit
to append to make both of these have odd parity? Solution: The ASCII “a” has an odd number of
bits that are equal to 1; therefore the parity bit is 0. The ASCII “A” has an even number of bits that
are equal to 1; therefore the parity bit is 1.

2.7.2 Cyclic Redundancy Check (CRC) Method

The cyclic redundancy check (CRC) is an error detection method that can detect multiple errors
in larger blocks of data. At the sending end, a checksum is appended to a block of data. At the
receiving end, the check sum is generated and compared to the sent checksum. If the check sums
are the same, no error is detected.

The diagram below illustrates the CRC process:

2.7 Error detection Codes 43

Figure 2.8: Figure adapted from (Floyd, 2015)

 44 Chapter 2. Number Systems and Codes

2.8 Self-assessment Activity

 2.9 Reference 45

2.9 Reference
Refer to the chapter 2 in the prescribed book by Thomas Floyd
 3. Logic gates

Overview of the Study Unit

In this study unit we focus on the operation, application and troubleshooting of logic gates. The
relationship between the input and output waveforms of a gate using timing diagrams is thoroughly
covered.
To complete this unit, study Chapter 3 in your prescribed textbook: Thomas, L Floyd. Digital
Fundamentals.

Learning Outcomes of this Unit

After completing this study unit, you should be able to:
• identify the different types of logic gates available and discuss their functionality

Assessment criteria for this unit

• The various types of logic gates are identified and discussed.
• The different types of logic gates are identified and their digital functions explained to
standard procedures.
• The truth tables of the various logic gates are identified and drawn correctly

3.1 Introduction
Logic devices, as the name suggests, carry out logical functions. Logic devices all have inputs
and outputs, and their output states are dependent upon the conditions applied to the inputs. The
devices that carry out basic logic functions are often referred to as “gates”. In digital systems, there
are 3 basic logic gates (NOT, AND, OR gates). They are called basic because all the other logic
gates and logic circuits can be derived from their combination.
Logic gates are used as basic building blocks of any logic circuit. They are, therefore, present in
any logic circuit.
 48 Chapter 3. Logic gates

3.2 The NOT gate: Inverter

The inverter performs the Boolean NOT operation. When the input is LOW, the output is HIGH;
when the input is HIGH, the output is LOW.

The NOT operation (complement) is shown with an overbar. Thus, the Boolean expression for an
inverter is X = Ā.

3.2.1 Symbols
The following symbols are used to represent a Inverter:

Figure 3.1: Adapted from (Floyd, 2015)

Example: Given the input signal (waveform) A to an inverter, draw the output signal X

Figure 3.2: Adapted from (Floyd, 2015)

Solution:

Figure 3.3: (Floyd, 2015)

A group of inverters can be used to form the 1’s complement of a binary number:
 3.3 The AND gate 49

Figure 3.4: (Floyd, 2015)

3.3 The AND gate

The AND gate produces a HIGH output when all inputs are HIGH; otherwise, the output is LOW.
For a 2-input AND gate, the truth table is:

Figure 3.5: (Floyd, 2015)

The AND operation is usually shown with a dot between the variables but it may be implied (no
dot). Thus, the AND operation is written as X = A.B or X = AB

3.3.1 Symbols
The following symbols are used to represent an AND gate:

Figure 3.6: (Floyd, 2015)

 50 Chapter 3. Logic gates

3.3.2 Example:
Given the input signals (waveforms) A and B to an AND gate, draw the output signal X

Figure 3.7: (Floyd, 2015)

Solution:

Figure 3.8: (Floyd, 2015)

3.3.3 Application:
The AND operation is used in computer programming as a selective mask. If you want to retain
certain bits of a binary number but reset the other bits to 0, you could set a mask with 1’s in the
position of the retained bits.
Example: If the binary number 10100011 is ANDed with the mask 000011112 , what is the result?
Solution: 000000112 .

3.4 The OR gate

The OR gate produces a HIGH output whenever there is a high on any or all of the inputs.The OR
operation is written as X = A + B.

3.4.1 Symbols
The following symbols are used to represent a two-inputs OR gate:

Figure 3.9: (Floyd, 2015)

For a 2-input OR gate, the truth table is:

 3.5 The Derived Logic Gates 51

Figure 3.10: (Floyd, 2015)

3.4.2 Example:
Given the input signals (waveforms) A and B to an OR gate, draw the output signal X

Figure 3.11: (Floyd, 2015)

3.5 The Derived Logic Gates

Besides the basic logic gates (NOT, AND and OR), there exists a number of derived logic gates
which are simply the combinations of the basic logic gates. The NOT, AND and OR gates are
called basic because all the other logic gates are obtained from the combination of the NOT, AND
and OR gates. Such derived logic gates include:

3.5.1 The NAND gate

A NAND gate is in effect a combination of two gates, namely a NOT gate and an AND gate – hence
the name. It is illustrated as follows:

Figure 3.12: (Floyd, 2015)

 52 Chapter 3. Logic gates

Figure 3.13: (Floyd, 2015)

A NAND gate is written as follows: The truth table of a 2-inputs NAND gate can be derived as

follows:

3.5.2 The NOR gate

A NOR gate is in effect a combination of two gates, namely a NOT gate and an OR gate – hence
the name. It is illustrated as follows:

Figure 3.14: (Floyd, 2015)

A NOR gate is written as follows:

 3.5 The Derived Logic Gates 53

The truth table of a 2-inputs NOR gate can be derived as follows:

3.5.3 The XOR gate

An XOR gate is an exclusive or gate in which the output shows whether the inputs A and B are the
same or different. Therefore, if the two inputs have the same value, output X will be low. If the two
inputs have a different value, output X will be high. It is illustrated as follows:

Figure 3.15: (Floyd, 2015)

A XOR gate is written as follows:

The truth table of a 2-inputs XOR gate can be derived as follows:

 54 Chapter 3. Logic gates

The truth table above shows that we get a logic low output when the two inputs are the same,
and a logic high output when the inputs are different. It can therefore be used to test for equality.

3.5.4 The XNOR gate

An XNOR gate is an exclusive Nor gate, similar to the XOR gate in that its output shows whether
the inputs A and B are the same or different. However, its output is the exact inverted version of
the XOR gate’s output. It is ,therefore, a XNOR gate followed by a NOT gate. It is illustrated as
follows:

Figure 3.16: (Floyd, 2015)

A XNOR gate is written as follows:

The truth table of a 2-inputs XNOR gate can be derived as follows:

3.6 Integrated Circuits (ICs)

3.6.1 The 7400 IC
The 7400 IC in figure 3.17 is a Quad 2-input NAND Gate. That is consisting of 4-two input NAND
gates. Before this can be utilised, one has to apply power to the IC. Pin 14 is Vcc (5 volts) and pin
7 is GND (0Volts). We then apply either a high (5 volts) or a low (0 volts) to the inputs of the gate
and monitor the output by means of LEDs or a logic probe.
 3.6 Integrated Circuits (ICs) 55

Figure 3.17: A Quad 2 input NAND IC (Floyd, 2015)

3.6.2 The 7404 IC

The 7404 in figure 3.18. is a hex inverter containing 6 complement gates.

Figure 3.18: An IC of 6 NOT gates (Floyd, 2015)

3.6.3 The 7408 IC

The 7408 in figure 3.19. is a quad 2-input AND gate. As, the word "Quad" says, this IC has 4 gates
inside.
 56 Chapter 3. Logic gates

Figure 3.19: An IC of 4 AND gates (Floyd, 2015)

3.6.4 The 7432 IC

The 7432 in figure 3.20. is a quad 2-input OR gate. As, the word "Quad" says, this IC has 4 gates
inside.

Figure 3.20: An IC of 4 OR gates (Floyd, 2015)

3.6.5 The 7486 IC

The 7486 in figure 3.21. is a quad 2-input XOR gate. As, the word "Quad" says, this IC has 4 gates
inside.
 3.7 NOMENCLATURE OF ICs 57

Figure 3.21: An IC of 4 XOR gates (Floyd, 2015)

3.7 NOMENCLATURE OF ICs

When looking at an IC, you will see that there are often other letters around and between the
numbers. These letters all have meaning, as can be seen in the figure 3.22:

Figure 3.22: Nomenclature of ICs (Floyd, 2015)

Identifying the pin numbers.

DIP package in figure 3.23.
 58 Chapter 3. Logic gates

Figure 3.23: IC pin numbers reading (Floyd, 2015)

This numbering method is used for these packages:

• DIP (dual in-line package)

• DIL (dual in-line)
• SDIP (shrink dual in-line package)
• SO (small outline)
• SOIC (small outline integrated circuit)
• SOJ (small outline J-leaded)
• SOP (small outline package)
• SSOP (shrink small outline package)
• TSOP (thin small outline package)

The pins on an IC are not numbered, so we have to establish which pin is which, as in figure 3.29.
There are two common ways of identifying pin number 1. The first is a dot over pin 1, and the
second is a semicircle. When the IC is rotated so that the semicircle is on the left of the IC, the
bottom left pin under it is pin 1.
The pins are then numbered anti-clockwise.

3.8 Self-assessment Activity

1. For the set of input waveforms in figure 3.24 below, determine the output for the gate shown
and draw the timing diagram.
 3.9 my UNISA ACTIVITY: 59

Figure 3.24: Waveform diagram and Logic Gate (Floyd, 2015)

2. Assume that an enable signal has the waveform shown in figure 3.25 below; assume that
waveform b is also available. Devise a circuit that will produce an active-HIGH reset pulse
to the counter only during the time that the enable signal is LOW

Figure 3.25: Waveform diagram (Floyd, 2015)

3.9 my UNISA ACTIVITY:

Log on to myunisa and go to “Announcements”. Select the announcement that is study unit 3 and
do the self-assessment activity.

3.10 References:
Refer to the chapter “Logic gates” in the prescribed book, Digital fundamentals, by Floyd.

3.11 Experiments
3.11.1 Experiment 1
Objective:
To familiarise yourself with the operation of the basic logic elements of the Or gate and the
AND gate, as well as the use of the logic probe.
Components required:
7400 quad 2-input NAND gate
7402 quad 2-input NOR gate
AD2004 analogue/digital trainer
Logic probe

Procedure:
build the circuit as shown below:
60 Chapter 3. Logic gates

Remember to identify the pin numbers on the IC as indicated below. Once you have identified
pin 1, you proceed in an anti-clockwise direction as you number the pins. Example: The pin directly
to right of pin 1 would be pin 2, then pin 3, etc.

The wiring of the two circuits is critical and any mistake will cause an error to occur. The first IC to
the left is the 7400 quad 2-input NAND gate. if you refer to data sheets on the last page of this
guide, you will see that there are four NAND gates in a 7400 and we only need to use one. It is also
very important to note that the ICs need power, that is 5V on pin 14 (Vcc), shown in red, and 0V on
pin 7 (GND). Not all ICs are the same, so it is important to check the data sheets. The inputs to the
7400 are shown in blue (pins 13 and 12) and the output in green (pin 11).

The second IC to the right is a 7402 quad 2-input NOR gate. Again we must apply power to
pins 14 and 7 before the IC will function. The inputs to the IC are shown in yellow and the output
in purple. It is now time to build the circuit as shown, and to establish whether it is working using
the truth tables associated with these gates.
3.11 Experiments 61

Results of experiment:

Do your results correspond to the theory?...............

 62 Chapter 3. Logic gates

3.11.2 Experiment 2
Objective:

To familiarise yourself with the operation of a basic combinational circuit.

Components required:
Development board ICs: 74LS02
74LS00

Procedure:

Build the circuit for the following expression. In order to determine the input and output pins
to the gates, refer to the data sheets.

Results of experiment
Name: ..................................
Student no: ..................................
Date: ..................................
On the breadboard below, draw a wiring diagram to show how you built the circuit. (Work in pencil
in case you make a mistake.)

Complete the truth table below.

3.11 Experiments 63
 4. Boolean Algebra and Logic Simplification

Overview of the Study Unit

This study unit covers the laws, rules, and theorems of Boolean algebra and their application to
digital circuits. You will learn how to define a given circuit by means of a Boolean expression and
then to evaluate its operation. You will also learn how to simplify logic circuits using the methods
of Boolean algebra and Karnaugh maps.
To complete this unit, study Chapter 4 in your prescribed textbook: Thomas, L Floyd. Digital
Fundamentals.

Learning Outcomes of this Unit

After completing this study unit, you should be able to:
• Simplify digital systems using Boolean algebra, truth tables and Karnaugh maps.

Assessment criteria for this unit

• The laws of Boolean Algebra are explained and applied.
• The rules of De Morgan’s theorems are applied correctly.
• Conversions between SOP expressions and POS expressions are performed logically.
• Boolean expressions are solved and simplified using Boolean algebra.
• Boolean expressions are minimised by means of Karnaugh maps.

4.1 Introduction
Boolean algebra is the mathematics of digital systems. By applying Boolean algebra, we can take a
function and simplify it to a much smaller function. As in maths, there are rules in Boolean algebra
that need to be applied in order to solve functions. However, functions in Boolean algebra are not
exactly the same as maths functions.
 66 Chapter 4. Boolean Algebra and Logic Simplification

4.2 Boolean Operations and Expressions

4.2.1 Boolean addition
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 1

This is essentially an OR function.

4.2.2 Boolean multiplication

0.0 = 0
0.1 = 0
1.0 = 0
1.1 = 1

This is essentially an AND function

4.3 Rules of Boolean Algebra

The 12 basic rules of Boolean algebra for manipulating and simplifying Boolean expressions are
listed below. Rules 1 to 9 will be viewed in terms of their application to logic gates.
Rules 10 to 12 will be derived in terms of the simpler rules and the laws previously discussed.
1. A+0=A
2. A+1=1
3. A.0=0
4. A.1=A
5. A+A=A 6. A+Ā=1
7. A.A=A 8. A.Ā=0
9. Ā¯ = A
10. A+AB=A
11. A+ĀB = A+B
12. (A+B)(A+C)=A+BC

Rule 1: A+0 = A

A variable ORed with 0 is always equal to the variable. If the input variable A is 1, the output
variable X is 1, which is equal to A. If A is 0, the output is 0, which is also equal to A.

Rule 2: A+1 = 1

A variable ORed with 1 is always equal to 1. A 1 on the input to an OR gate produces a 1 on

the output, regardless of the value of the variable on the other input.
Rule 3: A.0 = 0

A variable ANDed with 0 is always equal to 0. Whenever one input to an AND gate is 0, the
output is 0, regardless of the value of the variable on the other input.
4.3 Rules of Boolean Algebra 67

Rule 4: A.1 = A

A variable ANDed with 1 is always equal to the variable. If A is 0, the output of the AND gate
is 0. If A is 1, the output of the AND gate is 1, because both inputs are now 1s.

Rule 5: A+A = A

A variable ORed with itself is always equal to the variable. If A is 0, then 0+0 = 0; and if A is
1, then 1+1 =1

Rule 6: A+Ā = 1

A variable ORed with its complement is always equal to 1. If A is 0, then 0+0 = 0+1 = 1. If A
is 1, then 1+1 = 1+0 = 1
Rule 7: A.A = A

A variable ANDed with itself is always equal to the variable. If A = 0, Then 0.0 = 0; and if A =
1, then 1.1 = 1.

Rule 8: A.Ā = 0

A variable ANDed with its complement is always equal to 0. Either A or will always be 0, and
when a 0 is applied to the input of an AND gate, the output will also be 0.

Rule 9: Ā¯ = A

The double complement of a variable is always equal to the variable. If you start with the
variable A and complement (invert) it once, you get Ā. If you then take Ā and complement (invert)
it, you get A, which is the original variable.

Rule 10: A+AB = A

This rule can be proved by applying the distributive law, rule 2 and rule 4 as follows:

A+AB = A.1 + AB = A (1+B) Factoring (distributive law)

= A.1 Rule 2 : (1+B) = 1
=A Rule 4: A.1 = A

Rule 11: A+ĀB = A + B

This rule can be proved as follows:

A+ĀB =(A + AB) + ĀB Rule 10: A = A+AB

= (AA+AB) + ĀB Rule 7: A = AA
= AA+AB+ AĀ+ ĀB Rule 8: adding Ā = 0
= (A+ Ā)(A + B) Factoring
= 1.(A+B) Rule 6:A+Ā = 1
= A+B Rule 4: drop the 1

Rule 12 :( A+B) (A+C) = A+BC

 68 Chapter 4. Boolean Algebra and Logic Simplification

This rule can be proved as follows:

For a further explanation, you can watch the video clip:

(A+B)(A+C) = AA+AC+AB+BC Distributive law

=A+AC+AB+BC Rule 7: AA = A
= A (1+C)+AB+BC Factoring (distributive law)
= A.1+AB+BC Rule 2: 1+C = 1
= A (1+B) +BC Factoring (distributive law)
= A.1+BC Rule 2: 1+B = 1
= A+BC Rule 4: A.1 = A

Boolean Algebra 1 – The Laws of Boolean Algebra by Computer Science (14:54) https://youtu.
be/EPJf4owqwdA

4.4 DE MORGAN’S THEOREMS

De Morgan, a mathematician who was acquainted with Boole, proposed two theorems that now
form an important part of Boolean algebra.

The complement of a product is equal to the sum of the individual complements.

Breaking the line changes the sign.X.Y = X +Y
The complement of the sum is equal to the product of the individual complements.
Join the line and change the sign. X +Y = X.Y
A video clip to consider adding here:
De Morgan’s Theorem | Understand circuit simplification | Boolean algebra basics by Practical
Ninjas (6:39) https://youtu.be/RrynEQ7sG5A

4.5 STANDARD FORMS OF BOOLEAN EXPRESSIONS

All Boolean expressions, regardless of their form, can be converted into one of two standard forms:
the sum-of-products form or the product-of-sums form.
The sum-of-products (SOP) form

A product term can be defined as a term consisting of the product (Boolean multiplication) of
literals (variables or their complements). When two or more product terms are summed by Boolean
addition, the resulting expression is a sum-of-products (SOP) form.

Some examples are

AB + ABC
ABC +CDE + BCD

The standard SOP form

Converting product terms to standard SOP

Each product term in an SOP expression that does not contain all the variables in the domain
can be expanded to standard form to include all the variables in the domain and their complements.
As stated in the following steps, a nonstandard SOP expression is converted into standard form
4.5 STANDARD FORMS OF BOOLEAN EXPRESSIONS 69

using Boolean algebra rule 6.

(A + Ā = 1), A variable added to its complement equals 1.

Step 1: Multiply each nonstandard product term by a term made up of the sum of a missing
variable and its complement. This results in two product terms. As you know, you can multiply
anything by 1 without changing its value.

Step 2: Repeat step 1 until all resulting product terms contain all the variables in the domain in
either complemented or uncomplemented form. In converting a product term to standard form, the
number of product terms is doubled for each missing variable.
See the following example

The product-of-sums (POS) form

A sum term is defined as a term consisting of the sum (Boolean addition) of literals (variables
or their complements). When two or more sum terms are multiplied, the resulting expression is a
product-of-sums (POS) form.
Some examples are:

The standard product-of-sums (POS) form

In some POS expressions, the sum terms do not contain all the variables in the domain of the
expression.
For example, the expression
(A + B̄ +C)(A + B + D̄)(A + B̄ + C̄ + D)
has a domain made up of the variables A, B, C and D. Note that the complete set of variables in the
domain is not represented in the first two terms of the expression, that is, D or D̄ is missing from
the first term and C or C̄ is missing from the second term.
A standard POS expression is one in which all the variables in the domain appear in each sum term
in the expression.
For example: (Ā + B̄ + C̄ + D̄)(A + B̄ +C + D)(A + B + C̄ + D)
Converting a sum term into a standard POS form
 70 Chapter 4. Boolean Algebra and Logic Simplification

Convert the following Boolean expression into a standard POS form:

(A + B̄ +C)(B̄ +C + D̄)(A + B̄ + C̄ + D)
The domain of this POS expression is A, B, C and D.
Take one term at a time. The first term, A + B̄ +C is missing variable D or D̄ or, so add DD̄ and
apply rule 12 as follows:

A + B̄ +C + DD̄ = (A + B̄ +C + D)(A + B̄ +C + D̄)

The second term, B̄ + C + D̄ , is missing variable, A or Ā, so add AĀ and apply rule 12 as
follows:
B̄ +C + D̄ + AĀ = (A + B̄ +C + D̄)(Ā + B̄ +C + D̄) The third term is already in standard form.
The standard POS form of the overall original expression is as follows:
(A + B̄ +C + D)(A + B̄ +C + D̄)(A + B̄ +C + D̄)(Ā + B̄ +C + D̄)(A + B̄ + C̄ + D)
Video clips to consider adding here.
For further explanations, you can watch the video clips below:
Sum of Products (Part 1) | SOP Form by Neso Academy (12:29)
https://youtu.be/xnLBbOYYnHM
SOP and POS Form Examples by Neso Academy (12:37)
https://youtu.be/K2cpJex0o_A

4.6 CONSTRUCTING A TRUTH TABLE FOR A LOGIC CIRCUIT

Once the Boolean expression for a given logic circuit has been determined, a truth table that shows
the output for all possible values of the input variables can be developed. The procedure requires
that you evaluate the Boolean expression for all possible com- binations of values for the input
variables. In the case of the circuit in figure 4.1, there are four input variables (A, B, C, and D) and
therefore sixteen (24 = 16) combinations of values are possible.

Figure 4.1: A combinational logic circuit example (Floyd, 2015)

Evaluating the Expression

To evaluate the expression A(B+CD), first find the values of the variables that make the expression
equal to 1, using the rules for Boolean addition and multiplication. In this case, the expression
equals 1 only if A=1 and B+CD=1 because
A(B+CD)=1.1=1
4.6 CONSTRUCTING A TRUTH TABLE FOR A LOGIC CIRCUIT 71

Now determine when the B+CD term equals 1. The term B+CD=1 if either B=1 or CD=1 or if both
B and CD equal 1 because
B+CD=1+0=1
B+CD=0+1=1
B+CD=1+1=1
To summarize, the expression A(B+CD)=1 when A=1 and B=1 regardless of the values of C and D
or when A=1 and C=1 and D=1 regardless of the value of B. The expression A(B+CD)=0 for all
other combinations of the variables.
Putting the Results in the Truth Table Format

The first step is to list the sixteen input variable combinations of 1s and 0s in a binary sequence
as shown in the table 4.1 below. Next, place a 1 in the output column for each combination of input
variables that was determined in the evaluation. Finally, place a 0 in the output column for all other
combinations of input variables. These results are shown in the truth table below.
 72 Chapter 4. Boolean Algebra and Logic Simplification

4.7 Karnaugh Maps

A Karnaugh map is similar to a truth table because it presents all the possible values of input
variables and the resulting output for each value.
Instead of being organised into columns and rows like a truth table, the Karnaugh map is an array
of cells in which each cell represents a binary value of the input variables. The cells are arranged in
such a way to enable the simplification of a given expression simply by grouping the cells properly.
Karnaugh maps can be used for expressions with two, three, four and five variables, but we will
discuss only 3-variable and 4-variable situations to illustrate the principles.
The number of cells in a Karnaugh map, as well as the number of rows in a truth table, is equal to
the total number of possible input variable combinations. For three variables the number of cells is
23 = 8, for four variables the number of cells is 24 = 16.
The 3-variable Karnaugh map

The 3-variable Karnaugh map is an array of eight cells, as shown in figure 4.2. In this case A, B
and C are used for the variables, although other letters could be used. The binary values of A and B
are along the left side (note the sequence) and the values of C are across the top.

The value of a given cell is the binary values of A and B on the left in the same row, combined
with the value of C at the top in the same column. For example, the cell in the upper left corner has
a binary value of 000, and the cell in the lower right corner has a binary value of 101.

Figure 4.2 shows the standard product terms that are represented by each cell in the Karnaugh
map. The 3-variable Karnaugh map

The 4-variable Karnaugh map

The 4-variable Karnaugh map is an array of 16 cells, as shown in figure 4.3.

The binary values of A and B are along the left side, and the values of C and D are across the top.
The value of a given cell is the binary values of A and B on the left in the same row, combined with
the binary values of C and D at the top in the same column.
For example, the cell in the upper right corner has a binary value 0010, and the cell in the lower
right corner has a binary value of 1010.
4.7 Karnaugh Maps 73

Figure 4.2: The Product terms for each cell in the 3-variables K-Map

Figure 4.3: 4-variables K-Map

Figure 4.4 shows the standard product terms that are represented by each cell in the 4-variable
Karnaugh map.

Karnaugh map SOP minimisation

As stated above, the Karnaugh map is used to simplify Boolean expressions to their minimum
form. A minimised SOP expression contains the fewest possible terms with the fewest possible
variables per term. Generally, a minimum SOP expression can be implemented with fewer logic
gates than a standard expression.

Mapping a standard SOP expression

For an SOP expression in standard form, a 1 is placed on the Karnaugh map for each product
term in the expression. Each 1 is placed in a cell corresponding to the value of a product term. For
example, for the product term ABC, a 1 goes in the 101 cell on the 3-variable map in figure 4.5.

When an SOP expression is completely mapped, there will be a number of 1s on the Karnaugh
map equal to the number of product terms in the standard SOP expression. The cells that do not
have a 1, are the cells for which the expression is 0. Usually, when working with SOP expressions,
74 Chapter 4. Boolean Algebra and Logic Simplification

Figure 4.4: The Product terms for each cell in the 4-variables K-Map

the 0s are left off the map. The following steps and the illustration in the figure below show the
mapping process.

Step 1: Determine the binary value of each product term in the standard SOP expression. After
some practice, you will usually be able to do the evaluation of terms mentally.
Step 2: As each product term is evaluated, place a 1 on the Karnaugh map in the cell that has the
same value as the product term.

Figure 4.5: Example of a 3-variables SOP K-Map simplification

Karnaugh map simplification of SOP expressions

The process that results in an expression containing the fewest possible terms with the fewest
possible variables is called minimisation.
After an SOP expression has been mapped, a minimum SOP expression is obtained by grouping
the 1s and determining the minimum SOP expression from the map.
Grouping the 1s
 4.8 Examples 75

You can group the 1s on the Karnaugh map according to the rules below by enclosing those
adjacent cells that contain 1s. The goal is to maximise the size of the groups and to minimise the
number of groups.
Rules:
(1) A group must contain 1, 2, 4, 8, or 16 cells, which are all powers of two. In the case of a
3-variable map, 23 =8 cells is the maximum group.
(2) Each cell in the group must be adjacent to one or more cells in that same group, but not all the
cells in the group need to be adjacent to each other.
(3) Always include the largest possible number of 1s in a group, as prescribed by rule 1.
(4) Each 1 on the map must be included in at least one group. The 1s already in a group can be
included in another group as long as the overlapping groups include non-common 1s.

Figure 4.6: Examples of groupings with more than one way to group

Examples of groupings are shown in figure 4.6. In some cases, there may be more than one way to
group the 1s into maximum groupings.
Determining the minimum SOP expression from the map

When all the 1s representing the standard product terms in an expression have been properly
mapped and grouped, the process of determining the resulting minimum SOP expression begins.
Rule:
Group the cells that have 1s. Each group of cells containing 1s creates one product term composed
of all the variables that occur in only one form (either uncomplemented or complemented) within
the group. Variables that occur both uncomplemented and complemented within the group are
eliminated. These are called contradictory variables.
Video clip to consider adding here.
Karnaugh Map (K’ Map) - Part 1 by Neso Academy (25:44)
https://youtu.be/FPrcIhqNPVo

4.8 Examples
4.8.1 Example 4.1
Use a Karnaugh map to minimise the following standard SOP expression:
AB̄C + ĀBC + ĀB̄C + ĀB̄C̄ + AB̄C̄
Solution
The binary values of the expression are:
101+011+001+000+100
 76 Chapter 4. Boolean Algebra and Logic Simplification

Map the standard SOP expression and group the cells as shown in figure 4.7.

Figure 4.7: K-Map simplification

Note the “wrap-around” 4-cell group that includes the top row and the bottom row of 1s. The
remaining 1 is absorbed in an overlapping group of two cells. The group of four 1s produce a single
variable term B̄.
This is determined by observing that within the group, B̄ is the only variable that does not change
from cell to cell.
The group of two 1s produces a 2-variable term ĀC. This is determined by observing that within
the group, Ā and C do not change from one cell to the next.
The product term for each group is shown. The resulting minimum SOP expression is:

B̄ + ĀC

This minimum expression is equivalent to the original standard expression.

4.8.2 Example 4.2

Use a Karnaugh map to minimise the following SOP expression:
B̄C̄D̄ + ĀBC̄D̄ + ABC̄D̄ + ĀB̄CD + AB̄CD + ĀB̄CD̄ + ĀBCD̄ + ABCD̄ + AB̄CD̄
Solution
The first term B̄C̄D̄ must be expanded into AB̄C̄D̄ and ĀB̄C̄D̄ to obtain the standard Sop expression,
which is then mapped; the cells are grouped as shown in figure 4.8:

Figure 4.8: Example 2 solution

Note that both groups exhibit “wrap-around” adjacency. The group of eight is formed because the
 4.9 Code Converters 77

cells in the outer columns are adjacent. The group of four is formed to pick up the remaining two
1s because the top and bottom cells are adjacent. The product term for each group is shown. The
resulting minimum SOp expression is D̄ + B̄C.
keep in mind that this minimum expression is equivalent to the original standard expression.
Please decide if you can use this video clip here.
Constructing Truth Tables for Combinational Logic Circuits by Engineers Academy (9:34) https:
//youtu.be/C4MdUQJIhSE

4.9 Code Converters

A code converter is used to convert code from one form to another.

A code converter typically has four binary inputs and four binary outputs. When an input code
is entered on a circuit, it must give a corresponding output code. As in the case of all designs, we
would begin with a truth table and then enter and group the 1s on four Karnaugh maps to obtain the
minimum expression.

4.9.1 Example 4.3

Based on the first principles, design a 5421 to 7421 code converter in the table below.

We start with the 5421 code (AbCD) and insert the codes for decimal numbers 0 to 9. The remaining
six unused codes are then placed in positions 10 to 15. We then place the corresponding 7421 code
in columns WXYZ. The last six codes do not exist, so we can insert “don’t-care” terms.

We then look at each column in the 7421 code individually, starting with column W. We insert
the “don’t-care” terms and the 1s, and group and obtain the expression. We repeat this for x, y and
Z in the K-maps in figure 4.9.
78 Chapter 4. Boolean Algebra and Logic Simplification

Figure 4.9: Solution step 1

 4.10 A Simple Design Question 79

After obtaining the minimised outputs on the Karnaugh map, the logic diagrams are drawn in figure
4.10.

Figure 4.10: Solution step 2

4.10 A Simple Design Question

As part of an aircraft’s functional monitoring system, a circuit is required to indicate the status of
the landing gears prior to landing.
A green LED display turns on if all three gears are properly extended when the “gear down” switch
has been activated in preparation for landing.
80 Chapter 4. Boolean Algebra and Logic Simplification

A red LED display turns on if any of the gears fail to extend properly prior to landing. When a
landing gear is extended, its sensors produce a LOW voltage. When a landing gear is retracted, its
sensor produces a HIGH voltage. Implement a circuit to meet this requirement.
First do a truth Table for this word example:

The truth table will look like this, remember that when the all gears are zero and extended
because we are working active LOW then the Green gear lights with a “1”.
When any of the gears fail to extend represented by HIGH voltage then the red LED lights in all
cases and we have a “1”.

Gren LED=ĀB̄C̄
Red LED=ĀB̄C + ĀBC̄ + ĀBC + AB̄C̄ + AB̄C + ABC̄ + ABC̄ + ABC
For the Red LED we will have to simplify the expression suing a Karnaugh map.

The result of the minimization is Red LED=A+B+C

The implementation in Logic circuit can be seen in the figure below.
 4.11 Summary 81

4.11 Summary
There is more than one way to realize a logical expression by means of a logic circuit. However,
there is cost associated with each realization in terms of space, price, power consumption etc.
Therefore, it is very important to simplify a logic expression to come up with its simplest possible
implementation circuit in order to optimize on the above-mentioned resources. This study unit
introduced you to the rules and theorems of Boolean logic simplification that are normally used to
achieve the simplest form possible of the logic circuit.

4.12 Self-assessment Activity

1. Using Boolean algebra, simplify the following expression:
ĀB + ĀBC̄ + ĀBCD + ĀBC̄D̄E

2. Use a Karnaugh map to find the minimum Sop form for the following expression:
ĀB̄C̄ + AB̄C̄ + ĀBC̄ + ABC̄

4.13 myUNISA Activity

Log on to myunisa and go to “Announcements”. Select the announcement that is study unit 4, and
explain the terms stated there. (This is a self-assessment activity– do not submit it to the university.)
 82 Chapter 4. Boolean Algebra and Logic Simplification

4.14 Reference
Refer to the chapter “Boolean algebra and logic simplification” in the prescribed book, Digital
fundamentals, by Floyd.

4.15 Experiment
Objective:

To take a practical problem and solve it logically, and to build a functional circuit to solve the
problem.
Task:

You are given the task of designing a circuit that will allow pilots to land their aircraft in bad
weather. The aircraft is fitted with a radio receiver that gives a 4-bit binary output code. When
the aircraft is very low, the code will be 00002 to 00102 ; when the aircraft is low, the code will be
00112 to 01012 ; when the aircraft is at the correct height, the code will be 01102 to 10012 ; when
the aircraft is high, the code will be 10102 to 11002 ; and when the aircraft is very high, the code
will be 11012 to 11112 . in the cockpit are four LEDs. When the aircraft is very low, LED a should
light up; when the aircraft is low, LEDs a and B should light up; at the correct height, all the LEDs
should light up; when the aircraft is high, LEDs C and D should light up; and when the aircraft is
very high, LED D should light up. Show all steps and give the logic diagrams.

Results of experiment

Name: ...................................

Student no: .............................

Date: ...................................
Complete and simplify the truth table using the karnaugh map.
4.15 Experiment 83

Results of experiment

Name: ...................................

Student no: ...................................

Date: ...................................

Draw the logic diagram of the circuit you built.

 5. Combinational logic circuits

Overview of the Study Unit

When logic gates are connected together to produce a specified output for certain specified com-
binations of input variables, and no storage is involved, the resulting circuit falls in the category
of combinational logic. In combinational logic, the output level is at all times dependent on the
combination of input levels. This study unit covers the analysis of combinational logic.
To complete this unit, study Chapter 5 in your prescribed textbook: Thomas, L Floyd. Digital
Fundamentals.

Learning Outcomes of this Unit

After completing this study unit, you should be able to:
• Design basic combinational logic circuits

Assessment criteria for this unit

• Basic combinational circuits are designed from wording.
• Truth tables are used in the design process and also to verify the logic.
• The diagrams of combinational logic are implemented from the truth tables.

5.1 GATE UNIVERSALITY: IMPLEMENTATION OF OTHER LOGIC GATES USING NAND

GATES ONLY
Gate universality is a very important concept as it allows the designer of logic circuti with limited
discrete components to still be able to achieve his/her design by using a combination of some basic
logic gates to achieve the same design outcome. Additionally, this has allowed for the design of
Field Programmable Gate Arrays (FPGAs) devices within the category of Programmable Logic
Devices (PLDs) that are often made either of an array of NAND gates only or an array of NOR
gates only making their manufacturing simpler.
86 Chapter 5. Combinational logic circuits

1. The NAND gate in figure 5.1 is wired in a particular manner that causes it to behave like a
NOT gate.

Figure 5.1: NOT gate implementation using a NAND gate

A.A = A

2. The arrangement in figure 5.2 works like an AND gate.

Figure 5.2: AND gate implementation using NAND gate

A.B = A.B

3. The arrangement in figure 5.3 behaves like an OR gate.

Figure 5.3: OR gate implementation using NAND gate

ĀB̄ = A + B

4. The arrangement in figure 5.4 behaves like a NOR gate.

 5.2 GATE UNIVERSALITY: IMPLEMENTATION OF OTHER LOGIC GATES USING NOR
GATES ONLY 87

Figure 5.4: NOR gate implementation using NAND gate

ĀB̄ = Ā¯ + B̄¯ = A + B

5.2 GATE UNIVERSALITY: IMPLEMENTATION OF OTHER LOGIC GATES USING NOR

GATES ONLY
1. Figure 5.5 also behaves like a NOT gate.

Figure 5.5: NOT gate implementation using NOR gate

A + A = Ā
2. Figure 5.6 behaves like an OR gate.

Figure 5.6: OR gate implementation using NOR gate

 88 Chapter 5. Combinational logic circuits

A + B = (A + B)

3. Figure 5.7 behaves like an AND gate.

Figure 5.7: AND gate implementation using NOR gate

Ā + B̄ = Ā¯ .B̄¯ = A.B

4. Figure 5.8 behaves like a NAND gate.

Figure 5.8: NAND gate implementation using NOR gate

Ā + B̄ = Ā¯ .B̄¯ = A.B

5.3 Examples
5.3.1 Example 5.1
Convert the following expression to NAND gates only:
F = A.B̄ + C̄D
 5.3 Examples 89

Place a double bar

A.B̄ + C̄D
Applying De Morgan’s theorem:
A.B.C.D
This can be implemented in figure 5.9 with NAND gates only.

Figure 5.9: Solution to example 1

5.3.2 Example 5.2: Solved example

Design a logic circuit to implement the operation specified in the truth table of Table 5.3.2.

Inputs Output Product Term

A B C X
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1 𝐴̅𝐵𝐶
1 0 0 0
1 0 1 1 𝐴𝐵̅𝐶
1 1 0 1 𝐴𝐵𝐶̅
1 1 1 0

Given Truth table

Solution:
Notice that X = 1 for only three of the input conditions. Therefore, the logic expression is
X = ĀBC + AB̄C + ABC̄
The logic gates required are three inverters, three 3-input AND gates and one 3-input OR gate. The
logic circuit is shown in Figure 5.3.2
 90 Chapter 5. Combinational logic circuits

Corresponding combinational logic circuit

This short video clip provides a summary explanation ofthe basic concepts of combinational logic.

Introduction to Combinational Circuits by Tutorials Point (India) Ltd. (11:05) https://youtu.

be/Pjw8t-bGSBo

5.4 Summary

In the previous two study units (3 and 4), logic gates are discussed on an individual basis and in
simple combinations. You were introduced to SOP and POS implementations, which are basic
forms of combinational logic. When logic gates are connected together to produce a specified
output for certain specified combinations of input variables, with no storage involved, the resulting
circuit is in the category of combinational logic. In combinational logic, the output level is at all
times dependent on the combination of input levels.

5.5 Activities

5.5.1 Activity 5.1

Write the output expression for the circuit in figure 5.10 below:
 5.6 myUNISA ACTIVITY 91

Figure 5.10: Activity 5.10

5.5.2 Activity 5.2

Implement the logic circuit in the figure above using only NAND gates.

5.6 myUNISA ACTIVITY

Log on to myunisa, go to “Announcements”, and select the announcement that is study unit 5.
Answer the question given there. (This is a self-assessment activity – do not submit it to the
university.)

5.7 Reference
Refer to the chapter “Combinational logic analysis” in the prescribed book, Digital fundamentals,
by Floyd.

5.8 Experiment
Objective:

To demonstrate how basic gates can be used to implement any logic function, and to show
how Boolean algebra and Karnaugh maps can be used to reduce logic circuits to their minimum
configuration.
Procedure:

Show how the expression below can be constructed using NAND gates only.

F = A.B +C.D + (Ā +C)

Write the modified expression below:

F = ............................

Results of experiment

On the breadboard below, draw a wiring diagram to show how you built the circuit. (Work in
pencil in case you make a mistake.) F = ............................
92 Chapter 5. Combinational logic circuits

Complete the truth table below:

 6. Functions of combinational logic

Overview of the Study Unit

In this study unit several types of combinational logic circuits are introduced, including AND-OR-
invert ICs, adders, comparators, decoders, encoders, code converters, multiplexers (data selectors),
demultiplexers, and parity generators/checkers.
To complete this unit, study Chapter 6 in your prescribed textbook: Thomas, L Floyd. Digital
Fundamentals.

Learning Outcomes of this Unit

After completing this study unit, you should be able to:
• Apply combinational logic to build basic digital systems and to apply functionality.

Assessment criteria for this unit

• Binary adders are used to perform binary additions.
• Comparators are used to differentiate logic.
• Multiplexers are utilised to do many-to-one and one-to-many conversions.
• Code converters are used to convert from BCD code to other digital codes.

6.1 Basic Adders

Please see if you can add this video clip here:
Before continuing with this section, watch the video clips below:
Digital Electronics - Combinational Logic - Adder Circuit by Penguin Tutor (10:08) https:
//youtu.be/CaPVcCepJP8
Video Explanation: In this video, the construction of the half and full-adders using a combination
of logic gates (One XOR and one AND gate for the half-adder circuit and 2 XOR gate, 2 AND
gates and one OR gate for the full adder respectively)is provided. One very important aspect in
 94 Chapter 6. Functions of combinational logic

this video is that, the explanation links the construction of the two adder circuits to the theoretical
knowledge of binary addition.
What is Full Adder ?| Learn under 5 min | Adder circuit | Digital Circuit | DE.19 by Practical
Ninjas (3:46) https://youtu.be/m0C3-JWWvcc
Video Explanation: In this video, the Karnaugh map is used to design the logic circuits for the
half-adder as well as for the full-adder going from the truth table of each one respectively. The
half-adder and the full-adder’s truth table are derived from the basic knowledge of binary addition.
In the video, basic practical consideration on how to go about using adders is provided.

6.1.1 Half-adder
The basic rules for addition are:

0+0=0
0+1=1
1+0=1
1 + 1 = 0 (carry 1)

Adders are very important in many types of digital systems in which numerical data are pro-
cessed.
Logic symbol for a half-adder in figure 6.1

Figure 6.1: Half-Adder (Floyd, 2015)

Where A and B = input variables

∑ = the Sum
Cout = out put carry
Half-adder truth table:

From the truth table above you will need an exclusive-OR gate for the sum and an AND gate
for the carry-out. Half-adder logic diagram in figure 6.2
 6.1 Basic Adders 95

Figure 6.2: Half-adder logic circuit diagram (Floyd, 2015)

6.1.2 Full-Adder
Logic symbol for a full-adder in figure 6.3

Figure 6.3: Full Adder Block Diagram (Floyd, 2015)

Where
=
∑ SUM
Cout = Out put Carry
CIN = Input Carry
A and B = input variables
Full-adder truth table

In order to add three bits, we combine two XOR gates as in figure 6.4.
The sum part will be equal to ∑ = (AXORB)XORCin
96 Chapter 6. Functions of combinational logic

The carry-out component is (A XOR B).C + (A.B)

Figure 6.4: Full Adder Internal logic Circuit (Flod, 2015)

Two half-adders to make a full-adder as in figure 6.5

Figure 6.5: Arrangement of two half-adders to form a full-adder (Floyd, 2015)

Example 6.1

Design of a full-adder (SOP)

STEP 1: Truth table:
6.1 Basic Adders 97

STEP 2:

∑ = P̄Q̄CIN + P̄QC¯IN + PQ̄C¯IN + PQCIN

Co = P̄QCIN + PQ̄CIN + PQCIN + PQCIN

STEP 3:

Result of minimisation =
∑ = P̄Q̄CIN + P̄QCIN + PQ̄CIN + PQCIN
 98 Chapter 6. Functions of combinational logic

6.2 Parallel Adders

Please search for a relevant video clip to add here.

4 Bit Parallel Adder using Full Adders by Neso Academy (10:27)
https://youtu.be/NO7Gt8IDSGA
Video Explanation: In this video tutorial, the focus is on how to combine multiple full adders (4
in this case) to form a single larger circuit that is able to perform the sum of two numbers with four
bits each forming this way a parallel adder circuit. The 74LS283 4-bit parallel adder
An example of a 4-bit parallel adder such as that in figure 6.6 that is available in IC form is the
74LS283. For the 74LS283, VCC is pin 16 and ground is pin 8, which is a standard configuration.
The pin diagram and logic symbol for this device are shown, with pin numbers in parentheses on
the logic symbol.
6.2 Parallel Adders 99

Figure 6.6: 4-bit parallel adder (Floyd, 2015)

Cascading of two 4-bit adders to form an 8-bit adder

The 4-bit parallel adder can be expanded to handle the addition of two 8-bit numbers by using
two 4-bit adders in parallel, as is shown in figure 6.7. The carry input of the low-order adder (C0 ) is
connected to ground, because there is no carry into the least significant bit position, and the carry
output of the low-order adder is connected to the carry input of the high-order adder, as is shown in
figure 6.7. The process is known as cascading.

Note that in this case, the output carry is designated C8 , because it is generated from the 8-
bit position. The low-order adder is the one that adds the lower or less significant four bits to the
numbers, and the high-order adder is the one that adds the higher or more significant four bits to
the 8-bit numbers.
 100 Chapter 6. Functions of combinational logic

Figure 6.7: Cascading of two-bit adders to form an 8-bit adder (Floyd, 2015)

Cascading of four 4-bit adders to form a 16-bit adder

Similarly, four 4-bit adders can be cascaded to handle two 16-bit numbers, as shown in figure
6.8. Note that the output carry is designated C16 because it is generated from the 16th bit position.

Figure 6.8: Cascading of four 4-bit adders to form a 16-bit adder (Floyd, 2015)

6.2.1 Examples

Example 6.2

Show how two 74LS283 adders can be connected to form an 8-bit parallel adder.
Show output bits for the following 8-bit numbers:
Solution in figure 6.9
 6.3 COMPARATORS 101

Figure 6.9: Cascading of 2 of 74LS283 to form an 8-bit parallel adder (Floyd, 2015)

6.3 COMPARATORS

The basic function of a comparator is to compare the magnitudes of two binary quantities to
determine the relationship between those quantities. In its simplest form, a comparator circuit
determines whether two numbers are equal.
Equality
The exclusive-NOR gate can be used as a basic comparator because its output is a 0 if the two input
bits are not equal and a 1 if the input bits are equal. The figure 6.10 below shows the exclusive-NOR
gate as a 2-bit comparator.

Figure 6.10: Use of an XNOR gate as a 2-bit Comparator (Floyd, 2015)

In order to compare binary numbers containing two bits each, an additional exclusive-NOR gate is
necessary. The two least significant bits (LSBs) of the two numbers are compared by gate G1 and
the two most significant bits (MSBs) are compared by gate G2 as shown in figure 6.11 below. If the
two numbers are equal, their corresponding bits are the same, and the output of each exclusive-NOR
gate is a 1. If the corresponding sets of bits are not equal, a 0 occurs on that exclusive-NOR gate
output.
102 Chapter 6. Functions of combinational logic

Figure 6.11: 2-bits comparator design (Floyd, 2015)

In order to produce a single output indicating an equality or inequality of two numbers, an AND gate
can be combined with XNOR gates, as shown in figure 6.11. The output of each exclusive-NOR
gate is applied to the AND gate input. When the two input bits for each exclusive-NOR gate are
equal, the corresponding bits of the numbers are equal, producing a 1 on both inputs to the AND
gate and thus a 1 on the output. Thus, the output of the AND gate indicates equality (1) or inequality
(0) of the two numbers.

Inequality
In addition to the equality output, many IC comparators provide additional outputs that indicate
which of the two binary numbers being compared is the larger. That is, there is an output that
indicates when number A is greater than number B (A > B), and an output that indicates when
number A is less than number B (A < B), as shown in the logic symbol for a 4-bit comparator in
figure 6.12 below.

Figure 6.12: 4-bits comparator block diagram (Floyd, 2015)

To determine an inequality of binary numbers A and B, you first examine the highest-order bit in
each number. The following conditions are possible:
(1) If A3 = 1 and B3 = 0, number A is greater than number B.
(2) If A3 = 0 and B3 = 1, number A is less than number B.
(3) If A3 = B3, then you must examine the next lower bit position for an inequality.

These three operations are valid for each bit position in the numbers. The general procedure
used in a comparator is to check for an inequality in a bit position, starting with the highest-order
bits (MSBs). When such an inequality is found, the relationship between the two numbers is
established, and any other inequalities in lower-order bit positions must be ignored; the highest-
6.3 COMPARATORS 103

order indication must take precedence.

For more information, please watch the following video clip:
https://www.youtube.com/watch?v=hoSrJv47RaI
Video Explanation: In this video, the design of a logic circuit able to compare the magnitudes of
two binary numbers (A and B). There are three possible outcomes (either A > B, A < B or A=B).
The outcome of comparison sets one of the 3 output pins (A>B output pin or the A < B output pin
or the A=B output pin) and clear the other pins.

Example 6.3

Determine the A = B, A > B and A < B outputs for the input numbers shown on the comparator in
figure 6.13 below.

Figure 6.13: 4-bits comparator block diagram (Floyd, 2015)

The number on the A inputs is 0110 and the number on the B inputs is 0011. The A > B output is
high and the other outputs are low.
The 74LS85 4-bit magnitude comparator
The 74LS85 is a comparator that is also available in other IC families. The pin diagram and logic
symbol are shown in figure 6.14 below. Note that this device has all the inputs and outputs of
the generalised comparator previously discussed and, in addition, has three cascading inputs: A <
B, A = B, A > B. These inputs allow several comparators to be cascaded for comparison of any
number of bits greater than four. To expand the comparator, the A < B, A = B, and A> B outputs
of the lower-order comparator are connected to the corresponding cascading inputs of the next
higher-order comparator. The lowest-order comparator must have a HIGH on the A=B input and
LOWs on the A < B and A < B and A > B inputs.
 104 Chapter 6. Functions of combinational logic

Figure 6.14: Comparator IC & diagram (floyd, 2015)

6.4 DECODERS
Please visit the following video clip for more information:
Decoder Basics and 2 to 4 Decoder, Combinational circuit in Digital Electronics, Decoder by
Engineering Funda (11:10) https://youtu.be/TJ0EG5fmTWM

A decoder is a digital circuit that detects the presence of a specified combination of bits (code)
on its inputs and indicates the presence of that code by a specified output level. In its general form,
a decoder has n input lines to handle n bits, and from one to 2n output lines to indicate the presence
of one or more n-bit combinations. In this section, several decoders are introduced.
The basic binary decoder
Suppose you need to determine when a binary 1001 occurs on the inputs of a digital circuit. An
AND gate can be used as the basic decoding element because it produces a HIGH output only when
all of its inputs are HIGH. Therefore, you must make sure that all the inputs to the AND gate are all
HIGH when the binary number 1001 occurs; this can be done by inverting the two middle bits (the
0s) as shown in figure 6.15 below.

Figure 6.15: Basic Binary Decoder Example (Floyd, 2015)

You should verify that the output is 0 except when A0 = 1, A1 = 0 and A3 = 1 are applied to
the inputs. A0 is the LSB and A3 is the MSB. When a binary number or other weighted code is
 6.4 DECODERS 105

represented in this study guide, the LSB is the right-most bit in a horizontal arrangement and the
topmost bit in a vertical arrangement, unless otherwise specified.
If a NAND gate is used in place of the AND gate in the figure above, a low output will indicate the
presence of the proper binary code, which in this case is 1001.

6.4.1 Examples

Example 6.4

Determine the logic required to decode the binary number 1011 by producing a HIGH level on the
output.
Solution
The decoding function can be formed by complementing only the variables that appear as 0 in the
desired binary number, as follows:
X = A3 .A2 .A1 .A0 (1011)

This function can be implemented by connecting the true (uncomplemented) variables A0 , A1 ,

and A3 directly to the inputs of an AND gate, and inverting the variable A2 before applying it to the
AN D gate input. The decoding logic is shown in figure 6.16 below.

Figure 6.16: (Floyd, 2015)

The 4-bit decoder

In order to decode all possible combinations of four bits, sixteen decoding gates are required
(24 = 16). This type of decoder is commonly called either a 4-to-16-line decoder because there
are four inputs and sixteen outputs, or a 1-of-16 decoder, because for any given code on the inputs,
one of the sixteen outputs is activated. A list of the sixteen binary codes and their corresponding
decoding functions is given in the table below.
106 Chapter 6. Functions of combinational logic

Table taken from (Floyd, 2015)

If an active-LOW output is required for each decoded number, the entire decoder can be im-
plemented with NAND gates and inverters. In order to decode each of the sixteen binary codes,
sixteen NAND gates are required (AND gates can be used to produce active-HIGH outputs).

In figure 6.17 below, a logic symbol for a 4-to-16-line (1-of-16) decoder with active-LOW outputs
is shown. The BIN/DEC label indicates that a binary input makes the corresponding decimal output
active. The input labels 8, 4, 2 and 1 represent the binary weights of the input bits (23 , 22 , 21 , 20 )
6.4 DECODERS 107

Figure 6.17: 4-to-6-line decoder (Floyd, 2015)

The 74HC154 1-of-16 decoder

The 74HC154 is a good example of an IC decoder. The Logic symbol is shown in figure 6.18 below.
There is an enable function (EN ) provided on this device, which is implemented with a NOR gate
used as a negative-AND. A LOW level on each chip select input, CS1 and CS2 , is required in order
to make the enable gate output(EN) HIGH. The enable gate output is connected to an input of each
NAND gate in the decoder, so it must be HIGH for the NAND gates to be enabled. If the enable
gate is not activated by a LOW on both inputs, then all sixteen decoder outputs (Y) will be HIGH
regardless of the states of the four input variables, A0 , A1 , A2 , A3 .
108 Chapter 6. Functions of combinational logic

Figure 6.18: Pin diagram and logic symbol for the 74HC154 1-of-16 decoder (Floyd, 2015)

Example 6.5

A certain application requires that a 5-bit number be decoded. Use 74HC154 decoders to implement
the logic. The binary number is represented by the format A4 , A3 , A2 , A1 , A0 .
Solution
Since the 74HC154 can handle only four bits, two decoders must be used to decode five bits. The
fifth bit, A4 is connected to the chip select inputs CS1 and CS2 inputs of the other decoder, as shown
in figure 6.19 below. When the decimal number is 15 or less, A4 = 0 , the low-order decoder is
enabled, and the high-order decoder is disabled. When the decimal number is greater than 15,
A4 = 1 so A4 = 0, the high-order decoder is enabled, and the low-order decoder is disabled.
 6.5 Encoders 109

Figure 6.19: Using the 74HC154 to decode 5-bits (Floyd, 2015)

The BCD-to-7-segment decoder

The BCD-to-7-segment decoder accepts the BCD code on its inputs and provides outputs to drive
7-segment display devices to produce a decimal read-out. The logic diagram for a basic 7-segment
decoder is shown in figure 6.20 below.

Figure 6.20: BCD-to-7-segment decoder (Floyd, 2015)

6.5 Encoders
The following video clip provides some more information about this section:
Combinational Logic - Encoders by David Williams (12:40) https://youtu.be/iYrVc1Y3dO8

An encoder is a combinational logic circuit that essentially performs a “reverse” decoder

function. An encoder accepts an active level on one of its inputs representing a digit, such as a
110 Chapter 6. Functions of combinational logic

decimal or octal digit, and converts it to a coded output, such as BCD or binary. Encoders can also
be devised to encode various symbols and alphabetic characters. The process of converting from
familiar symbols or numbers to a coded format is called encoding.

The decimal to BCD encoder

This type of encoder has ten inputs – one for each decimal digit – and four outputs corresponding
to the BCD code, as shown in figure 6.21. This is a basic 10-line-to-4-line encoder.

The BCD (8421) code is listed in the table below. From this table you can determine the
relationship between each BCD bit and the decimal digits in order to analyse the logic. For instance,
the most significant bit of the BCD code, A3 is always a 1 for decimal digits 8 or 9. An OR
expression for bit A3 in terms of the decimal digits can therefore be written as
A3 = 8 + 9

Figure 6.21: 10-line-to-4-line encoder (Floyd, 2015)

6.5 Encoders 111

Bit A2 is always a 1 for decimal digits 4, 5, 6 or 7, and can be expressed as an OR function as

follows:
A2 = 4 + 5 + 6 + 7
Bit A1 is always a 1 for decimal digits 2, 3, 6 or 7, and can be expressed as
A1 = 2 + 3 + 6 + 7
Finally, A0 is always a 1 for decimal digits 1, 3, 5, 7 or 9. The expression for A0 is
A0 = 1 + 3 + 5 + 7 + 9
Now let’s implement the logic circuitry required for encoding each decimal digit to a BCD code by
using the logic expressions just developed. It is simply a matter of ORing the appropriate decimal
digit input lines to form each BCD output. The basic encoder logic resulting from these expressions
is shown in figure 6.22 below.

Figure 6.22: Circuit for a 10-line-to-4-line encoder (Floyd, 2015)

The basic operation of the circuit in the figure above is as follows: When a HIGH appears on one
of the decimal digit input lines, the appropriate levels occur on the four BCD output lines. For
instance, if the input line 9 is HIGH (assuming all other input lines are LOW), this condition will
produce a HIGH on outputs A0 and A3 and LOW’s on outputs A1 and A2 , which is the BCD code
(1001) for decimal 9.

The 74HC147 decimal-to-bcd encoder

The 74HC147 is a priority encoder with active-low inputs (0)m for decimal digits 1 to 9 and
active-low BCD outputs, as indicated in the logic symbol in figure 6.23. A BCD zero output is
represented when none of the inputs is active. The device pin numbers are in parentheses.
 112 Chapter 6. Functions of combinational logic

Figure 6.23: 74HC147 decimal-to-BCD encoder (Floyd, 2015)

6.6 MULTIPLEXERS

For more information, the following video clip is recommended:

Combinational Logic - Multiplexers by David Williams (18:48)
https://youtu.be/kpGEL7Xynjc

A multiplexer (MUX) is a device that allows digital information from several sources to be
routed onto a single line for transmission over that line to a common destination. The basic multi-
plexer has several data-input lines and a single output line. It also has data-select inputs, which
permit digital data on any one of the inputs to be switched to the output line. Multiplexers are also
known as data selectors.

After completing this section, you should be able to

• explain the basic operation of a multiplexer
• describe the 74HC157 multiplexer
• use the multiplexer as a logic function generator
A logic symbol for a 4-input multiplexer (MUX) is shown in figure 6.24. Note that there are two
data-select lines because with two select bits, any one of the four data-input lines can be selected.
6.6 MULTIPLEXERS 113

Figure 6.24: 1-of-4 data selector multiplexer (Floyd, 2015)

In figure 6.24, a 2-bit code on the data-select (S) inputs will allow the data on the selected data input
to pass through to the data output. If a binary 0 (S1 = 0 and S0 = 0) is applied to the data-select
lines, the data on input D0 appear on the data-output line. If a binary 1 (S1 = 0 and S0 = 1) is
applied to the data-select lines, the data on input D1 appear on the data output. If a binary 2 (S1 = 1
and S0 = 0) is applied, the data on D2 appear on the output. If a binary 3 (S1 = 1 and S0 = 1) is
applied, the data on D3 are switched to the output line. A summary on this operation is given in the
table below.

Now let’s look at the logic circuitry required to perform this multiplexing operation. The data
output is equal to the state of the selected data input. We can therefore derive a logic expression for
the output in terms of the data input and the select inputs.

The total expression for the data output is

Y = D0 S¯1 S¯0 + D1 S¯1 S¯0 + D2 S1 S0 + D3 S1 S0 (6.1)

The implementation of this equation requires four 3-input AND gates, a 4-input OR gate and two
inverters to generate the complements of S1 and S0 , as shown in figure 6.25. Because data can be
selected from any of the input lines, this circuit is also referred to as a data selector.
 114 Chapter 6. Functions of combinational logic

Figure 6.25: Implementation circuit of equation 6.1 (Floyd, 2015)

6.6.1 Examples
Example 6.6
The data-input and data-select waveforms in figure 6.26 are applied to the multiplexer in figure
6.25. Determine the output waveform in relation to the inputs.

Figure 6.26: Example 1 input waveforms (Floyd, 2015)

Solution
The binary state of the data-select inputs during each interval determines which data input is
selected. Note that the data-select inputs undergo a repetitive binary sequence 00, 01, 10, 11, 00,
01, 10, 11 and so on. The resulting output waveform is shown in figure 6.26.
6.6 MULTIPLEXERS 115

The 74HC157 quad 2-input data selector/multiplexer

The 74HC157 as well as its LS version consists of four separate 2-input multiplexers. Each of the
four multiplexers shares a common data-select line and a common enable. Because there are only
two inputs to be selected in each multiplexer, a single data-select input is sufficient, as can be seen
in figure 6.27.

Figure 6.27: Pin diagram and logic symbol for the 74HC157 quadruple 2-input data selec-
tor/multiplexer (Floyd, 2015)

Demultiplexers

for extra information on this section, kindly watch the following video clip
Combinational Logic - Demultiplexers by David Williams (8:19)
https://youtu.be/OEAOgDIgPbM
A demultiplexer (DEMUX) basically reverses the multiplexing function. It takes digital information
from one line and distributes it to a given number of output lines. For this reason, the demultiplexer
is also known as a data distributor. As you will learn, decoders can also be used as demultiplexers.

After completing this section, you should be able to

• Explain the basic operation of a demultiplexer

• Describe how the 74HC154 4-line-to-16-line decoder can be used as a demultiplexer

Figure 6.28 shows a 1-line-to-4-line demultiplexer (DEMUX) circuit. The data-input line goes to
all the AND gates. The two data-select lines enable only one gate at a time, and the data appearing
on the data-input line pass through the selected gate to the associated data-output line.
 116 Chapter 6. Functions of combinational logic

Figure 6.28: 1-line-to-4-line demultiplexer (Floyd, 2015)

6.7 Examples
6.7.1 Example 6.7
The serial data-input waveform (data in) and data select inputs (S0 and S1) are shown in figure 6.29.
Determine the data-output waveforms on D0 through D3 for the demultiplexer in figure 6.28.

Figure 6.29: Example input data waveforms (Floyd, 2015)

 6.8 Summary 117

Solution
Note that the select lines go through a binary sequence so that each successive input bit is routed to
D0 , D1 , D2 , D3 in sequence, as shown by the output waveforms in figure 6.29.
The 74HC154 demultiplexer
We have already discussed the 74HC154 decoder in its application as a 4-line-to-16-line decoder.
This device and other decoders can also be used in demultiplexing applications. The logic symbol
for this device when used as a demultiplexer is shown in figure 30. In demultiplexer applications,
the input lines are used as the data-select lines. One of the chip select inputs is used as the data-input
line, with the other chip select input held LOW to enable the internal negative-AND gate at the
bottom of the diagram.

Figure 6.30: The 74HC154 decoder used as a demultiplexer (Floyd, 2015)

6.8 Summary

In this study unit, various types of common logic components that purely consist of a combina-
tion of logic gates were studied one by one. These logic circuits included adders, comparators,
decoders, encoders, code converters, multiplexers (data selectors), demultiplexers, and parity gener-
ators/checkers. This study unit studies each of these logic circuit from its truth table, deducts its
boolean logic expression, applies the rules and theorems of Boolean logic simplification as studied
in study unit 5 to obtain the simplest SOP or POS form of the logic circuit’s boolean expression,
and realises the logic circuit itself.
 118 Chapter 6. Functions of combinational logic

6.9 Activity 6.1

BCD numbers are applied sequentially to the BCD-to-decimal decoder in figure 6.31 below. Draw
a timing diagram, showing each output in the proper relationship with others and with the inputs.

Figure 6.31: BCD-to-decimal decoder (Floyd, 2015)

6.9.1 Activity 6.2

A 7-segment decoder/driver drives the display in figure 6.32 below. If the waveforms are applied as
indicated, determine the sequence of digits that appears on the display.

Figure 6.32: Activity 6.2 (Floyd, 2015)

6.10 myUNISA ACTIVITY

Log on to myUnisa, go to “Announcements”, and select the announcement that is study unit 6.
Explain the terms given there. (This is a self-assessment activity – do not submit it to the University.)
 6.11 REFERENCE 119

6.11 REFERENCE
Refer to the chapter “Functions of combinational logic” in the prescribed book by Floyd.
 7. And-or-invert (AOI) ICs for implementing SOP ex

Overview of the Study Unit

This study unit introduces a specific group of combinational logic circuits, namely the and-or-invert
ICs, which perform simple combinational logic circuit functions such as generating standard SOP
expressions.

Learning Outcomes of this Unit

After completing this study unit, you should be able to:
• Explain how the different combinational logic ICs can be used to simplify combinational
logic.

Assessment criteria for this unit

• The different types of and-or-invert ICs are explained.
• The functions of the different types of and-or-invert ICs are explained.
• And-or-invert ICs are connected to produce a Boolean expression.

7.1 Introduction
As you can recall from SOP expressions, their logic circuit consists of AND gates feeding into a
single OR gate, for example This is then referred to as AND-OR logic. Sometimes when applying
AOI (and-or-invert) gates, the SOP expressions are not in the standard form.

Because the SOP expressions are used so often, they have manufactured ICs that perform this
operation for us. This means that fewer ICs need to be used in logic circuits.

Old symbols for gates

To help you to understand the material introduced in this study unit, the old logic gates standards
 122 Chapter 7. And-or-invert (AOI) ICs for implementing SOP expressions

are introduced briefly, since the ICs use the old gate nomenclature.
Briefly, the AND gate is represented in figure 7.1 as follows:

Figure 7.1: AND gate Symbol

The OR gate is represented in figure 7.2 as:

Figure 7.2: OR gate Symbol

The NOT gate is represented in figure 7.3 as:

Figure 7.3: NOT gate Symbol

Apply this knowledge to the structure of the ICs.

7.2 The 74S64 4-WIDE 4-2-3-2 AOI

For more information about this section, kindly visit the following video clip:
https://www.youtube.com/watch?v=OOgkMXtR7VE

Logic expression for the 74S64

The logic expression for the 74LS64 is given in the following equation:
The layout of the gates inside the IC can clearly be seen from the Boolean expression. It consists of
four AND gates, one of them with 4 inputs, two with 2-inputs and the remaining one with three
inputs. All the AND gates are ORed together, which makes it a SOP expression, but the final output
is inverted because of the bar across the expression, as can be seen in figures 7.4 and 7.5. The IC
pin layers are shown in figure 7.6.
7.2 The 74S64 4-WIDE 4-2-3-2 AOI 123

Logic symbol for the 74S64

Figure 7.4: Logic symbol for the 74S64

Internal logic circuit for the 74S64

Figure 7.5: Internal logic circuit for the 74S64

Pin layout for the 74LS64

 124 Chapter 7. And-or-invert (AOI) ICs for implementing SOP expressions

Figure 7.6: IC 74LS64

7.3 THE 74LS54 4-WIDE 2-3-3-2 AOI

This IC consists of four AND gates, two with two inputs and two with three inputs in the sequence
as indicated 2-3-3-2.
Logic function for the 74LS54
The logic expression for the 74LS54 is given in the following equation:
Y = A.B +C.D.E + F.G.H + I.J
This expression clearly shows the layout of the gates inside the 74LS54 IC in figure 7.7.
The internal circuit is shown in figure 7.8.
The pin layout is shown in figure 7.9.
Logic symbol for the 74LS54

Figure 7.7: IC 74LS64

Internal logic circuit for the 74LS54

 7.4 The 74LS51 AND-OR-INVERT (AOI) GATES 125

Figure 7.8: Logic circuit 74LS54

Pin configuration of the 74S54

Figure 7.9: Pin configuration 74S54

7.4 The 74LS51 AND-OR-INVERT (AOI) GATES

The 74LS51 contains one 2-wide 3-input and one 2-wide 2-input and-or-invert gate. This IC has
two outputs, 1Y and 2Y, as shown in the logic expression for the 74LS51.

The two outputs are entirely independent of one another

Logic function for the 74LS51

126 Chapter 7. And-or-invert (AOI) ICs for implementing SOP expressions

The logic expression for the 74LS51 is given in the following two equations:

1Y = 1A.1B.1C + 1D.1E.1F
2Y = 2A.2B + 2C.2D
There are two outputs, which is why there are two expressions, 1Y and 2Y. The 1 or the 2 in front
of the variables give an indication of which output it is connected to. The expression clearly shows
you the layout of the gates inside the 74LS51 IC, as can be seen in figure 7.10, in the internal circuit
in figure 7.11, and the pin layout in figure 7.12.

Logic symbol for the 74LS51

Figure 7.10: Logic symbol 74LS51

Internal logic circuit of the 74LS51

Figure 7.11 shows the internal circuit diagram of the and-or-invert (AOI) 74LS51 ICs. Note
that they use a NOR gate for the outputs. This leads to the IC having an active LOW output. If we
want to affect an active high output, we must invert the output of the AOI. The 74LS51 can be used
to implement two SOP expressions.
 7.5 Summary 127

Figure 7.11: Logic circuit 74LS51

Pin layout for the 74LS51

Figure 7.12: Pin layout 74LS51

As you will see, these AOI devices have a limited application, but they are nevertheless useful for
small circuits.

7.5 Summary
AND-OR-Invert (AOI) logic and AOI gates are two-level compound (or complex) logic functions
constructed from the combination of one or more AND gates followed by a NOR gate. Construction
of AOI cells is particularly efficient using CMOS technology where the total number of transistor
gates can be compared to the same construction using NAND logic or NOR logic. The complement
of AOI Logic is OR-AND-Invert (OAI) logic where the OR gates precede a NAND gate.This study
unit studies the various common AOI Integrated ICs for logic gates and devices as studies in this
 128 Chapter 7. And-or-invert (AOI) ICs for implementing SOP expressions

module. Each time, the pinout of the considered IC is studied and you learn how to identify the
various pins of an IC.

7.6 Activity 7.1

Use the 74LS64 and show the connections to implement the Boolean expression:
f (A, B,C, D) = A.B̄.D̄ + A.B̄ + B.D +C: Show pin numbers on the logic symbol.
 8. FEEDBACK ON ACTIVITIES

8.1 ACTIVITY 1.1

tW = 2 ms, T = 4 ms
%duty cycle = ( tTW ) × 100 = ( 24 ms
ms ) × 100 = 50%

8.2 ACTIVITY 2.1

Append remainder to data. CRC is 101100100110

 130 Chapter 8. FEEDBACK ON ACTIVITIES

8.3 ACTIVITY 3.1

8.4 ACTIVITY 3.2

8.5 ACTIVITY 4.1

ĀB + ĀBC̄ + ĀBCD + ĀBC̄D̄E = ĀB(1 + C̄ +CD + C̄D̄E) = ĀB(1) = ĀB

8.6 ACTIVITY 4.2

X = ĀB̄C̄ + AB̄C̄ + ĀBC̄ + ABC̄

 8.7 ACTIVITY 5.1 131

8.7 ACTIVITY 5.1

X = ĀB + ĀCD + DBD̄

8.8 ACTIVITY 5.2

 132 Chapter 8. FEEDBACK ON ACTIVITIES

8.9 ACTIVITY 6.1

8.10 ACTIVITY 6.2

The sequence will be

016944480

8.11 ACTIVITY 7.1

As we can see, there are four product terms in the expression, therefore we can use all four AND
gates in the 74LS64 AOI IC. The first and third terms have one variable fewer than the number of
inputs that are available on the gates. This causes no problem; we simply need to reduce the inputs
on these particular gates. To reduce the inputs on an AND gate, the unused inputs can be connected
to the supply voltage.
8.11 ACTIVITY 7.1 133

Datasheet