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7.priority Encoderronak

The document outlines a practical assignment for designing an 8:3 priority encoder using VHDL at S.B. Jain Institute of Technology. It includes objectives, theory, steps for programming, VHDL code, a test bench, and applications of priority encoders. The conclusion emphasizes the importance of priority encoders in digital electronics for efficiently selecting the highest-priority active input.

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9 views5 pages

7.priority Encoderronak

The document outlines a practical assignment for designing an 8:3 priority encoder using VHDL at S.B. Jain Institute of Technology. It includes objectives, theory, steps for programming, VHDL code, a test bench, and applications of priority encoders. The conclusion emphasizes the importance of priority encoders in digital electronics for efficiently selecting the highest-priority active input.

Uploaded by

cajat99283
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital System Design (PCCET604P)

S. B. JAIN INSTITUTE OF TECHNOLOGY,MANAGEMENT &


RESEARCH,NAGPUR.

Practical No. 07

Aim: Design 8:3 priority Encoder using generate statement and also write test bench for
same.

Name of Student: _Ronak Wanjari_____________


Roll No.: _ET22036_____________
Semester/Year: __6th/3rd____________
Academic Session:__2024-25___________
Date of Performance:__________
Date of Submission: __________

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur


Digital System Design (PCCET604P)

AIM: Design 8:3 priority Encoder using generate statement and also write test bench for
same.

OBJECTIVE:

• Use the generate statement to implement a scalable 8:3 priority encoder, optimizing
the selection of the highest-priority bit while reducing redundant logic.
• Implement a parameterized priority encoder using the generate block, allowing
flexibility to extend the design to different input sizes in future applications.
• Develop a comprehensive testbench that applies various input combinations to verify
that the priority encoder correctly encodes the highest-priority bit.

SOFTWARE: - Xilinx Simulation Tool.

THEORY:-
A priority encoder is a digital combinational circuit that encodes multiple binary inputs into a
smaller number of output bits. Unlike a normal encoder, which assigns binary codes based on
input position, a priority encoder assigns priority to the highest-order active input (i.e., the
input with the highest index).
Functionality

• A priority encoder takes an n-bit input and produces a log₂(n)-bit output.


• If multiple inputs are active (1), the encoder outputs the position of the highest-
priority input.
• If no input is active, the output is typically set to zero or an invalid state.

8:3 Priority Encoder

An 8-to-3 priority encoder takes 8 input lines and produces a 3-bit output, encoding the
position of the highest-priority bit.

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur


Digital System Design (PCCET604P)

STEPS FOR PROGRAM:-

Step 1: Define Entity

• The entity defines the module name and its input/output ports.
• An 8-bit input (in_bits) and a 3-bit output (out_bits) are required.

Step 2: Architecture Declaration

• The architecture contains the logic to determine the highest-priority active input.
• Use if-elsif or case statements to implement priority logic.

Step 3: Implement Priority Logic

• The logic should check inputs from the highest (7) to the lowest (0) priority.
• If multiple inputs are active, the highest-priority input dictates the output.

Step 4: Test bench Creation

• A test bench applies different input values and verifies if the output matches
expectations.
• It includes stimulus processes, clock (if required), and monitoring of results.

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Priority_Encoder_8to3 is
Port (
in_bits : in STD_LOGIC_VECTOR(7 downto 0); -- 8-bit input
out_bits : out STD_LOGIC_VECTOR(2 downto 0) -- 3-bit encoded output
);
end Priority_Encoder_8to3;

architecture Generate_Arch of Priority_Encoder_8to3 is


signal temp_out : STD_LOGIC_VECTOR(2 downto 0) := "000";
begin

-- Generate loop to check highest priority bit


GEN_ENCODE: for i in 7 downto 0 generate
begin
process (in_bits)
begin
if in_bits(i) = '1' then

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur


Digital System Design (PCCET604P)

temp_out <= CONV_STD_LOGIC_VECTOR(i, 3); -- Convert index to 3-bit


output
end if;
end process;
end generate GEN_ENCODE;

TESTBENCH:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity TB_Priority_Encoder is
end TB_Priority_Encoder;

architecture Test of TB_Priority_Encoder is


signal in_bits : STD_LOGIC_VECTOR(7 downto 0);
signal out_bits : STD_LOGIC_VECTOR(2 downto 0);

-- Instantiate the Priority Encoder


component Priority_Encoder_8to3
Port ( in_bits : in STD_LOGIC_VECTOR(7 downto 0);
out_bits : out STD_LOGIC_VECTOR(2 downto 0));
end component;

begin
uut: Priority_Encoder_8to3 port map (in_bits => in_bits, out_bits => out_bits);

-- Stimulus process
process
begin
-- Apply test cases
in_bits <= "00000000"; wait for 10 ns; -- No active input
in_bits <= "00000001"; wait for 10 ns; -- Priority at bit 0
in_bits <= "00000100"; wait for 10 ns; -- Priority at bit 2
in_bits <= "10000000"; wait for 10 ns; -- Priority at bit 7
in_bits <= "01100000"; wait for 10 ns; -- Priority at bit 6 (highest)
in_bits <= "00010010"; wait for 10 ns; -- Priority at bit 4

wait; -- Stop simulation


end process;
end Test;

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur


Digital System Design (PCCET604P)

WAVEFORM:

RESULT:-

Applications of Priority Encoders

1. Interrupt Handling in Processors – Determines the highest-priority interrupt


request.
2. Data Compression – Reduces multiple inputs into a compact representation.
3. Digital Circuit Optimization – Reduces complexity in large systems by focusing on
significant signals.

Conclusion

A priority encoder is an essential component in digital electronics that efficiently selects the
highest-priority active input. It is widely used in digital systems where multiple signals need
to be prioritized for further processing.

DISCUSSION & VIVA VOCE

1) How does a priority encoder differ from a normal encoder?


2) What happens if multiple inputs are active simultaneously in a priority encoder?
3) What are some real-world applications of a priority encoder?
REFERENCE:
• VHDL Primer–J Bhasker –Pearson Education

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur

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