Digital System Design (PCCET604P)

S. B. JAIN INSTITUTE OF TECHNOLOGY,MANAGEMENT &

RESEARCH,NAGPUR.

Practical No. 08

Aim: Design 4 bit parallel adder using generate statement and verify the design using test
bench. (Use Generic and Generate statement)

Name of Student: __Ronak S. Wanari____________

Roll No.: __ET22036____________
Semester/Year: _6TH/3RD _____________
Academic Session:__2024-25___________
Date of Performance:__________
Date of Submission: __________

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur

 Digital System Design (PCCET604P)

AIM: Design 4 bit parallel adder using generate statement and verify the design using test
bench. (Use Generic and Generate statement)

OBJECTIVE:

• To verify the functionality of Full Adder.

• To design a digital system using Adder.
• To get familiar with Generate Statement.

SOFTWARE: - Simulation Tool.

THEORY:-

A single full adder performs the addition of two one bit numbers and an input carry. But
a Parallel Adder is a digital circuit capable of finding the arithmetic sum of two binary
numbers that is greater than one bit in length by operating on corresponding pairs of bits in
parallel. It consists of full adders connected in a chain where the output carry from each full
adder is connected to the carry input of the next higher order full adder in the chain. A n bit
parallel adder requires n full adders to perform the operation. So for the two-bit number,
two adders are needed while for four bit number, four adders are needed and so on. Parallel
adders normally incorporate carry look-ahead logic to ensure that carry propagation between
subsequent stages of addition does not limit addition speed.

Fig. 4 Bit Parallel Adder

STEPS FOR PROGRAM:-

Here's a step-by-step guide to design a 4-bit parallel adder using generate statements
in Verilog:

1.Define Inputs and Outputs: Declare the input signals A and B (both 4 bits wide), the
carry-in (Cin), and the output signals Sum (4 bits wide) and the carry-out (Cout).

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur

 Digital System Design (PCCET604P)

2. Generate the Full Adders: Use a generate statement to create four full adders, each
adding one bit of A, B, and the carry-in, and generating one bit of the sum and the
carry-out. Each full adder will have inputs A[i], B[i], Cin, and outputs Sum[i] and
Cout[i], where i ranges from 0 to 3.

3. Connect the Full Adders: Wire up the inputs and outputs of the full adders such that
each adder takes the corresponding bits of A, B, and carry-in, and produces the
respective sum and carry-out.

4. Top-Level Module: Define a top-level module that instantiates the 4-bit parallel
adder and connects it to the input and output ports.

A 1-bit full adder takes three inputs: two operands (a and b) and a carry-in (cin), and
produces two outputs: the sum and a carry-out (cout). The logic equations are:

• sum = a XOR b XOR cin

• cout = (a AND b) OR (b AND cin) OR (a AND cin)

Multiple full adders can be chained together to build an N-bit adder, where the carry-
out from one stage becomes the carry-in to the next.

The generate statement allows repeating a block of code with varying parameters. In the
context of a parallel adder:

• The generate block is used in the architecture section.

• A loop index (e.g., i) helps in selecting bits and mapping signals dynamically.
• The generate-for loop instantiates full adders for each bit of the operands.

VHDL CODE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity parallel_adder is
generic (
N : integer := 4 -- Width of the adder
);
Port (
a : in STD_LOGIC_VECTOR(N-1 downto 0);
b : in STD_LOGIC_VECTOR(N-1 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR(N-1 downto 0);
cout : out STD_LOGIC
);
end parallel_adder;

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur

 Digital System Design (PCCET604P)

architecture Structural of parallel_adder is

component full_adder
Port (
a : in STD_LOGIC;
b : in STD_LOGIC;
cin : in STD_LOGIC;
sum : out STD_LOGIC;
cout : out STD_LOGIC
);
end component;

signal carry : STD_LOGIC_VECTOR(N downto 0);

begin
carry(0) <= cin;

gen_adders: for i in 0 to N-1 generate

fa_inst : full_adder
port map (
a => a(i),
b => b(i),
cin => carry(i),
sum => sum(i),
cout => carry(i+1)
);
end generate;

TESTBENCH:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tb_parallel_adder is
end tb_parallel_adder;

architecture Behavioral of tb_parallel_adder is

constant N : integer := 4;

signal a : STD_LOGIC_VECTOR(N-1 downto 0);

signal b : STD_LOGIC_VECTOR(N-1 downto 0);
signal cin : STD_LOGIC;
signal sum : STD_LOGIC_VECTOR(N-1 downto 0);
signal cout : STD_LOGIC;

-- Component Declaration
component parallel_adder
generic (
N : integer := 4

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur

 Digital System Design (PCCET604P)

);
Port (
a : in STD_LOGIC_VECTOR(N-1 downto 0);
b : in STD_LOGIC_VECTOR(N-1 downto 0);
cin : in STD_LOGIC;
sum : out STD_LOGIC_VECTOR(N-1 downto 0);
cout : out STD_LOGIC
);
end component;

begin
uut: parallel_adder
generic map (N => N)
port map (
a => a,
b => b,
cin => cin,
sum => sum,
cout => cout
);
process
begin
-- Test Case 1
a <= "0001";
b <= "0010";
cin <= '0';
wait for 10 ns;

-- Test Case 2
a <= "1111";
b <= "0001";
cin <= '0';
wait for 10 ns;

-- Test Case 3
a <= "1010";
b <= "0101";
cin <= '1';
wait for 10 ns;

-- Test Case 4
a <= "1001";
b <= "1001";
cin <= '1';
wait for 10 ns;

wait;
end process;
end Behavioral;

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur

 Digital System Design (PCCET604P)

WAVEFORM:

RESULT:-

CONCLUSION:

DISCUSSION & VIVA VOCE

1) What is the purpose of using a generate statement in designing a four-bit parallel

adder?.
2) How many full adders are instantiated in the design of a four-bit parallel adder
using generate statements?
3) Explain how the inputs and outputs are connected in the full adders within the
generate statement.

REFERENCE:
• VHDL Primer–J Bhasker –Pearson Education

Department of Electronics and Telecommunication Engineering, S.B.J.I.T.M.R, Nagpur