Scribd
Upload
16 views4 pages

DLD Lab Report

The document outlines an experiment focused on understanding and building various types of 4-bit registers, including parallel-load, right-shift, left-shift, and universal registers using D flip-flops. It discusses the apparatus used, provides circuit diagrams, and highlights the importance of synchronized clocks and secure connections to avoid data errors. The experiment reinforced key principles of sequential logic design and timing trade-offs, with functional tests confirming expected outcomes despite some propagation delays.

Uploaded by

nazhatarannum090
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
16 views4 pages

DLD Lab Report

The document outlines an experiment focused on understanding and building various types of 4-bit registers, including parallel-load, right-shift, left-shift, and universal registers using D flip-flops. It discusses the apparatus used, provides circuit diagrams, and highlights the importance of synchronized clocks and secure connections to avoid data errors. The experiment reinforced key principles of sequential logic design and timing trade-offs, with functional tests confirming expected outcomes despite some propagation delays.

Uploaded by

nazhatarannum090
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 4

0112420465

Nazha Tarannum Roza

Nazha Tarannum
0112
Roza 420
465

NAZHA
Objectives:

● To learn how a basic 4-bit register, a shift register, and a multifunction register work.

● To join several 4-bit registers to make a larger storage unit.

● To design and build a 4-bit binary adder using simple logic gates.

Introduction:

Register: A register is made up of several flip-flops that each store one bit of digital data. By
linking many flip-flops together, you can store multiple bits at once. Registers act like a fast
memory inside the CPU, holding data and instructions that the processor needs immediately.

Parallel-load register: A register that captures and stores all bits in one go from a set of input
lines when a clock signal arrives. This lets you quickly load a whole data word (e.g., 4 bits) in a
single cycle rather than bit by bit.

Right-shift register: A register that, on each clock pulse, moves every stored bit one position
toward the least significant end (right). The bit vacated at the leftmost position is filled from an
external input, enabling serial data input or simple data manipulation.

Left-shift register: Similar to the right-shift version, but shifts every bit one position toward the
most significant end (left) on each clock. A new bit enters at the rightmost position, making it
useful for serial output or data alignment tasks.

Universal register: A versatile register design with control lines that let you choose between
parallel loading, shifting left, shifting right, or holding the current contents. By setting the control
signals, you can perform any of these operations in a single clock cycle, making it ideal for
flexible data handling.

Apparatus:
Table 1: Instrument Details
Name Specification Quantity

IC 7474 3

IC 74153 3

Circuit – 1

Wire 5V Multiple

Logisim Win-2.7.1 –
Experimental Details:

D - Flip Flop: A one-bit memory element that captures the input (D) on a clock edge and holds
it at its output (Q) until the next clock edge.

Table 2: Function Table of D- flip flop


Clk D D’ P P1 Q Q’

1 1 0 0 1 1 0

1 0 1 1 0 0 1

Figure 1: Gate Diagram of Figure 2: IC Pin Diagram of


D- flip flop D- flip flop

Circuit Diagram:

Figure 3: Parallel Load Register


Figure 4: Right Shift Register

Figure 5: Left Shift Register

Figure 6: Universal Shift Register

Discussion:
This experiment built a 4-bit multifunction register (parallel load, left/right shift, universal ops)
using D flip-flops and control logic. We found clock skew and loose mode-select wiring caused
occasional data errors, stressing the need for synchronized clocks and secure connections.
Functional tests matched the expected state table, though propagation delays capped our
maximum clock speed. Overall, this hands-on work reinforced key principles of sequential logic
design and timing trade-offs.

You might also like