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FPGA implementation of sobel edge detection algorithm

K. Navinkumar1, R. Logesh2, P. VishnuBabu3, A.V. Ananthalakshmi4,
1,2,3
Department of ECE, Puducherry Technological University, Puducherry, India.

Abstract

Sobel Edge detection algorithm is used to extract the edges (region of maximum variation) from an image. It is based on
the concept that the edges of an image contains maximum information whose computation depends on multipliers and
square root. As multipliers consume more logic, a modified sobel edge detection algorithm which does not employ
multipliers and square root function is proposed. A mathematical model of the proposed sobel edge algorithm was first
developed and MATLAB was used to verify the model. On comparing with the original model, the proposed model has a
SSIM of 96.43%. To analyse the hardware complexity, Verilog model of the modified sobel edge detection algorithm was
developed using Quartus II. The chosen evaluation board is Cylone III FPGA EP3C120F780. The performance metrics
such has Logic Elements utilization, Power dissipation and Maximum Operating Frequency were obtained. Open-Source
toolchain (Yosys, OpenVPR, and Google Skywater 130nm PDK) was used to obtain the RTL Netlist and Synthesis
reports. Verilog Modules for the Camera (CMOS OV7670) interface and FIFO Buffer were synthesized. The modified
algorithm was integrated with them. An HSMC (HSMB) breakout board was connected to the FPGA Development board
to increase the number of I/O ports. Thus in real time, the proposed modified Sobel Edge detection system can be used as a
pre-processor to reduce the amount of computations and power consumption.

Keywords: Sobel Algorithm, Edge Detection, Matlab, FPGA

Received on 3 May 2024, accepted on 2 September 2024, published on 23 October 2024

Copyright © 2024 Navinkumar et al., licensed to EAI. This is an open access article distributed under the terms of the CC BY-NC-
SA 4.0, which permits copying, redistributing, remixing, transformation, and building upon the material in any medium so long as
the original work is properly cited.

doi: 10.4108/eetiot.5148

*Corresponding author. Email: [email protected]

The Sobel edge detection algorithm is a method for

1. Introduction detecting edges in images by applying a set of
convolution filters to the image data. It is widely used in
Edge in an image contains the number of important image processing and computer vision applications,
parameters which is widely used in image analysis. Thus, particularly for detecting edges in grayscale images. It is
edge detection acts as a pre-processing in the analysis of relatively simple to implement and produces good results,
an image, image segmentation and in image feature but it can be sensitive to noise and may produce some
extraction. Some of the widely employed edge detection false edges. It can be implemented on both a GPU
algorithms are Robert, Prewit, LOG, Canny, Sobel and (graphics processing unit) and an FPGA. Both
other algorithms all belong to spatial detection [1]. Of the implementations can provide significant performance
above mentioned, Robert and Prewit has low edge improvements over a CPU-based implementation,
positioning accuracy. LOG operators cannot identify the particularly for large or complex images. Ultimately, the
direction of edges and are sensitive to noise. Canny choice between a GPU and an FPGA for the Sobel edge
operators have superior functions but are complex to detection algorithm will depend on the specific
implement [2]. It is difficult to use them in realtime requirements of the application. A GPU may be more
hardware systems. Although traditional Sobel algorithms suitable for tasks that require high-performance graphics
need to manually specify detection thresholds, they have processing or that can be parallelized, while an FPGA
the advantages of simple detection principle and easy may be more suitable for tasks that require custom
hardware implementation. hardware acceleration or real-time processing. Thus the

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K. Navinkumar et al.

proposed modified sobel edge algorithm will be device hardware resources.

implemented using FPGA. Thus OpenCL is not
preferred to program
The organization of the paper is as follows:- Section 2 FPGAs.
elaborates on the literature survey, section 3 discusses the [15] 2020 FPGA Fastens the
methods employed in the proposed work. Section 4 performing processes
discusses the results and finally section 5 concludes the and has reduced the
paper. spatial complexity of
the FPGA with
increase in hardware
2. Related Works resource.
[16] 2021 Software Instead of employing
Several works were reported on the implementation of platform the hardware
sobel edge detection algorithm using different platforms employed accelerator, software
as shown in Table 1. (MATLAB) based method is
employed using
Standard C, AVX
intrinsics and
OpenMP
Table 1. Related Works directives. Software
development time is
reduced at the cost of
Related Year Platform Inference latency.
Works Used
[17] 2021 FPGA Edge detected image
[3] 2007 FPGA Complex in hardware cannot be obtained
architecture completely and the
[4] 2008 FPGA Complex in hardware time and space
architecture complexity are high.
[5] 2012 FPGA Suffers from space No open-source
and time complexity implementation.
[6] 2013 FPGA Complex in hardware [18] 2022 MATLAB Increased the
architecture and hardware resource as
[7] 2014 FPGA Complex in hardware OpenCV, well as the time delay
architecture Xilinx gets affected. Also
[8] 2014 GPU FPGA FPGA has increased
(NVIDIA implementation is the performance
GeForce speed efficient than when compared to
310) & GPU. software method.
Xilinx
Virtex-5
From the literature survey, it is inferred that FPGA
FPGA
implementation of sobel algorithm offers very good
device
performance when compared to software based methods.
[9] 2017 FPGA Complex in hardware
The works proposed using FPGA either it has increased
architecture
the hardware complexity or it has increased the time
[10] 2018 FPGA Complex in hardware complexity. Further, there is no open source
architecture implementation. The motivation of the proposed work is
[11] 2018 Xilinx Reduced the number to increase the speed and minimize the power
Spartan 6 of resources and consumption by making the hardware architecture
FPGA space complexity simpler.
with higher clock
rate than the work
proposed in [5] 3. Methodology
[12] 2018 FPGA No open source
implementation An FPGA implementation of the Sobel algorithm
[13],[14] 2015, OpenCL Shows significant typically consists of a set of convolution filters, a gradient
2018 software on improvement in computation unit, and a thresholding unit. To implement
Intel Terasic performance by the convolution filters, the Sobel algorithm requires a set
DE5 target employing pipelining of shift registers and a set of multipliers. The shift
FPGA but at the cost of registers are used to store the image data and shift it

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 FPGA implementation of sobel edge detection algorithm

through the filters, while the multipliers are used to

perform the convolution operation. The filters can be
implemented as hardwired logic or as programmable
functions, depending on the specific requirements of the
application. The gradient computation unit combines the
results of the horizontal and vertical filters to produce the
gradient image. This unit may include a set of adders,
subtractors, and absolute value units to compute the
gradient magnitude and direction. The thresholding unit is
used to highlight the edges of interest by applying a Figure 2. Proposed sobel algorithm
threshold to the gradient image. This unit may include a
comparator and a register to store the threshold value.
Figure 1 shows the Sobel Kernels. 3.2 Matlab Simulation Flowchart

Figure 3 shows the flowchart of the MATLAB

Simulation. The necessary in-built functions are imported
as needed. It is done for both the existing and proposed
model for various scenarios. The results are then
compared.

Figure 1. Sobel Kernels

In earlier works reported so far, sobel filter has been

implemented with the use of multipliers and square root
operation for the kernel convolution. While this might be
available in higher end FPGAs, it is not always viable to
include these operations in all implementations. The Figure 3. Matlab Simulation Flowchart
proposed work aims to eliminate these two operations. A
high similarity index is also achieved by eliminating the 3.3 Verilog Implementation Flowchart
multiplier and square root.
Figure 4 shows the Verilog implementation of the
Also with the move towards the open-source hardware, proposed Sobel algorithm. It is a pipelined
there is a dire need of open source implementations of implementation. Pipelined design is a technique that is
many systems. Till date, there is not much work in open- used to improve the performance of digital circuits by
source hardware implementation of sobel filter. Closed- breaking a complex operation into smaller stages and
source hardware is proprietary to the company or executing them in parallel. In Verilog, pipelined design
individual who owns it and is not publicly available. It is can be implemented by creating a pipeline of stages, each
typically distributed under a license that grants users the of which performs a specific operation on the data.
right to use the hardware but not to modify or distribute
the source code or design files.

3.1 Mathematical Description of the Proposed

Sobel Algorithm

Let Sx and Sy be the matrices obtained after applying the

kernel convolution. Some of the entries will contain
negative values. To remove these values, magnitude is
taken by applying first multiplying the matrix (dot Figure 4. Verilog Implementation Flowchart
product) and then applying the square root operation.

Instead of this, a simple sign reversal is used to remove To implement pipelined design in Verilog, a combination
the negative signs and then they are added together. This of registers and combinational logic can be used. Each
is then repeated for the entire image. This has been stage performs a specific operation on the data and then
explained in Figure 2. passes the result to the next stage. The stages are
connected by registers, which hold the data as it moves
through the pipeline.

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3.4. Real-Time Implementation of the The Cyclone III FPGA core has two parts working in
Proposed Sobel algorithm using Cyclone different clock domains. The camera module continuously
III FPGA senses and sends the data to the camera interface module.
It is then interfaced with the Sobel Unit using a FIFO
The requirements for the real time implementation are: buffer. It allows the data to be read in the same order in
• Live feed from an input source which it is inserted. The results are then stored in the
• Input source – can be a camera (OV7670) or RAM module. PLL is used to provide the necessary
from PC through UART Module clocks from the on-board oscillator. The specification
• Need a buffer for read and write operations. sheets should be referred to know the frequency of
• On-board SRAM insufficient. operation of various peripherals.
• SDRAM – For holding the data temporarily
• FIFO Buffer for interfacing modules with The orange coloured regions depict the domain, which
different speeds works in 24 MHz clock domain. The blue is for 166.67
MHz clock domain. The camera works in I2C mode.
The OV7670 is a low-power CMOS image sensor
designed for use in portable devices such as mobile PHY is the physical layer of the SDRAM Controller. An
phones, laptops, and digital still cameras. It is a VGA FSM based design is used. The IP is obtained from the
(640x480) resolution image sensor that can operate at up megacore function wizard of Quartus II. While creating
to 60 frames per second and is capable of capturing high- the IP, specifications such as the frequency, burst mode,
quality images and video in a wide range of lighting frames, error correction mode must be set properly in
conditions. The OV7670 includes on-chip image accordance with datasheet of the SDRAM DDR2
processing functions, such as color interpolation, gamma controller.
correction, and white balance, which can improve the
quality of the captured images. The OV7670 has good
low light sensitivity, allowing it to capture good-quality
images in low light conditions.

SDRAM DDR2 module is the most challenging part of

the real-time implementation. To interface an FPGA
(field-programmable gate array) with DDR2 SDRAM,
design and implement a memory controller that can 4. Results and Discussion
handle the communication between the FPGA and the
SDRAM. The memory controller is responsible for
managing the transfer of data between the FPGA and the Three samples were chosen to compare the existing and
SDRAM, as well as handling the timing and control the proposed model. Figure 6, shows the MATLAB
signals required for the SDRAM to operate correctly. simulation results for the given sample. From the
simulation results, it is inferred that the outputs of the
The PLL circuit includes a phase detector and a low-pass proposed Sobel model is virtually indistinguishable from
filter. The phase detector compares the input clock with the output of the existing sobel model.
the output clock and generates a feedback signal based on
the phase difference between the two clocks. The low-
pass filter filters the feedback signal and generates the
output clock. The proposed sobel algorithm is
implemented using Cyclone III FPGA as shown in Figure
5.

Figure 6. MATLAB Comparison of the Proposed and

the Existing Sobel Model

A similarity index of 96.43% has been achieved with the

proposed model in comparison with the existing model.
Figure 7 shows the Quartus II RTL netlist of the proposed
sobel model.

Figure 5. Proposed sobel edge architecture using

Cyclone III FPGA

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 FPGA implementation of sobel edge detection algorithm

number of logic elements used. The thermal power

dissipation remains the same in both the models. However
the proposed sobel algorithm operates at a higher speed
than the existing sobel algorithm.

4.2 Real Time implementation results of the

Proposed sobel Algorithm using the open source
YOSYS tool

Real time implementation of the proposed sobel algorithm

has been carried out by interfacing camera with Cyclone
III FPGA module using the open source YOSYS tool.
Figure 11 shows the YOSYS RTL netlist.

Figure 7. Quartus II RTL netlist view

4.1 Performance Metrics of the Proposed and the

Existing Sobel Algorithm Figure 11. YOSYS RTL netlist

The performance metrics chosen are number of logic Figure 12 shows the DDR2 SDRAM RTL netlist.
elements, total thermal power dissipation, maximum
frequency of operation and the number of multipliers
used. Figure 8 shows the number of logic elements
utilized in the existing and in the proposed work.

Figure 8. Comparison of the hardware complexity

Figure 9 compares the thermal power dissipation in the

existing and in the proposed work.

Figure 12. DDR2 SDRAM RTL netlist

Figure 9. Thermal Power dissipation comparison Figure 13 shows the real time implementation RTL netlist
of the proposed sobel algorithm by interfacing the camera
Figure 10 shows the maximum frequency of operation in module with Cyclone III FPGA.
the existing and in the proposed work.

Figure 10. Maximum frequency of operation

comparison

From Figures 8, 9 and 10, it is inferred that the proposed Figure 13. RTL Netlist of the proposed sobel edge
work has completely eliminated the use of multiplier. algorithm
However this has led to the slight increase 21.62% in the

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