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This VHDL code defines a 7-segment display decoder entity named 'sseg_dec' that takes an 8-bit input and outputs signals to control the display. It includes a clock signal for counting and a process to decode the lower 4 bits of the input into the corresponding 7-segment display representation. The decoder activates only the first digit of the display and handles input values from 0 to 9, providing a blank output for other values.

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ahmedkarcum
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6 views1 page

4

This VHDL code defines a 7-segment display decoder entity named 'sseg_dec' that takes an 8-bit input and outputs signals to control the display. It includes a clock signal for counting and a process to decode the lower 4 bits of the input into the corresponding 7-segment display representation. The decoder activates only the first digit of the display and handles input values from 0 to 9, providing a blank output for other values.

Uploaded by

ahmedkarcum
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sseg_dec is
Port (
clk : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(7 downto 0);
an : out STD_LOGIC_VECTOR(3 downto 0);
seg : out STD_LOGIC_VECTOR(6 downto 0)
);
end sseg_dec;

architecture Behavioral of sseg_dec is


signal count : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal digit : STD_LOGIC_VECTOR(3 downto 0);
begin

process(clk)
begin
if rising_edge(clk) then
count <= count + 1;
end if;
end process;

-- Sadece 1. basamağı aktif et


an <= "1110";

-- data_in(3 downto 0)'ı göster


digit <= data_in(3 downto 0);

process(digit)
begin
case digit is
when "0000" => seg <= "1000000"; -- 0
when "0001" => seg <= "1111001"; -- 1
when "0010" => seg <= "0100100"; -- 2
when "0011" => seg <= "0110000"; -- 3
when "0100" => seg <= "0011001"; -- 4
when "0101" => seg <= "0010010"; -- 5
when "0110" => seg <= "0000010"; -- 6
when "0111" => seg <= "1111000"; -- 7
when "1000" => seg <= "0000000"; -- 8
when "1001" => seg <= "0010000"; -- 9
when others => seg <= "1111111"; -- blank
end case;
end process;

end Behavioral;

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