COMBINATIONAL LOGIC CIRCUIT + Acombinational circuit consists of logic gates whose outputs at any time are determined from only the present combination of inputs. ‘* A combinational circuit performs an operation that can be specified logically by a set of Boolean functions. ‘+ It consists of an interconnection of logic gates. Combinational logic gates react to the values of the signals at their inputs and produce the value of the output signal, transforming binary information from the given input data to a required output data. ‘* Ablock diagram of a combinational circuit is shown in the below figure. ‘* The n input binary variables come from an extemal source; the m output variables are produced by the internal combinational logic circuit and go to an extemal destination. ‘+ Each input and output variable exists physically as an analog signal whose values are interpreted to be a binary signal that represents logic 1and logic 0. Combinational BINARY ADDER-SUBTRACTO Digital computers perform a variety of information-processing tasks. Among the functions encountered are the various arithmetic operations. ‘+ The most basic arithmetic operation is the addition of two binary digits. This simple addition consists of four possible elementary operations: 0+ 0=0,0+1=1,1+0=1, and 1+1= 10. ‘+The first three operations produce a sum of one digit, but when both augend and addend bits are equal to 1; the binary sum consists of two digits. The higher significant bit of this result is called a carry. ‘+ When the augend and addend numbers contain more significant digits, the cary obtained from the addition of two bits is added to the next higher order pair of significant bits. A combinational circuit that performs the addition of two bits is called a half adder. ‘One that performs the addition of three bits (two significant bits and a previous carry) is a full adder. The names of the circuits stem from the fact that two half adders can be employed to implement a full adder. HALF ADDER: This circuit needs two binary inputs and two binary outputs. The input variables designate the augend and addend bits; the output variables produce the sum and carry. Symbols x and y are assigned to the two inputs and S (for sum) and C (for carry) to the outputs. ‘* The truth table for the half adder is listed in the below table. ‘© The C output is 1 only when both inputs are 1. The S output represents the least significant bit of the sum, «The simplified Boolean functions for the two outputs can be obtained directly from the truth table. x y Do B o ofo o o 1 1 o 1 of 2 0 a 1fo a Truth Table + The simplified sum-of-products expressions are S=xyty C=xy ‘+ The logic diagram of the half adder implemented in sum of products is shown in the below figure. It can be also implemented with an exclusive-OR and an AND gate.FULL ADDER:- ‘* full adder is a combinational circuit that forms the arithmetic sum of three bits. ‘+ It consists of three inputs and two outputs. Two of the input variables, denoted by x and y , represent the two significant bits to be added. The third input, z , represents the carry from the previous lower significant position. Truth Table ‘+ Two outputs are necessary because the arithmetic sum of three binary digits ranges in value from 0 to 3, and binary representation of 2 or 3 needs two bits. The two outputs are designated by the symbols S for sum and C for carry. a a —— \_wo oo no oo no im G@)S = xy'e 4 rye bay’ byt (b) Caay tart ys K-Map for full adder . + The binary variable S gives the value of the least significant bit of the sum. The binary variable C gives the output carry formed by adding the input carry and the bits of the words. ‘* The eight rows under the input variables designate all possible combinations of the three variables. The output variables are determined from the arithmetic sum of the input bits. When all input bits are 0, the output is 0. ‘* The S output is equal to 1 when only one input is equal to 1 or when all three inputs are equal to 1. The C output has a carry of 1 if two or three inputs are equal to 1 «The simplified expressions are S= xyz + xyz! + xy'2' +2Caxytxetyz ‘© The logic diagram for the full adder implemented in sum-of-products form is shown in figure. tO » Poo 3={ implementation of Full Adder in SOP form + Itcan also be implemented with two half adders and one OR gate as shown in the figure. Half Adder 2Oy9 r ' t ip oe eazy Implementation of Full Adder using Two Half Adders and an OR gate ‘*__Afull adder is a combinational circuit that forms the arithmetic sum of three bits. BINARY ADDER:- ‘* Abinary adder Is a digital circuit that produces the arithmetic sum of two binary numbers. ‘+ It'can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of the next full adder in the chain. * Addition of n-bit numbers requires a chain of n full adders or a chain of one-half adder and n-1 full adders. In the former case, the input carry to the least significant position is fixed at 0. ‘+ The interconnection of four full-adder (FA) circuits to provide a four-bit binary ripple camry adder is shown in the figure. ‘+ The augend bils of A and the addend bits of B are designated by subscript numbers from right to lef, with subscript 0 denoting the least significant bit. ‘+The carries are connected in a chain through the full adders. The input carry to the adder is CO, and it ripples through the full adders to the output carry C4. The S outputs generate the required sum bits. + An n-bit adder requires n full adders, with each output carry connected to the input carry of the next higher order full adder. + Consider the two binary numbers A = 1011 and 8 = 0011. Their sum S = 1110 is formed with the four- bit adder as follows:Subscript EE a ee) Input carry 9 1 1 0 G Augend Poo 1 1 4 Addend 0 o 1 1 B Sum 1 1 1 oO S Output carry 0 Oo tf 1 Ga «The bits are added with full adders, starting from the least significant position (subscript 0), to form the sum bit and carry bit. The input carry Co in the least significant position must be 0. + The value of Cs in a given significant position is the output carry of the full adder. This value is transferred into the input carry of the full adder that adds the bits one higher significant position to the left. + The sum bits are thus generated starting from the rightmost position and are available as soon as the corresponding previous carry bit is generated. All the carries must be generated for the correct sum bits to appear at the outputs. Lh ti it ti 24 | | fo Four Bit Binary Adder HALF SUBTRACTOR:- «This circuit needs two binary inputs and two binary outputs. Symbols x and y are assigned to the two inputs and D (for difference) and B (for borrow) to the outputs. The truth table for the half subtractor is listed in the below table. eos cona]a Truth Table + The B output is 1 only when the inputs are 0 and 1. The D output represents the least significant bit of the subtraction. ‘The subtraction operation is done by using the following rules as with borrow 1; ‘+ The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The simplified sum-of-products expressions are D=xy+xy and BaxyD=x6y any ‘+ The logic diagram of the half adder Implemented in sum of products Is shown In the figure. It can be also implemented with an exclusive-OR and an AND gate with one inverted input EULL SUBTRACTOR:- Aull subtractor is a combinational circuit that forms the arithmetic subtraction operation of three bits. + It consists of three inputs and two outputs. Two of the input variables, denoted by x and y , represent the two significant bits ta be subtracted. The third input, z , is subtracted from the result Of the first subtraction. < jo jo Truth Table * Two outputs are necessary because the arithmetic subtraction of three binary digits ranges in value from 0 to 3, and binary representation of 2 or 3 needs two bits. The two outputs are designated by the symbols D for difference and B for borrow. ‘+The binary variable D gives the value of the least significant bit of the difference. The binary variable B gives the output borrow formed during the subtraction process. ye —— »~ —— 2 oo oO W 10 7 oo on u to 0 1 1 x{if 1 1 : D= xy exe txy'2'ye B= x'zex'yeyz K-Map for full Subtractor ‘+ The eight rows under the input variables designate all possible combinations of the three variables. The output variables are determined from the arithmetic subtraction of the input bits. «The difference D becomes 1 when any one of the input is ‘or all three inputs are equal tot and the borrow B is 1 when the input combination is (0 0 1) or (0 1 0) or (0 4 1) or(1 1 1). «The simplified expressions are D= xyz + xyz! + xyz’ + xyz Bexztxy+yz + The logic diagram for the full adder implemented in sum-of-products form is shown in figure.Poo Implementation of Full Subtractor in SOP form MAGNITUDE COMPARATOR:- ‘A magnitude comparator is a combinational circuit that compares two numbers A and B and determines their relative magnitudes. The following description is about a 2-bit magnitude comparator circuit. The outcome of the comparison is specified by three binary variables that indicate whether A < B, A= B,orA>B. Consider two numbers, A and B, with two digits each. Now writing the coefficients of the numbers in descending order of significance: B= B, By ‘The two numbers are equal if all pairs of significant digits are equal Le. if and only if A1 = B1, and AO = Bo, When the numbers are binary, the digits are either 1 or 0, and the equality of each pair of bits can be expressed logically with an exclusive-NOR function as X1SA,By+AVBy And x0=AgBy+Ao'Bo’ The equality of the two numbers A and 8 is displayed in a combinational circuit by an output binary variable that we designate by the symbol (A = B). This binary variable is equal to 1 if the input numbers, A and B , are equal, and is equal to 0 otherwise. For equality to exist, all xi variables must be equal to 1, a condition that dictates an AND operation of all variables: (A=B) = xix The binary variable (A = B) is equal to 1 only if all pairs of digits of the two numbers are equal. To determine whether A is greater or less than B, we inspect the relative magnitudes of pairs of significant digits, starting from the most significant position. If the two digits of a pair are equal, we compare the next lower significant pair of digits. If he corresponding digit of Ais 1 and that of B Is 0, we conclude that A > B. If the corresponding digit of A is 0 and that of B is 1, we have A < B. The ‘sequential comparison can be expressed logically by the two Boolean functions. (A> B) = ABr'+x:AgB'o (AB | A By 5 (A=B) Logic Diagram of 2-bit Magnitude ComparatorDECODER:- ap a Dy D, p, EA BY] Do Di Dr Ds 1x xprradig oo of orig yn 8 O1f to1d » or oft rod or rfprraig Addecoder is a combinational circuit that converts binary information from n input lines to a maximum of 2" unique output lines. If the n -bit coded information has unused combinations, the decoder may have fewer than 2n outputs. The decoders presented here are called n -1o- m-line decoders, where m... 2n. Their purpose is to generate the 2n (or fewer) minterms of n input variables. Each combination of inputs will assert a unique output. The name decoder is also used in conjunction with other code converters, such as a BCD-to-seven-segment decoder. Consider the three-to-eight-ine decoder circuit of three inputs are decoded into eight outputs, each representing one of the minterms of the three input variables. The three inverters provide the complement of the inputs, and each one of the eight AND gates generates one of the minterms. The input variables represent a binary number, and the outputs represent the eight digits of a number in the octal number system. However, a three-to-eight-line decoder can be used for decading any three-bit code to provide eight cutputs, one for each element of the code. ‘Atwo-to-four-tine decoder with an enable input constructed with NAND gates is shown in Fig. The circuit operates with complemented outputs and a complement enable input. The decoder is enabled when E is equal to 0 (Le., active-low enable). As indicated by the truth table, only one output can be equal to 0 at any given time; all other outputs are equal to 1. The output whose value is equal to 0 represents the minterm selected by inputs A and B. The circuit is disabled when E is equal to 1, regardless of the values of the other two inputs. ‘When the circuit is disabled, none of the outputs are equal to 0 and none of the minterms are selected. In general, a decoder may operate with complemented or un-complemented outputs. ‘The enable input may be activated with a 0 or with a 1 signal Some decoders have two or more enable inputs that must satisfy a given logic condition in order to enable the circuit. A decoder with enable input can function as a demuttiplexer—a circuit that receives information from a single line and directs it to one of 2n possible output lines. The selection of a specific output is controlled by the bit combination of n selection lines. ‘The decoder of Fig. can function as a one-to-four-line demultiplexer when E Is taken as a data input line and A and B are taken as the selection inputs, The single input variable E has a path to all four outputs, but the input information is directed to only ‘one of the output fines, as specified by the binary combination of the two selection lines A and B . This feature can be verified from the truth table of the circuit For example, if the selection lines AB = 10, output D, will be the same as the input value E, while all other outputs are maintained at 1. Since decoder and demultiplexer operations are obtained from the same circuit, a decoder with an enable input is referred to as a decoder — demultiplexer. Application of this decoder is binary-to-octal conversionENCODER: + Anencoder is a digital circuit that performs the inverse operation of a decoder. * Anencoder has 2n (or fewer) input lines and n output lines. + The output lines, as an aggregate, generate the binary code corresponding to the input value. Inputs Outputs DD, Dy Dy Dy Dy De Dy xy 2 1 0 0 0 0 0 0 o 0 0 Oo o 1 0 0 0 0 oO O 0 0 1 o o 1 0 0 0 0 © o 1 0 o o 0 1 0 oO 0 oO oo rot o o 0 Oo 1 0 0 0 1 9 Oo o o 0 0 O 1 0 © 1 0 1 o o 0 © © o 1 0 1 1 0 o 0 0 60 0 o 0 1 1 1 1 * The above Encoder has eight inputs (one for each of the octal digits) and three outputs that generate the corresponding binary number. Itis assumed that only one input has a value of 1 at any given time. ‘The encoder can be implemented with OR gates whose inputs are determined directly from the truth table Output z is equal to 1 when the input octal digit is 1, 3, 5, or 7. Output y is 1 for octal digits 2, 3, 6, or 7, and output x is 1 for digits 4, 5, 6, of 7. + These conditions can be expressed by the following Boolean output functions: z= Dy +D3;+Ds+Dr Dz + D3 +D5+D; = Dy + Ds + Dg+ Dy «The encoder can be implemented with three OR gates. + The encoder defined above has the limitation that only one input can be active at any given time, H two inputs are active simultaneously, the output produces an undefined combination * To resolve this ambiguity, encoder circuits must establish an input priority to ensure that only one Input is encoded which is done in the Priority Encoder PRIORITY ENCODE! + Apriority encoder is an encoder circuit that includes the priority function. * The operation of the priority encoder is such that if two or more inputs are equal to 1 at the same time, the input having the highest priority will take precedence. Inputs Outputs Do Di Dz Dy xy V o 0 0 0 x x 0 1 0 0 oO oo 1 x 1 0 0 oor. x x 1.0 1 0 1 x x x 1 hot 2 * In addition to the two outputs x and y , the circuit has a third output designated by V; this is a valid bit indicator that is set to 1 when one or more inputs are equal to 1.{all inputs are 0, there is no valid input and V is equal to 0. The other two outputs are not inspected when V equals 0 and are specified as don't-care conditions. Here X's in output columns represent don't-care conditions, the X 's in the input columns are useful for Tepresenting a truth table in condensed form. ——_Inputs Outputs Dy Diz Ds xy V 0 0 0 0 x x 0 1 0 0 0 0 oO 1 x 1 0 0 0 1 1 x x 1 oO 1 o 1 x x x 1 a 1 1 Higher the subscript number, the higher the priority of the input. Input D3 has the highest priority, so, regardless of the values of the other inputs, when this input is 1, the output for xy is 11 (binary 3). If D2 = 1, provided that D3 = 0, regardless of the values of the other two lower priority inputs the output is 10. The output for D1 is generated only if higher priority inputs are 0, and so on down the priority levels. Ds Ds Did, DDN” wo on n 10 my rs of x [fr [7 DiDy DPN o_o oof x | fpr o 1 off [fal p os 10 = 4] eG Ce Te ] a TT me eT " 1 Py a aff rp py) ttt Del be a pe 10 1 10) a fa Dy Ds x= D:+Dy Y= D+ DD, ‘The maps for simplifying outputs x and y are shown in above Fig The minterms for the two functions are derived from its truth table. Although the table has only five rows, when each X in a row is replaced first by 0 and then by 1, we obtain all 16 possible input combinations. For example, the fourth row in the table, with inputs XX10, represents the four minterms 0010, 0110, 1010, and 1110. The simplified Boolean expressions for the priority encoder are obtained from the maps. The condition for output V is an OR function of all the input variables. The priority encoder is implemented according to the following Boolean functions: s+ D; Dz 0+ Di + D2 + DsDo MULTIPLEXE! ‘A multiplexer is @ combinational circuit that selects binary information from one of many input lines and directs it to a single output line, ‘+ The selection of a particular input line is controlled by a set of selection lines. + Normally, there are 2° input lines and n selection lines whose bit combinations determine which input is selected. «A four-to-one-line multiplexer is shown in the below figure. Each of the four inputs, Io through Is, is applied to one input of an AND gate. + Selection lines S: and S2 are decoded to select a particular AND gate. The outputs of the AND gates are applied to a single OR gate that provides the one-line output. ‘The function table lists the input that is passed to the output for each combination of the binary selection values. ‘To demonstrate the operation of the circuit, consider the case when S,S0= 10. + The AND gate associated with input |, has two of its inputs equal to 1 and the third input connected to hy + The other three AND gates have at least one input equal to 0, which makes their outputs equal to 0. The output of the OR gate is now equal to the value of Iz, providing a path from the selected input to the output. + A multiplexer Is also called a data selector, since it selects one of many inputs and steers the binary information to the output line. 4x1 MUX 0 F (b) Multiplexer implementationmone Truth table Logic diagram DEMULTIPLEXER:- * The data distributor, known more commonly as a Demultiplexer or “Demux” for short, is the exact opposite of the Multiplexer. * The demultiplexer takes one single input data line and then switches it to any one of a number of individual output lines one at a time. The demultiplexer converts a serial data signal at the input to a Parallel data at its output lines as shown below. * The Boolean expression for this 1-0-4 demultiplexer above with outputs A to D and data select lines a, bis given as: F = (@b)A+a'bB + ab'C + abD * The function of the demultiplexer is to switch one common data input line to any one of the 4 output data lines A to D In our example above. As with the multiplexer the individual solid state switches are selected by the binary input address code on the output select pins “a” and “b" as shown. T}— A F 12 o re utput trot | 2 3f-—pLogie Dlagram Unlike multiplexers which convert data from a single data line to multiple lines and demultiplexers which convert multiple lines to a single data line, there are devices available which convert data to and from multiple lines and in the next tutorial about combinational logic devices. Standard demultiplexer IC packages available are the TTL 74LS138 1 to 8-output demultiplexer, the TTL 74LS139 Dual 1-to-4 output demultiplexer or the CMOS CD4514 1-to-16 output demultiplexer. Outaut Select Data output Selected Truth Table